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JPS56112742A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56112742A
JPS56112742A JP1625980A JP1625980A JPS56112742A JP S56112742 A JPS56112742 A JP S56112742A JP 1625980 A JP1625980 A JP 1625980A JP 1625980 A JP1625980 A JP 1625980A JP S56112742 A JPS56112742 A JP S56112742A
Authority
JP
Japan
Prior art keywords
oxide film
film
injected
silicon nitride
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1625980A
Other languages
Japanese (ja)
Inventor
Shigenobu Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1625980A priority Critical patent/JPS56112742A/en
Publication of JPS56112742A publication Critical patent/JPS56112742A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a high density semiconductor integrated circuit having small stepwise unevenness on the surface by employing a semiconductor substrate part under an oxide film as an active region. CONSTITUTION:A protective oxide film 2 and a silicon nitride film 3 are sequentially formed on a P type semiconductor substrate 1, the silicon nitride film is selectively removed, and phosphorus or arsenic ions are injected to dope it. Then, an oxide film 5 is formed by a selective oxidation, and an element forming N type region 4 is formed. With the film 5 as a mask P type impurity ion is injected, and an injection region 6 is thus formed. Thereafter, the films 5, 3 and 2 are removed on the substrate, the entire surface of the wafer is then oxidized, and a field oxide film 7 and a channel stopper 6 are formed thereon. Thus, it can improve the wire disconnection preventing effect. It can also increase the integrity by forming a channel stopper by a self-alignment.
JP1625980A 1980-02-12 1980-02-12 Manufacture of semiconductor device Pending JPS56112742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1625980A JPS56112742A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1625980A JPS56112742A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56112742A true JPS56112742A (en) 1981-09-05

Family

ID=11911556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1625980A Pending JPS56112742A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56112742A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106142A (en) * 1983-11-15 1985-06-11 Nec Corp Manufacture of semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106142A (en) * 1983-11-15 1985-06-11 Nec Corp Manufacture of semiconductor element

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