JPS5597709A - Analog signal amplifier circuit - Google Patents
Analog signal amplifier circuitInfo
- Publication number
- JPS5597709A JPS5597709A JP627579A JP627579A JPS5597709A JP S5597709 A JPS5597709 A JP S5597709A JP 627579 A JP627579 A JP 627579A JP 627579 A JP627579 A JP 627579A JP S5597709 A JPS5597709 A JP S5597709A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- analog signal
- led
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE:To improve the SN ratio of an analog signal amplifier circuit by exercising switching control by a control signal synchronizing with an input signal over a switching circuit, which varies in impedance, provided in parallel to the output load of the amplifier. CONSTITUTION:Analog signal Va is periodically sent out from signal source 1 and led to one input of differential amplifier 2, where it is compared with reference voltage REF supplied to the other input to output a binary signal showing their magnitude relation. The output of differential amplifier 2 is supplied to level converter 3 and also led to switching circuit 4 by being branched, and the output of level converter 3 is led to the output terminal by way of latch circuit 5. Signal source 1, level converter 3, switching circuit 4, and latch circuit 5 are all supplied with synchronizing clock signals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP627579A JPS5597709A (en) | 1979-01-22 | 1979-01-22 | Analog signal amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP627579A JPS5597709A (en) | 1979-01-22 | 1979-01-22 | Analog signal amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5597709A true JPS5597709A (en) | 1980-07-25 |
JPS6260846B2 JPS6260846B2 (en) | 1987-12-18 |
Family
ID=11633851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP627579A Granted JPS5597709A (en) | 1979-01-22 | 1979-01-22 | Analog signal amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5597709A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6093812A (en) * | 1983-10-26 | 1985-05-25 | Nec Corp | Integrated circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120754A (en) * | 1974-03-09 | 1975-09-22 |
-
1979
- 1979-01-22 JP JP627579A patent/JPS5597709A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120754A (en) * | 1974-03-09 | 1975-09-22 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6093812A (en) * | 1983-10-26 | 1985-05-25 | Nec Corp | Integrated circuit |
JPH0317244B2 (en) * | 1983-10-26 | 1991-03-07 | Nippon Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS6260846B2 (en) | 1987-12-18 |
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