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JPS5574175A - Preparing interpolation type mos semiconductor device - Google Patents

Preparing interpolation type mos semiconductor device

Info

Publication number
JPS5574175A
JPS5574175A JP14760578A JP14760578A JPS5574175A JP S5574175 A JPS5574175 A JP S5574175A JP 14760578 A JP14760578 A JP 14760578A JP 14760578 A JP14760578 A JP 14760578A JP S5574175 A JPS5574175 A JP S5574175A
Authority
JP
Japan
Prior art keywords
layers
openings
type
diffusion layers
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14760578A
Other languages
Japanese (ja)
Other versions
JPH0127589B2 (en
Inventor
Ikuo Kawamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14760578A priority Critical patent/JPS5574175A/en
Publication of JPS5574175A publication Critical patent/JPS5574175A/en
Publication of JPH0127589B2 publication Critical patent/JPH0127589B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a high degree of intergration by a method wherein opening are made on the SiO2 film on p and n-type diffusion layers and, after injection of the same type impurity ions, the openings are stacked with semiconductor layer and wiring layer. CONSTITUTION:In a CMOS device, openings are made on the SiO2 film on an Si substrate in which source and drain layers have been formed on the p-type and n- type areas. The openings expose p and n-type layers, on which the same type impurity ions are injected respectively to form diffusion layers 5a, 6a. Then, the openings are provided with adition-free polycrystalline Si 11 and Al wiring 1 in double layers. Although Si diffuses into Al, the Si is supplied from the Si layer 11 and therefore the diffusion layers 5, 6 are completely unaffected, thereby providing a good pn-junction property. Even when the openings are shifted from the layers 5, 6, the ion injection layers 5a, 6a formed on the substrate 3 at the locations of the openings prevent short-circuit failures. As such, the process prevents alloy spike, and provides shallow diffusion layers and compactly sized elements.
JP14760578A 1978-11-29 1978-11-29 Preparing interpolation type mos semiconductor device Granted JPS5574175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14760578A JPS5574175A (en) 1978-11-29 1978-11-29 Preparing interpolation type mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14760578A JPS5574175A (en) 1978-11-29 1978-11-29 Preparing interpolation type mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS5574175A true JPS5574175A (en) 1980-06-04
JPH0127589B2 JPH0127589B2 (en) 1989-05-30

Family

ID=15434100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14760578A Granted JPS5574175A (en) 1978-11-29 1978-11-29 Preparing interpolation type mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5574175A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785226A (en) * 1980-11-18 1982-05-27 Seiko Epson Corp Manufacture of semiconductor device
JPS5810856A (en) * 1981-07-10 1983-01-21 Nec Corp Manufacture of complementary type semiconductor integrated circuit device
JPS5821858A (en) * 1981-07-31 1983-02-08 Nec Corp Manufacturing method of semiconductor device
JPS5885559A (en) * 1981-11-18 1983-05-21 Nec Corp CMOS type semiconductor integrated circuit device
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Semiconductor memory device using stack-shaped capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116675A (en) * 1975-04-05 1976-10-14 Fujitsu Ltd Manufacturing method for a semiconductor device
JPS51134566A (en) * 1975-05-17 1976-11-22 Fujitsu Ltd Semiconductor unit manufacturing process
JPS51137384A (en) * 1975-05-23 1976-11-27 Nippon Telegr & Teleph Corp <Ntt> Semi conductor device manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116675A (en) * 1975-04-05 1976-10-14 Fujitsu Ltd Manufacturing method for a semiconductor device
JPS51134566A (en) * 1975-05-17 1976-11-22 Fujitsu Ltd Semiconductor unit manufacturing process
JPS51137384A (en) * 1975-05-23 1976-11-27 Nippon Telegr & Teleph Corp <Ntt> Semi conductor device manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785226A (en) * 1980-11-18 1982-05-27 Seiko Epson Corp Manufacture of semiconductor device
JPH0255937B2 (en) * 1980-11-18 1990-11-28 Seiko Epson Corp
JPS5810856A (en) * 1981-07-10 1983-01-21 Nec Corp Manufacture of complementary type semiconductor integrated circuit device
JPS5821858A (en) * 1981-07-31 1983-02-08 Nec Corp Manufacturing method of semiconductor device
JPS6359548B2 (en) * 1981-07-31 1988-11-21
JPS5885559A (en) * 1981-11-18 1983-05-21 Nec Corp CMOS type semiconductor integrated circuit device
JPH0121630B2 (en) * 1981-11-18 1989-04-21 Nippon Electric Co
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Semiconductor memory device using stack-shaped capacitor

Also Published As

Publication number Publication date
JPH0127589B2 (en) 1989-05-30

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