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JPS5451709A - Bit phase synchronizing circuit - Google Patents

Bit phase synchronizing circuit

Info

Publication number
JPS5451709A
JPS5451709A JP11795377A JP11795377A JPS5451709A JP S5451709 A JPS5451709 A JP S5451709A JP 11795377 A JP11795377 A JP 11795377A JP 11795377 A JP11795377 A JP 11795377A JP S5451709 A JPS5451709 A JP S5451709A
Authority
JP
Japan
Prior art keywords
circuit
signal
timing
retiming
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11795377A
Other languages
Japanese (ja)
Inventor
Haruo Tsuda
Makoto Sudo
Hidetoshi Shirakawa
Moriyuki Yamamoto
Susumu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP11795377A priority Critical patent/JPS5451709A/en
Publication of JPS5451709A publication Critical patent/JPS5451709A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To secure the bit phase synchronization between the digital units through a simple circuit with no piling of the timing matching signals in case the digital signals are transferred between plural units of devices via the same reference timing signal. CONSTITUTION:The following circuits are installed: timing signal generator circuit 12 which generates timing signal S4 and S5 of different phases to each other based on reference timing signals S1; changing point detecting circuit 11 which detects the changing point of receiving digital signal S2; and phase difference detecting circuit 13 which detects the phase difference between the output of circuit 11 and the timing signal S4 or S5. In addition, selector circuit 17 which the phase producing no decision error for signal S2 among two timing signals based on the output result of circuit 13 is added, along with retiming circuit 21 which gives retiming to signal S2 via retiming signal S9 selected through circuit 17. Thus, bit phase synchronous circuit 10 is constituted.
JP11795377A 1977-10-03 1977-10-03 Bit phase synchronizing circuit Pending JPS5451709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11795377A JPS5451709A (en) 1977-10-03 1977-10-03 Bit phase synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11795377A JPS5451709A (en) 1977-10-03 1977-10-03 Bit phase synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS5451709A true JPS5451709A (en) 1979-04-23

Family

ID=14724316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11795377A Pending JPS5451709A (en) 1977-10-03 1977-10-03 Bit phase synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS5451709A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2478410A1 (en) * 1980-03-11 1981-09-18 Ericsson Telefon Ab L M METHOD AND DEVICE FOR SYNCHRONIZING A BINARY DATA SIGNAL
JPS5774569U (en) * 1980-10-24 1982-05-08
WO2009084124A1 (en) * 2007-12-27 2009-07-09 Panasonic Corporation Semiconductor integrated circuit and designing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2478410A1 (en) * 1980-03-11 1981-09-18 Ericsson Telefon Ab L M METHOD AND DEVICE FOR SYNCHRONIZING A BINARY DATA SIGNAL
JPS5774569U (en) * 1980-10-24 1982-05-08
WO2009084124A1 (en) * 2007-12-27 2009-07-09 Panasonic Corporation Semiconductor integrated circuit and designing method thereof

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