JPS5451710A - Bit phase synchronizing circuit - Google Patents
Bit phase synchronizing circuitInfo
- Publication number
- JPS5451710A JPS5451710A JP11795477A JP11795477A JPS5451710A JP S5451710 A JPS5451710 A JP S5451710A JP 11795477 A JP11795477 A JP 11795477A JP 11795477 A JP11795477 A JP 11795477A JP S5451710 A JPS5451710 A JP S5451710A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- reference timing
- bit phase
- changing point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To omit the transfer of the timing information as well as the distance limitation between plural units of the device which carry out the digital signal processing via the reference timing signal, and thus to simplify the circuit constitution. CONSTITUTION:Bit phase synchronizing circuit 10 to secure the bit phase syncronization is provided between plural units of the device which carry out the digital signal processing via the reference timing signal given from the same reference timing generator source. Then changing point detecting circuit 11 which generates changing point pulse S3 with every changing point under the logic state of digital receiving signal S2 plus clock pulse generator 13 which produces reading clock pulse S4 featuring the frequency of an integer times as high as the frequency of reference timing signal S1 are added to circuit 10. In addition, the following component units are installed: RSFF12 which is set by output pulse S3 of circuit 10 and reset by pulse S4 and delivers clock pulse S6 only while FF12 is reset; and retiming circuit 15 which reads signal S2 by the output of gate 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11795477A JPS5451710A (en) | 1977-10-03 | 1977-10-03 | Bit phase synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11795477A JPS5451710A (en) | 1977-10-03 | 1977-10-03 | Bit phase synchronizing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5451710A true JPS5451710A (en) | 1979-04-23 |
Family
ID=14724343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11795477A Pending JPS5451710A (en) | 1977-10-03 | 1977-10-03 | Bit phase synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5451710A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55152710U (en) * | 1979-04-17 | 1980-11-04 | ||
| WO1981002654A1 (en) * | 1980-03-11 | 1981-09-17 | Ericsson Telefon Ab L M | A method and apparatus for synchronizing a binary data signal |
| JPS61144931A (en) * | 1984-12-19 | 1986-07-02 | Nec Corp | Multiplied sampling circuit |
-
1977
- 1977-10-03 JP JP11795477A patent/JPS5451710A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55152710U (en) * | 1979-04-17 | 1980-11-04 | ||
| WO1981002654A1 (en) * | 1980-03-11 | 1981-09-17 | Ericsson Telefon Ab L M | A method and apparatus for synchronizing a binary data signal |
| JPS61144931A (en) * | 1984-12-19 | 1986-07-02 | Nec Corp | Multiplied sampling circuit |
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