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JPS54121627A - Memory unit control system - Google Patents

Memory unit control system

Info

Publication number
JPS54121627A
JPS54121627A JP2938578A JP2938578A JPS54121627A JP S54121627 A JPS54121627 A JP S54121627A JP 2938578 A JP2938578 A JP 2938578A JP 2938578 A JP2938578 A JP 2938578A JP S54121627 A JPS54121627 A JP S54121627A
Authority
JP
Japan
Prior art keywords
memory
refresh
initial writing
action
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2938578A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Keizo Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2938578A priority Critical patent/JPS54121627A/en
Publication of JPS54121627A publication Critical patent/JPS54121627A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

PURPOSE:To reduce the quantity of the hardware by sharing a circuit for execution of two action modes of the refresh action of the volatile memory and initial writing action and performing the switching through CPU at the power supply making time. CONSTITUTION:Start timing generator circuit 6 generates the signals of the fixed period and gives the refresh with every fixed period to the memory consisting of the volatile memory elements in order to block the volatilization of the memory information. On the other hand, memory initializing signal 16 is transmitted from CPU at the break and make time of the power supply to give the mode designation for the initial writing. For both actions, the address of refresh address register 12 is sent to the memory via multiplexer 11 to give the address designation to the memory. Thus, a circuit is shared for execution of both the initial writing and the refresh, so the hardware increment is avoided for the initial writing.
JP2938578A 1978-03-15 1978-03-15 Memory unit control system Pending JPS54121627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2938578A JPS54121627A (en) 1978-03-15 1978-03-15 Memory unit control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2938578A JPS54121627A (en) 1978-03-15 1978-03-15 Memory unit control system

Publications (1)

Publication Number Publication Date
JPS54121627A true JPS54121627A (en) 1979-09-20

Family

ID=12274661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2938578A Pending JPS54121627A (en) 1978-03-15 1978-03-15 Memory unit control system

Country Status (1)

Country Link
JP (1) JPS54121627A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415433A2 (en) * 1989-09-01 1991-03-06 Oki Electric Industry Co., Ltd. Main memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415433A2 (en) * 1989-09-01 1991-03-06 Oki Electric Industry Co., Ltd. Main memory control system
US5235691A (en) * 1989-09-01 1993-08-10 Oki Electric Industry Co., Ltd. Main memory initializing system

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