JPH1197535A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the resistance of a plug and wiring layers, or to reduce the parasitic capacitance between the wiring layers, by providing a stopper as barrier to a metal for substitution between lower and metal substitution plugs. SOLUTION: A metal 8 for substitution such as a stopper 6 as a barrier to Al with small specific resistance is provided between a lower plug 5 and a metal substitution plug 10, thus preventing the metal 8 from entering the lower plug 5, and preventing pn junction due to a source/drain region 4 being formed on the semiconductor substrate 1 to be connected to the lower plug 5 from being damaged by the metal 8. Also, the stopper 6 as the berrier to the metal 8 has a wiring layer. Then, the wiring layer is constituted of a conductor layer that becomes the stopper 6 and the metal substitution layer 8 being provided on the conductor layer, thus reducing the resistance of the wiring layer, at the same time, thinning the wiring layer, and hence improving the operating speed of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. The present invention relates to a method of substituting a metal, and as a result, a semiconductor device having a characteristic structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the design rules (line / space) have become strict with the increase in the degree of integration and capacity of semiconductor devices.
The width of a wiring layer of (dynamic random access memory) is becoming narrower, and the diameter of a via hole for forming a plug that connects upper and lower wiring layers is becoming smaller.

As described above, when the width of the wiring layer is reduced, the resistance is increased, and the operation speed is delayed. In addition, as the diameter of the via hole becomes smaller, the aspect ratio (depth / diameter) becomes smaller. Even if a CVD method having better step coverage than a sputtering method is used, Al cannot be completely buried in such a via hole, and voids are formed inside the via holes, and voids are formed. As a result, the cross-sectional area of the portion where
There is a problem that the resistance is increased or the wire is broken in some cases.

In order to solve such a problem of a fine via hole, a polysilicon-aluminum replacement method (Pol
ysilicon-Aluminium Substi
Tute: PAS) has been proposed (if necessary, International Electron).
Devices Meeting 96, p. 946-
948) and FIG.

Referring to FIG. 19A, first, a silicon substrate 201 having a thickness of 2.
After depositing a 4 μm SiO ₂ film 202, RIE
A via hole having a bottom diameter of 0.25 μm, that is, a contact hole 203 is formed by (reactive ion etching), and then a low pressure chemical vapor deposition (LP)
By the CVD method, a polycrystalline Si layer 204 having a very good wraparound from Al is deposited, and the contact hole 20 is formed.
3 is embedded.

Next, referring to FIG. 19B, a CMP method (chemical mechanical polishing)
₂ Polishing until the surface of the film 202 is exposed to form a polycrystalline Si plug 205 with a polycrystalline Si layer embedded in the contact hole 203, and then depositing a 0.5 μm thick Al layer 206 by sputtering. Let it.

Next, as shown in FIG. 19 (c), the polycrystalline Si plug 205 is replaced with Al by performing an annealing treatment at 500 ° C. in a nitrogen atmosphere due to mutual diffusion between Si and Al. Then, the contact electrode including the Al-substituted plug 207 is formed by polishing until the surface of the SiO ₂ film 202 is exposed. In this case, the Si content in the Al-substituted plug 207 is about 0.4% even at the bottom.
In Al, Al is almost replaced.

In the annealing step, the Al layer 20
6, a Ti layer having a thickness of 0.2 μm is deposited thereon, so that the Ti layer functions as a Si absorption layer.
It is possible to make the Al layer 206 for 1 substitution thinner, lower the annealing temperature, and shorten the annealing time.

By using such a polysilicon-aluminum substitution method (PAS method), a via hole having a maximum aspect ratio of about 10 and a diameter of 0.1 μm or less can be filled with low-resistance Al. MPU (Mi
This is expected as a plug (contact electrode) of a C.I.

However, when such a polysilicon-aluminum replacement method is applied to an actual LSI manufacturing process, there is a relationship with other processes, and various problems are caused by the simple introduction of the above-described single process. Expected to occur.

For example, when the present invention is applied to a source / drain contact electrode of an IGFET (insulated gate field effect transistor), the source / drain region is made of polycrystalline Si.
After the polycrystalline Si plug is replaced with Al, the source / drain regions are also made of Al.
Will be replaced by

In this case, if Al enters the pn junction formed in the silicon substrate, the pn junction is destroyed due to the extension of Al spikes between the pn junctions, which is fatal to LSI. Serious damage.

Therefore, the present inventor, when applying such a polysilicon-aluminum substitution method to an actual device, uses a stopper film or a stopper film serving as an Al stopper between a source / drain region and a polycrystalline Si plug. Since an attempt was made to provide a barrier film, this application example will be described with reference to FIG.

As a general theory, providing a stopper film or a barrier film in order to prevent diffusion is a conventional means. However, in the case of the polysilicon-aluminum substitution method, it does not react with Al even at a high temperature, or , It is necessary to select a substance that is difficult to react.
It was determined that iN, WN or SiC was appropriate.

However, TiN, WN, or SiC has a problem that the reactivity with Si is poor and it is difficult to make electrical contact, and the contact resistance with the source / drain region becomes extremely high. in case of,
At the interface between the stopper film or the barrier film and the source / drain region, a film that easily reacts with Si, that is, a thin contact metal is formed.

Referring to FIG. 20A, first, an element isolation oxide film 212 is formed in a predetermined region of a p-type silicon substrate 211 by selective oxidation, and then the exposed surface of the p-type silicon substrate 211 surrounded by the element isolation oxide film 212 is formed. Is thermally oxidized to form a gate oxide film 213, and then a non-doped polycrystalline Si layer is deposited.
Ion implantation of impurities such as (phosphorus), and then,
After depositing a SiO ₂ film or a Si ₃ N ₄ film serving as a protective film 215 by a CVD method, the gate electrode 214 is formed by etching in a predetermined pattern.

Next, the gate electrode 214 and the protective film 21 are formed.
5 is used as a mask to ion-implant impurities such as As or P to form n-type source / drain regions 217. Then, an SiO ₂ film is deposited on the entire surface by a CVD method, and anisotropic etching is performed. 216 are formed.

Next, the entire surface is etched by the CVD method.
As a stopper film at the time of polishing_ThreeN _FourDeposited film 218
After that, the entire surface is_ThreeN_FourMembrane 218
And SiO with different etching characteristics_TwoDeposit the film between layers
An insulating film 219 is formed, and then Si_ThreeN_FourRemove membrane 218
An opening is formed in the interlayer insulating film 219 as a tuning stopper layer.
After being formed, the Si_ThreeN_FourSelect membrane 218
Remove selectively.

Next, the contact metal having a thickness of 20
nm thickness of the Ti film 220 and barrier metal
A 100 nm TiN film 221 is sequentially deposited by a sputtering method or a CVD method.

Next, polycrystalline Si is formed by LPCVD.
After depositing the film, C is deposited until the TiN film 221 is exposed.
A polycrystalline Si plug 222 is formed by polishing by the MP method, and then an Al layer 223 having a thickness of 2 μm and a Ti layer 22 having a thickness of 200 nm are formed by using a sputtering method.
4 is deposited.

Referring to FIG. 20B, the polycrystalline Si plug 222 is replaced with Al by performing a heat treatment at a temperature of 400 to 660 ° C. for about 1 hour in a nitrogen atmosphere, and then again using the CMP method. The Al-substituted plug 225 is formed by polishing until the surface of the interlayer insulating film 219 is exposed.

By adopting such a structure, that is, by employing a stopper film composed of a contact metal and a barrier metal, the polysilicon-aluminum replacement method can be implemented in an actual LSI.
It was found that the method can be applied to the manufacturing process.

As the contact metal in this case, besides Ti, W, Co, Ni, Ta, or a silicide thereof can be used, and the silicide is already formed on the surface of the n-type source / drain region 217. Is formed, or when a base functioning as a contact metal is formed, the contact metal deposition step can be omitted.

[0024]

However, in the above-mentioned application example, there is no problem when the annealing temperature is relatively low, such as 400 ° C. to 450 ° C., but higher temperatures, for example, 450 ° C. to 850 ° C. A problem arises when the heat treatment is performed at ℃.

That is, when a heat treatment for replacing Al is performed at such a high temperature, Ti itself of the contact metal reacts with Si of the source / drain regions, and enters into the pn junction to form the pn junction. This is because there is a possibility of destruction.

Therefore, although there is no problem if such a contact plug forming step is the final step, a polycrystalline Si plug is provided via a stopper layer in the middle of the manufacturing step, and a high-temperature processing step is performed in a later manufacturing step. After that, if the polysilicon-aluminum replacement method is performed, an Al-substituted plug can be formed.
There is also a problem that i diffuses and destroys a pn junction, and a problem that a eutectic alloy of Ti and Si is formed by diffusion of Ti and impurities are abnormally segregated in this eutectic region to cause a contact failure. Therefore, there is a problem that the application process is limited.

Further, since the conventional polysilicon-aluminum replacement method assumes only replacement of a polycrystalline Si plug, the lower wiring layer constituting the conductive path of the LSI is formed of Al.
(Specific resistance: 2.8 μΩ · cm) doped polycrystalline Si having a higher specific resistance (specific resistance: 300 to 800 μΩ · c)
m), high melting point metal (specific resistance of W: 6 μΩ · cm), or high melting point metal silicide (specific resistance of W silicide: 7)
0 μΩ · cm, specific resistance of Ti silicide: 15 μΩ · c
m) etc., so that the polysilicon-
The advantages of the aluminum substitution method were not fully exploited.

For example, in the case of a bit line of a DRAM,
A storage electrode and a capacitor insulating film constituting a memory cell capacitor are formed above the bit line,
According to the current technology, it is very difficult to form this capacitor insulating film at a low temperature of about 600 ° C. and to obtain high reliability. Therefore, a high-temperature heat treatment at 700 ° C. to 850 ° C. is required.

Since this step is performed after the formation of the bit line, Al having a melting point of 660 ° C. cannot be used for the bit line. However, if Al can be used for the bit line, the bit line is simply formed. Not only can the resistance be lowered, but also the bit lines can be made thinner, so that the parasitic capacitance between adjacent bit lines can be reduced, and a high-speed, low-power memory LSI can be manufactured. It becomes possible to do.

Further, since the resistance and the parasitic capacitance of the bit line can be reduced, the number of cells connected to one bit line can be increased, so that the integration degree of the memory can be increased. And therefore the bit line A
This is where long-awaited.

In the case of a normal self-aligned IGFET, ion implantation is performed using the gate electrode as a mask.
The source / drain regions are formed by performing annealing for activation.
Since the temperature is about 00 ° C., Al is not used as the gate electrode.

However, if Al can be used as the gate electrode, as in the case of the bit line, it can greatly contribute to an increase in the speed and power consumption of the LSI, and a high value-added LSI can be manufactured. If Al can be used as a gate electrode of a memory, that is, Al can be used as a word line, the number of cells that can be connected to one word line can be increased, and the degree of integration of the memory can be increased. Becomes possible.

In the case of a self-aligned bipolar transistor, an external base region and an emitter region are formed by solid-phase diffusion of impurities from a base extraction electrode and an emitter electrode made of a doped polycrystalline Si layer. Since the heat treatment temperature for diffusion is 800 ° C. to 1100 ° C., Al cannot be used as a diffusion source / electrode.

However, if the base extraction electrode and the emitter electrode can be replaced with Al, remarkable high speed operation and low power consumption can be achieved, which is very desirable.

In order to reduce the resistance of such a wiring layer or an electrode, even if the polysilicon-aluminum replacement method is considered, the above-described bit line, gate electrode,
Alternatively, since the base extraction electrode is formed in a part deep from the surface of the LSI, that is, near the surface of the silicon substrate, the bit line, the gate electrode, or the base extraction electrode is formed of a polycrystalline Si layer. However, even if an attempt is made to replace Al with the polysilicon-aluminum replacement method, there is a problem that a simple application of the polysilicon-aluminum replacement method cannot connect a thick Al layer required for the replacement to the polycrystalline Si layer to be replaced.

In a state-of-the-art LSI, a source / drain electrode is formed for a word line and a capacitor contact is formed for a bit line in a self-aligned manner. It is essential that the upper part of the line is covered with an insulating film, and it is not allowed to remove this insulating film in the subsequent steps.

Therefore, in a dense part of cells, a conventional polysilicon-aluminum substitution method in which the upper part of a word line or a bit line is exposed and Al substitution is performed by contact with a thick substitution Al layer is performed. It cannot be applied and some contrivance is required.

For example, when replacing a bit line with Al, a structure in which the bit line itself is easily replaced with Al,
Structure of introduction part of substitution, after replacing bit line with Al, stopper structure to prevent Al from further entering lower polycrystalline Si plug and source / drain region, contact with lower plug where Al substitution is not desired It is necessary to devise a stopper structure when the upper plug is replaced with Al, and if these countermeasures are taken separately, the work constant increases and leads to an increase in cost.
It is also necessary to take some measures to avoid increasing the number of manufacturing steps.

In particular, in the case of DRAM, competition between manufacturers is fierce and it is very important to reduce the cost. Therefore, even if the polysilicon-aluminum substitution method is introduced to achieve high functionality, it is necessary to reduce the cost. Is the most important issue, and it is indispensable to prevent the cost of the Al replacement itself process and the accompanying stopper forming process from increasing.

The gate electrode is made of polysilicon.
When applying the aluminum replacement method, the gate insulating film is a very delicate thin insulating film, and the reliability is easily damaged by the diffusion of trivial metal. It is necessary to devise a device that does not impair the reliability of the device.

When the polysilicon-aluminum replacement method is applied to the base extraction electrode and the emitter extraction electrode of the self-aligned bipolar transistor, these extraction electrodes also serve as impurity diffusion sources. It is necessary to devise an electrode structure so as to fulfill these roles.

Further, in order to increase the speed and reduce the power consumption of the LSI, it is necessary to reduce the parasitic capacitance between the wiring layers. However, in the conventional LSI, the dielectric constant of the insulating film itself constituting the interlayer insulating film must be reduced. Consideration was only given to lowering the level, and measures against parasitic capacitance were not sufficient.

Therefore, according to the present invention, the polysilicon-aluminum substitution method is not required to increase the number of manufacturing steps, and
By applying the device so that it does not adversely affect the element characteristics, the resistance of the plug and the wiring layer can be reduced, or
An object is to reduce parasitic capacitance between wiring layers.

[0044]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. 1 (a) and 1 (b) (1) In the present invention, in a semiconductor device, a replacement metal 8 is provided at least between a lower plug 5 and a metal replacement plug 10.
A stopper 6 serving as a barrier against the above is provided.

As described above, by providing the stopper 6 serving as a barrier for the replacement metal 8, for example, Al having a small specific resistance, at least between the lower plug 5 and the metal replacement plug 10, the replacement of the upper plug 7 is performed. In addition, the replacement metal 8 does not enter the lower plug, and the pn junction by the source / drain region 4 formed in the semiconductor substrate 1 connected to the lower plug 5 is not broken by the replacement metal 8.

(2) Further, according to the present invention, in the above (1), the stopper 6 serving as a barrier to the replacement metal 8 is
It is characterized in that it also serves as a wiring layer.

As described above, the wiring layer may be constituted by the stopper 6 serving as a barrier to the replacement metal 8.

(3) The present invention is characterized in that, in the above (2), the wiring layer comprises a conductor layer serving as the stopper 6 and a metal substitution layer provided thereon.

As described above, since the wiring layer is also composed of the metal substitution layer, the resistance of the wiring layer can be reduced.
Since the thickness of the wiring layer can be reduced, the operation speed of the semiconductor device can be significantly increased.

(4) Further, according to the present invention, in the semiconductor device, the gate electrode 3 comprises a metal replacement layer, a conductor layer serving as a stopper 6 for the replacement metal 8, and a silicon layer doped with impurities from the upper side. It is characterized by having a multilayer structure.

As described above, the gate electrode 3 has a multilayer structure with the stopper 6 interposed therebetween, so that the threshold voltage _{Vth of the} IGFET is not changed and the reliability of the gate insulating film 2 is not impaired. , It is possible to increase the speed.

(5) Further, the present invention is characterized in that, in the semiconductor device, the gate electrode 3 is formed of a metal substitution layer, and the gate insulating film 2 is formed of an insulating film containing nitrogen.

[0053] Thus, the insulating film containing nitrogen as the gate electrode 3, for example, SiON film (silicon oxynitride film), or Si _x N _y and by the use of laminated composite film of SiO _2, a gate electrode 3 Can be constituted by a metal substitution layer, whereby the operating speed can be increased.

(6) Further, according to the present invention, in a semiconductor device, an electrode in contact with the semiconductor substrate 1 is a conductive layer serving as a stopper 6 for a metal substitution layer and a substitution metal 8 from the upper side.
Further, it is characterized by being constituted by a multilayer structure composed of a silicon layer doped with impurities.

As described above, by forming the electrode in contact with the semiconductor substrate 1 in a multilayer structure with the stopper 6 interposed therebetween, it is possible to reduce the specific resistance of the electrode serving also as a diffusion source by the metal substitution layer.

(7) The present invention is characterized in that, in the above (6), the electrode in contact with the semiconductor substrate 1 is a base extraction electrode of a bipolar transistor.

By using such a configuration as the base extraction electrode, the operating speed of the self-aligned bipolar transistor can be increased.

(8) In the semiconductor device according to the present invention, the bit line of the dynamic random access memory is formed of a metal substitution layer.

As described above, by configuring the bit lines of the DRAM with the metal substitution layer, it is possible to increase the operation speed of the DRAM, to prevent signal delay, and, A contact is not required, and the number of cells that can be connected to one bit line can be increased, so that the DRAM can be highly integrated.

(9) The present invention is characterized in that, in the above (8), the word line is constituted by a metal substitution layer.

As described above, by configuring the word lines of the DRAM also with the metal substitution layer, the operation speed of the DRAM can be further increased, and the number of cells that can be connected to one word line is increased. Therefore, the DRAM can be further integrated.

(10) In the present invention, the metal-substituted plug 10 or the metal-substituted layer in any one of the above-mentioned (1) to (9),
Characterized by containing silicon.

As described above, by including 0.1 to 50% of Si in the metal substitution plug 10 or the metal substitution layer, the electromigration resistance can be increased.

(11) Further, the present invention is characterized in that in any one of the above (1) to (10), the metal substitution plug 10 or the metal substitution layer contains strontium or lithium.

As described above, about 0.05 to 0.2% of strontium (S) is added to the metal replacement plug 10 or the metal replacement layer.
r) or by containing lithium (Li)
Since the crystal grain size can be reduced, processing is facilitated and electromigration resistance is improved.

(12) Further, according to the present invention, in any one of the above (1) to (11), the main component of the metal substitution plug 10 or the metal substitution layer substituted by the substitution metal 8 is A
1, Cu, Ag, Ru, or Pt.

As described above, the main component of the metal replacement plug 10 or the metal replacement layer, that is, the replacement metal 8 is made of Al, Cu,
Ag, Ru, or Pt is preferred, and among them,
In particular, Al is preferred, followed by Cu.

(13) According to the present invention, in a method of manufacturing a semiconductor device, a stopper 6 serving as a barrier to a replacement metal 8 is provided at least between a lower plug 5 and an upper plug 7 made of silicon. It is characterized in that the upper plug 7 is replaced with a replacement metal 8.

As described above, the upper plug 7 is replaced by providing the stopper 6 serving as a barrier against the replacement metal 8, for example, Al having a small specific resistance, at least between the lower plug 5 and the metal replacement plug 10. By the heat treatment, the replacement metal 8 does not enter the lower plug, and the pn junction formed on the semiconductor substrate 1 connected to the lower plug 5 is not broken by the replacement metal 8.

Further, in the step of replacing the upper plug 7, even if the element forming the stopper 6 enters the lower plug 5, the element further enters the semiconductor substrate 1 connected to the lower plug 5 therebelow to form the eutectic alloy. Does not form pn
The reliability of the semiconductor device can be improved without breaking the junction or causing a contact failure.

In the present invention, the term silicon or silicon layer means polycrystalline silicon, microcrystalline silicon, amorphous silicon, or monocrystalline silicon, and non-doped polycrystalline silicon is particularly preferable. In addition, at the time of metal replacement, it is desirable to cover the replacement metal 8 with the silicon absorbent layer 9.

(14) The invention according to (13), wherein the stopper 6 serving as a barrier to the replacement metal 8 is provided.
Are also used as wiring layers.

As described above, by allowing the wiring layer to also serve as the stopper 6, it is possible to replace the metal of the upper plug 7 at a desired location without increasing the number of manufacturing steps.

(15) According to the present invention, in the above (14), the wiring layer is constituted by the conductor layer serving as the stopper 6 and the silicon layer provided thereon, and a silicon plug reaching the silicon layer is provided. It is characterized in that the silicon layer is replaced with the replacement metal 8.

As described above, by forming the wiring layer with the laminated structure of the silicon layer / stopper 6, it is possible to replace the metal of the upper plug 7 at a desired position without increasing the number of manufacturing steps. By using a plug, metal replacement of a silicon wiring layer at a recessed position is also possible.

(16) Further, according to the present invention, in the method for manufacturing a semiconductor device, the gate electrode 3 may be formed by forming a silicon layer from the upper layer side, a conductor layer serving as a stopper 6 for the replacement metal 8,
Further, the gate electrode 3 has a multilayer structure including a silicon layer doped with an impurity, and only the upper silicon layer in the gate electrode 3 is replaced with the replacement metal 8.

As described above, the gate electrode 3 is formed on the silicon layer /
With the multilayer structure of the stopper 6 and the doped silicon layer, only the silicon layer can be replaced with metal, so that _Vth is not changed and the reliability of the gate insulating film 2 is not reduced. In addition, the specific resistance of the gate electrode 3 can be reduced.

(17) According to the present invention, in the method for manufacturing a semiconductor device, the gate electrode 3 is formed of a silicon layer, the gate insulating film 2 is formed of an insulating film containing nitrogen, and the gate electrode 3 is replaced. It is characterized in that it is replaced with a metal 8 for use.

As described above, the gate insulating film 2 is made of an insulating film containing nitrogen having a small diffusion coefficient of Al.
For example, by configuring in the SiON film or Si _x N _y and SiO ₂ of the laminated composite film, without damaging the gate insulating film 2 and the channel region, a gate electrode 3
Only the metal can be substituted to lower the specific resistance.

(18) In the method of manufacturing a semiconductor device according to the present invention, the electrode in contact with the semiconductor substrate 1 may be formed by forming a silicon layer from the upper layer side, a conductor layer serving as a stopper 6 for the replacement metal 8, and an impurity. It has a multilayer structure composed of a doped silicon layer, characterized in that a silicon layer doped with impurities is used as a diffusion source and an upper silicon layer is replaced with a replacement metal 8.

As described above, the electrodes in contact with the semiconductor substrate 1 are
By forming a multilayer structure of the silicon layer / stopper 6 / doped silicon layer, it is possible to finally lower the specific resistance of the electrode serving also as the diffusion source.

(19) The present invention is characterized in that, in the above (18), the electrode in contact with the semiconductor substrate 1 is a base extraction electrode of a bipolar transistor.

By using the above-described multilayer structure electrode as the base extraction electrode, the base extraction electrode of the self-aligned bipolar transistor can be reduced in specific resistance without affecting other manufacturing steps.

(20) Further, according to the present invention, in any one of the above (13) to (19), after replacing the upper plug 7 or the silicon layer with the replacement metal 8,
Is etched into a predetermined shape and used as a wiring layer.

As described above, by using the replacement metal 8 also as the wiring layer, the step of forming the conductor layer for the wiring layer can be omitted, and Si is naturally contained in the wiring layer. Therefore, electromigration resistance is improved.

(21) According to the present invention, in any one of the above (13) to (19), before providing the replacement metal 8, the upper plug 7 or the silicon plug is exposed in at least a part of the insulating film. To provide a wiring layer groove,
After replacing at least the upper plug 7 or the silicon plug with the replacement metal 8, the film is reduced so that the replacement metal 8 is buried in the wiring layer groove and used as a wiring layer.

As described above, since the thickness of the wiring layer can be controlled by the thickness of the insulating film by using the wiring layer groove, the thickness of the wiring layer can be easily controlled.

(22) Further, according to the present invention, in the method for manufacturing a semiconductor device, the wiring layer formed of the silicon
After a heat treatment step at a temperature of 00 ° C. or more, the metal is replaced with a metal for replacement 8.

As described above, the wiring layer, which conventionally had to be constituted by a heat-resistant silicon layer due to the heat treatment process, can be reduced in resistance by metal replacement via the silicon plug. Thereby, the operation speed of the semiconductor device can be greatly increased.

(23) The present invention is characterized in that, in the above (22), the wiring layer composed of a silicon layer is a bit line of a dynamic random access memory.

As described above, the bit line, which conventionally had to be constituted by the silicon layer due to the manufacturing process, can be reduced in resistance by the metal replacement via the silicon plug. Speed can be greatly increased.

(24) The present invention is characterized in that, in the above (22), the wiring layer composed of a silicon layer is a word line of a dynamic random access memory.

As described above, the word line, which had to be formed of a silicon layer for use in the self-alignment process, can be reduced in resistance by metal replacement through a silicon plug, thereby reducing the operating speed of the DRAM. Can be made faster.

(25) The invention according to (23) or (24), wherein the non-replacement portion of a plug or a wiring layer of a circuit element constituting a peripheral circuit of the dynamic random access memory is replaced. It is characterized in that a stopper pad is provided at a portion where the metal 8 enters.

As described above, by providing the stopper pad at the non-substituted portion, for example, at the portion where the replacement metal 8 enters in the gate electrode 3 or the like where fluctuation of V _th due to metal substitution is to be minimized, only the desired portion is provided. Metal replacement becomes possible.

(26) Further, the present invention is characterized in that, in the above (25), the non-substituted portion forms a resistor.

As described above, by providing the stopper pads at the leading end and the trailing end of the non-substituted portion constituting the resistor, a predetermined portion of the bit line composed of the unsubstituted silicon layer can be used as the resistor.

(27) Further, according to the present invention, in any one of the above (13) to (26), the metal replacement plug 10 or the metal replacement wiring layer after the replacement with the replacement metal 8
It is characterized by containing 0.1 to 50% of silicon.

As described above, by including 0.1 to 50% of Si in the metal substitution plug 10 or the metal substitution layer, the electromigration resistance can be increased. The Si content can be controlled by the temperature and time of the annealing treatment for metal replacement.

(28) Further, the present invention is characterized in that in any one of the above (13) to (27), the replacement metal 8 contains strontium or lithium.

As described above, Sr or Li is used as the replacement metal 8.
, Sr or Li is also contained in the metal replacement plug 10 or the metal replacement layer, thereby reducing the crystal grain size, thereby facilitating the processing and being constituted by the replacement metal layer. Electromigration resistance of the wiring layer and the metal substitution layer is improved.

(29) Further, according to the present invention, in a method of manufacturing a semiconductor device, a silicon plug or a silicon wiring layer provided on a semiconductor substrate 1 via an insulating film may be replaced with a replacement metal 8.
Then, at least a part or the whole of the metal-substituted plug 10 or the metal-substituted wiring layer, which is metal-substituted, is removed to form a cavity.

As described above, by removing at least a part or the whole of the metal replacement plug 10 or the metal replacement wiring layer formed by using the metal replacement and forming the cavity, the effective thickness of the insulating film including the cavity is reduced. The effective dielectric constant can be greatly reduced, thereby reducing the parasitic capacitance.

(30) Further, the present invention is characterized in that, in the above (29), the cavity separates wiring layers of the same layer in the cavity.

Such a cavity is formed between wiring layers of the same level.
That is, it can be used for reducing the parasitic capacitance between wiring layers formed from conductor films formed in the same film forming process. In this case, the same wiring layer can be used as a silicon layer, or Alternatively, a metal-substituted one may be used.

(31) Further, the present invention is characterized in that, in the above (29), the cavity separates the wiring layer between different layers from the cavity.

Such a cavity can be used to reduce the parasitic capacitance between the wiring layers between different layers, ie, between the lower wiring layer and the upper wiring layer. The quasi-wiring layer may be a silicon layer or a metal-substituted one.

(32) According to the present invention, in the above (29), the hollow portion is removed by replacing the side wall made of the silicon layer provided on the side wall of the gate electrode 3 with the replacement metal 8. It is characterized by being formed.

As described above, the cavity can be formed on the side of the gate electrode 3 by utilizing the silicon sidewall, thereby reducing the parasitic capacitance between the gate electrode 3 and the source / drain electrodes. be able to.

(33) The present invention provides the method according to any one of the above (13) to (32), wherein
1, Cu, Ag, Ru, or Pt.

The use of such a metal as the replacement metal 8 facilitates the replacement of the metal in the silicon plug or the silicon wiring layer.
Al is preferred, followed by Cu.

[0112]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The steps of a first embodiment of the present invention will now be described with reference to FIG. See FIG. 2 (a). As in the prior art, as described with reference to FIG.
After forming an element isolation oxide film 12 in a predetermined region of a p-type silicon substrate 11 by selective oxidation, the element isolation oxide film 12 is formed.
The exposed surface of the p-type silicon substrate 11 surrounded by is thermally oxidized to form a gate oxide film 13, and then a non-doped polycrystalline Si layer is deposited. After that, a SiO ₂ film serving as the protective film 15 is deposited on the entire surface by the CVD method, and then etched in a predetermined pattern to form the gate electrode 14.

Next, As is ion-implanted using the gate electrode 14 and the protective film 15 as masks to form n-type source / drain regions 17, and then an SiO ₂ film is deposited on the entire surface by CVD, and anisotropic etching is performed. Is performed to form the sidewalls 16.

Then, a 10 to 100 nm thick Si film serving as a stopper film during etching is formed on the entire surface by CVD.
₃ N ₄ After the film 18 is deposited, Si ₃ N ₄ film 18 and the different thicknesses of the etching characteristics 10 on the entire surface by CVD
An interlayer insulating film 1 is formed by depositing a SiO ₂ film of 0 to 500 nm.
And 9, then, after an opening is formed in the interlayer insulating film 19 and the Si ₃ N ₄ film 18 as an etching stopper layer, n-type source by selectively removing the Si ₃ N ₄ film 18 exposed in the opening -A via hole reaching the drain region 17 is formed.

Then, a polycrystalline Si layer doped with impurities is deposited by LPCVD, and then polished by CMP until the first interlayer insulating film 19 is exposed to form a polycrystalline Si plug 20 having conductivity. I do.

Next, the contact metal having a thickness of 10
After a Ti film 21 having a thickness of, for example, 20 nm, for example, 20 nm, and a TiN film 22 having a thickness of 10 to 200 nm, for example, 50 nm serving as a barrier metal are sequentially deposited by a sputtering method, the TiN film 22 is left on the polycrystalline Si plug 20. To form a stopper pad for Al.

Then, again, the SiO.sub.3 having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m
_After depositing the _two films to form the second interlayer insulating film 23, a via hole reaching the stopper pad is provided, and then a non-doped polycrystalline Si layer is deposited again by the LPCVD method. The polycrystalline Si plug 24 is formed by polishing by a CMP method until the film 23 is exposed.

Next, an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.

Next, as shown in FIG. 2B, in a nitrogen atmosphere, at 400 to 660 ° C., for example,
A heat treatment is performed at 500 ° C. for 1.0 to 48 hours, for example, 6 hours, so that the polycrystalline Si plug 24 is
Then, the surface is polished again by using the CMP method until the surface of the second interlayer insulating film 23 is exposed.
The replacement plug 27 is formed.

As described above, in the first embodiment of the present invention, since the stopper pad is provided between the lower polycrystalline Si plug 20 and the upper polycrystalline Si plug 24, the upper pad is provided. Al is not diffused into the lower polycrystalline Si plug 20 when the polycrystalline Si plug 24 of FIG.
7 is not destroyed.

Further, in the heat treatment step accompanying the polysilicon-aluminum replacement step or other manufacturing steps,
Even if a high-temperature process of 450 ° C. or more is performed, diffusion of Ti as a contact metal forming the stopper pad occurs, but the distance between the n-type source / drain region 17 and the n-type source / drain region 17 due to the presence of the lower polycrystalline Si plug 20. Are separated from each other, so that no junction breakdown occurs.

For the same reason, Ti and Si in the n-type source / drain regions 17 do not form a eutectic alloy, and abnormal segregation of impurities accompanying the eutectic alloy does not occur. Does not occur,
As a result, the resistivity of the minute via hole can be reduced, and the reliability of the element can be improved.

Next, the steps of the second embodiment of the present invention will be described with reference to FIG. The steps up to the manufacturing process of the lower polycrystalline Si plug are completely the same as those of the above-described first embodiment, and the description is omitted.

Referring to FIG. 3, after forming a polycrystalline Si plug 20 having conductivity in the same manner as in the first embodiment, a Ti film 21 having a thickness of 10 to 100 nm, for example, 20 nm as a contact metal, and a barrier metal are formed. Thickness of 10 to 200 nm, for example, 50
After sequentially depositing a TiN film 22 having a thickness of 10 nm and a W layer having a thickness of 10 to 500 nm, for example, 50 nm, which effectively becomes a wiring layer, by a sputtering method, etching is performed so as to remain on the polycrystalline Si plug 20. And W pad 28
And a W wiring layer 29 is formed.

Then, again, the SiO.sub.3 having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m
_After depositing the _two films to form the second interlayer insulating film 23, a via hole reaching the W pad 28 and the W wiring layer 29 is provided,
Next, a non-doped polycrystalline Si layer is deposited again by the LPCVD method, and then polished by the CMP method until the second interlayer insulating film 23 is exposed, thereby forming a polycrystalline Si plug (not shown). .

Next, an Al layer (not shown) having a thickness of 0.1 to 10.0 μm, for example, 2 μm and a thickness of 50 to 2000 nm, for example, 200
After depositing a Ti layer (not shown) with a thickness of 400 nm, a heat treatment is performed in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours to form a polycrystalline Si plug. After replacing with Al,
The Al-substituted plugs 27 and 30 are formed by polishing using a CMP method until the surface of the second interlayer insulating film 23 is exposed.

As described above, in the second embodiment of the present invention, since the stopper pad serving as a barrier against Al is formed by using the wiring layer forming process, the stopper pad is formed. The film forming step and the patterning step become unnecessary.

In this case, the W pad 28 and the W wiring layer 29
W reacts with the Si of the replacement polycrystalline Si plug and is partially or entirely silicided. However, since the TiN film 22 serves as a barrier to Al, the Al is deposited on the lower polycrystalline Si plug 20. There is no diffusion, so that the pn junction constituting the n-type source / drain region 17 is not broken, and no junction breakage due to Ti or contact failure due to the eutectic alloy occurs.

The W layer according to the second embodiment may be replaced with WN, W silicide, Ta, Ti, TiN, Ti silicide, Co silicide, or the like. And, a conductive material having high heat resistance is desirable, and when WN or TIN is used,
It is not necessary to provide the TiN film 22 as a barrier metal.

Next, the steps of the third embodiment of the present invention will be described with reference to FIG. The steps up to the manufacturing process of the lower polycrystalline Si plug are completely the same as those of the above-described first embodiment, and the description is omitted.

Referring to FIG. 4A, a polycrystalline Si plug 20 having conductivity is formed in the same manner as in the first embodiment, and then a Ti film 21 having a thickness of 10 to 100 nm, for example, 20 nm serving as a contact metal is formed. 10 to 200 nm in thickness serving as a barrier metal, for example, 5
A 0 nm TiN film 22 is sequentially deposited by a sputtering method, and then a thickness of 10 to 10 is formed by an LPCVD method.
After depositing a non-doped polycrystalline Si layer of 00 nm, for example, 300 nm, etching is performed so as to remain on the polycrystalline Si plug 20 to form a polycrystalline Si pad 31 and a polycrystalline Si wiring layer. 32 are formed.

Then, again, a CVD method is used to cover the entire surface with a SiO.sub.
_After depositing the _two films to form the second interlayer insulating film 23, a via hole reaching the polycrystalline Si pad 31 and the polycrystalline Si wiring layer 32 is provided, and then the non-doped polycrystalline Si layer is again formed by LPCVD. After the deposition, the polycrystalline Si plugs 24 and 33 are formed by polishing by a CMP method until the second interlayer insulating film 23 is exposed.

Next, an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.

Next, as shown in FIG. 4B, in a nitrogen atmosphere at 400 to 660 ° C., for example,
By performing heat treatment at 500 ° C. for 1 to 48 hours, for example, 6 hours, the polycrystalline Si plugs 24 and 33 and the polycrystalline Si connected to the polycrystalline Si plugs 24 and 33
After replacing the pad 31 and the polycrystalline Si wiring layer 32 with Al, the Al replacement plugs 27 and 30 and the Al replacement pad 34 are polished again using the CMP method until the surface of the second interlayer insulating film 23 is exposed. , And an Al-substituted wiring layer 35 are formed.

As described above, in the third embodiment of the present invention, since the stopper pad serving as a barrier against Al is formed by using the wiring layer forming step, the stopper pad for forming the stopper pad is formed. A wiring layer that does not require a patterning step and that could not use Al due to a high-temperature heat treatment at 600 ° C. or higher accompanying a later manufacturing step,
The operation speed of the semiconductor device can be increased because it can be replaced with Al having a low specific resistance.

The Al substitution of the polycrystalline Si wiring layer 32 is a matter clarified by the experiment of the present inventor, and even if the entire upper surface of the polycrystalline Si wiring layer 32 is not exposed, 33, the polycrystalline S
The length from the contact portion of the i-plug 33 to 100 μm can be reliably replaced with Al, and the mutual solid-phase diffusion that cannot be expected from the Al-substitution technique of the polycrystalline Si plug itself is generated. Was revealed.

In particular, in the third embodiment,
In the middle of the manufacturing process, a conventional semiconductor device is manufactured by using a non-doped polycrystalline Si wiring layer 32 which has a very low conductivity as a wiring layer and has not been used as a conventional wiring layer. A structure that does not appear in the process is adopted. By using such a non-doped polycrystalline Si wiring layer 32, Al substitution becomes easier,
This allows the polycrystalline Si wiring layer at a position away from the polycrystalline Si plug 33 to be replaced with Al.

Next, steps of a fourth embodiment of the present invention will be described with reference to FIG. Note that FIG.
FIG. 3A is a cross-sectional view along the gate lead-out wiring layer. 5A and 5B, first, an element isolation oxide film 12 is formed in a predetermined region of the p-type silicon substrate 11 by selective oxidation, and then the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is exposed. The surface is thermally oxidized to form a gate oxide film 13, which is then
After depositing a non-doped polycrystalline Si layer of up to 300 nm, for example, 50 nm, P is ion-implanted to form a doped polycrystalline Si layer 36. Note that a doped polycrystalline Si film may be formed from the beginning.

Next, the contact metal having a thickness of 10
100 nm, for example, 20 nm Ti film 37 and burr
A metal thickness of 10 to 200 nm, for example, 50 n
m TiN films 38 are sequentially deposited by sputtering.
After that, the thickness is again 10 to 100 using the LPCVD method.
0 nm, for example 150 nm, undoped polycrystalline S
An i-layer is deposited and then deposited over the entire surface by CVD.
SiO to be protective film 15 _TwoI deposited a 100nm film
First, the gate electrode and the gate are etched into a predetermined pattern.
Forming a lead wiring layer.

Next, As is ion-implanted using the gate electrode and the protective film 15 as a mask to form n-type source / drain regions 17, and then an SiO ₂ film is deposited on the entire surface.
By performing anisotropic etching, the side wall 1 is formed.
6 is formed.

Next, a 10 to 100 nm thick Si film serving as a stopper film during etching is formed on the entire surface by CVD.
₃ N ₄ After the film 18 is deposited, Si ₃ N ₄ film 18 and the different thicknesses of the etching characteristics 10 on the entire surface by CVD
An interlayer insulating film 1 is formed by depositing a SiO ₂ film of 0 to 500 nm.
And 9, then, after an opening is formed in the interlayer insulating film 19 and the Si ₃ N ₄ film 18 as an etching stopper layer, n-type source by selectively removing the Si ₃ N ₄ film 18 exposed in the opening -A via hole reaching the drain region 17 is formed.

Next, a polycrystalline Si layer doped with impurities is deposited by the LPCVD method, and is polished by the CMP method until the first interlayer insulating film 19 is exposed to form a polycrystalline Si plug 20 having conductivity. I do.

Then, again, a CVD method is used to cover the entire surface with a SiO.sub.2 having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m.
_After depositing _two films to form the second interlayer insulating film 23, a via hole reaching the gate lead-out wiring layer is provided. Then, a non-doped polycrystalline Si layer is deposited again by the LPCVD method. Polishing is performed by a CMP method until the insulating film 23 is exposed to form a polycrystalline Si plug.

Next, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm and a thickness of 50 to 2000 nm, for example, 200 n
After depositing a Ti layer of m (not shown), at a temperature of 400 to 660 ° C., for example, 500 ° C. in a nitrogen atmosphere,
Heat treatment is performed for 1 to 48 hours, for example, 6 hours, so that a polycrystalline Si plug and an upper non-doped polycrystalline Si constituting a gate extraction electrode and a gate electrode connected thereto are formed.
After the layer is replaced with Al, the layer is polished again using the CMP method until the surface of the second interlayer insulating film 23 is exposed, thereby forming the Al-substituted plug 39, the Al-substituted wiring layer 40, and the Al-substituted gate electrode 41.

As described above, in the fourth embodiment of the present invention, the gate electrode and the gate lead-out wiring layer, for which Al could not be used due to the high-temperature heat treatment accompanying the self-alignment step, are replaced with a low specific resistance. Since it can be replaced with Al,
The operating speed of the insulated gate semiconductor device can be increased.

In this case, the gate electrode has a multilayer structure of a non-doped polycrystalline Si layer / stopper / doped polycrystalline Si layer 36, and diffusion of Al is stopped by the stopper. And the doped polycrystalline Si layer 36 remains as it is,
Since _Vth does not fluctuate and does not damage the gate oxide film 13 and the channel region 42, the resistance of the gate electrode and the gate lead-out wiring layer can be reduced without impairing reliability.

Next, steps of a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view taken along the gate extraction electrode, and is the same as the above-described fourth embodiment except for the structures of the gate insulating film and the gate electrode. First, an element isolation oxide film 12 is formed in a predetermined region of a p-type silicon substrate 11 by selective oxidation, and then the exposed surface of the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is thermally oxidized to form a gate. An oxide film is formed, and the gate oxide film is converted into an oxynitride film 43 by performing a heat treatment in an ammonia atmosphere. In this case, the composition of the oxynitride film 43 has a higher nitrogen content toward the surface.

Next, a thickness of 10 to 1000 n
After depositing a non-doped polycrystalline Si layer having a thickness of, for example, 150 nm,
An iO ₂ film is deposited and etched in a predetermined pattern to form a gate electrode and a gate lead wiring layer.

Next, after ion implantation of As using the gate electrode and the protective film 15 as a mask to form n-type source / drain regions (not shown), a SiO ₂ film is deposited on the entire surface by the CVD method. The side wall 16 is formed by performing the reactive etching.

Next, a 10 to 100 nm thick Si film serving as a stopper film during etching is formed on the entire surface by CVD.
₃ N ₄ After the film 18 is deposited, Si ₃ N ₄ film 18 and the different thicknesses of the etching characteristics 10 on the entire surface by CVD
An interlayer insulating film 1 is formed by depositing a SiO ₂ film of 0 to 500 nm.
And 9, then, after an opening is formed in the interlayer insulating film 19 and the Si ₃ N ₄ film 18 as an etching stopper layer, n-type source by selectively removing the Si ₃ N ₄ film 18 exposed in the opening Forming a via hole reaching the drain region (not shown);

Next, a polycrystalline Si layer doped with impurities is deposited by the LPCVD method, and is polished by the CMP method until the first interlayer insulating film 19 is exposed. ) Are formed.

Next, again, the SiO.sub.2 having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m
_After depositing _two films to form the second interlayer insulating film 23, a via hole reaching the gate lead-out wiring layer is provided. Then, a non-doped polycrystalline Si layer is deposited again by the LPCVD method. Polishing is performed by a CMP method until the insulating film 23 is exposed to form a polycrystalline Si plug.

Next, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm and a thickness of 50 to 2000 nm, for example, 200 n
After depositing a Ti layer of m (not shown), at a temperature of 400 to 660 ° C., for example, 500 ° C. in a nitrogen atmosphere,
By performing a heat treatment for 1 to 48 hours, for example, 6 hours, the polycrystalline Si plug and the non-doped polycrystalline Si layer forming the gate extraction electrode and the gate electrode connected to the polycrystalline silicon plug are converted to A.
After the l-substitution, the substrate is polished again by the CMP method until the surface of the second interlayer insulating film 23 is exposed.
The replacement plug 39 and the Al replacement wiring layer 44 are formed.

As described above, in the fifth embodiment of the present invention, since the oxynitride film 43 having a small Al diffusion coefficient is used as the gate insulating film, similar to the fourth embodiment, The gate electrode and the gate lead-out wiring layer, for which Al could not be used due to the high-temperature heat treatment accompanying the self-alignment process, can be replaced with low-resistivity Al, so that the operating speed of the insulated gate semiconductor device can be increased. Can be

In particular, in the fifth embodiment,
Since the gate electrode and the entire gate lead-out wiring layer are replaced with Al, the n-channel IGFET and the p-channel IGFET
Since it can be used as any of the gate electrodes of the FET, the manufacturing process constant can be significantly reduced.

That is, in the case of the conventional Si gate IGFET, a surface channel type IGFE which is said to be effective in suppressing the short channel effect and the hot carrier effect is provided.
In order to configure T, a p-type Si gate electrode is provided for a p-channel IGFET, and an n-channel IGFE
For T, it was necessary to separately provide an n-type Si gate electrode, but when Al was replaced, this was not necessary, and in a CMOS (complementary MOSFET), a p-type Si gate electrode was used. The diode formed at the connection with the n-type Si gate electrode can be extinguished by Al substitution.

Also, in the fifth embodiment,
When forming the gate electrode, a stopper composed of a Ti film and a TiN film is not required, so that the manufacturing process can be shortened accordingly and the step caused by the gate structure can be reduced, so that the surface Is easy to planarize, and
Since the height of the lower polycrystalline Si plug can be reduced accordingly, the parasitic capacitance can be reduced.

Next, the steps of the sixth embodiment of the present invention will be described with reference to FIG. Note that the steps up to the Al substitution step are the same as those in the above-described second embodiment, so that the description of the intermediate production steps will be omitted. Referring to FIG. 7A, similarly to the above-described second embodiment, after forming a polycrystalline Si plug 24 serving as an upper plug, a 0.1 to 10 μm, for example, 2 μm thick Al is formed by sputtering.
Layer 25 and thickness 50 nm to 2000 nm, for example 200
A nm layer of Ti 26 is deposited.

Next, as shown in FIG. 7B, in a nitrogen atmosphere, at 400 to 660 ° C., for example,
After the polycrystalline Si plug 24 has been replaced with Al by performing a heat treatment at 500 ° C. for 1 to 48 hours, for example, 6 hours, the Al layer 25 is formed again to a thickness of 0.
Polishing is performed to a thickness of 1 to 2.0 μm, for example, 0.7 μm.

Then, the remaining Al layer 25 is etched into a predetermined pattern using a resist mask (not shown) as a mask by using a normal photo-etching process, so that the Al wiring layer 46 connected to the Al-substituted plug 27 is formed.
Is formed.

As described above, in the sixth embodiment of the present invention, since the wiring layer is formed by using the Al layer 25 for Al substitution, the step of forming the wiring layer becomes unnecessary. ,
The number of manufacturing steps can be reduced.

In the sixth embodiment,
In the Al substitution step, the substituted Si is mixed into the Al layer 25, and the Si content in the Al layer 25 is 0.1 to 5%.
And the electromigration resistance is improved, so that it is suitable as a wiring layer. The Si content in the substituted Al-substituted plug 27 is also about 0.1 to 5%.

The Si content in this case depends on the heat treatment temperature, the heat treatment time, and the absolute amount of the substituted portion, and the final Si content is 0.1 to 50 even at the end of the Si-substituted region. %, The heat treatment time or the like may be set according to the absolute amount of the substituted portion.

The technical idea of the sixth embodiment is also applied to the third embodiment. Instead of the W wiring layer 29, non-doped polycrystalline Si is used.
A wiring layer is provided, and polycrystalline S reaching the polycrystalline Si wiring layer is provided.
The i-plug may be formed simultaneously with the polycrystalline Si plug 24, and the polycrystalline Si wiring layer may be substituted with Al at the same time as the polycrystalline Si plug 24 is substituted with Al.

Next, referring to FIG. 8, a seventh embodiment of the present invention will be described.
The steps of the embodiment will be described. The polycrystalline Si plug 2
The steps up to the formation step 4 are the same as in the above-described sixth embodiment.
Therefore, the description of the manufacturing process in the middle is omitted. See FIG. 8 (a). As in the sixth embodiment described above, the
After forming the crystalline Si plug 24, the CVD method is used.
S having a thickness of 0.05 to 5 μm, for example, 0.5 μm
iO_TwoA film 47 is deposited and a normal photo etching process is performed.
Using SiO _TwoBy etching the film 47
And at least a wiring layer from which the polycrystalline Si plug 24 is exposed.
After forming the groove 48, the thickness is
0.1 to 10 μm, for example, 2 μm Al layer 25 and thickness
Ti having a thickness of 50 nm to 2000 nm, for example, 200 nm
Layer 26 is deposited.

Next, as shown in FIG. 8B, in a nitrogen atmosphere, at 400 to 660 ° C., for example,
After the polycrystalline Si plug 24 is replaced with Al by performing a heat treatment at 500 ° C. for 1 to 48 hours, for example, 6 hours, the Al layer 25 is again removed by CMP until the surface of the SiO ₂ film 47 is exposed. Is polished to form an Al wiring layer 46 buried in the wiring layer groove 48.

As described above, in the seventh embodiment of the present invention, although the step of forming the SiO ₂ film 47 is increased, the step of forming the wiring layer becomes unnecessary, and the insulating layer for covering the wiring layer is formed. Since the film formation process and the insulating film flattening process are not required, two processes of the wiring layer film formation process and the planarization process are compared with the above-described sixth embodiment in consideration of the entire process. Can be shortened.

Also, in the seventh embodiment,
Since the film thickness of the Al wiring layer 46 is determined by the film formation accuracy of the SiO ₂ film 47, it is necessary to make the thickness more accurate and uniform than in the sixth embodiment determined by the polishing accuracy of CMP. it can.

In the seventh embodiment, also,
In the Al substitution step, the substituted Si is mixed into the Al layer 25, and the Si content in the Al layer 25 is 0.1 to 5%.
And the electromigration resistance is improved, so that it is suitable as a wiring layer.

The technical concept of the seventh embodiment is also applied to the third embodiment. Instead of the W wiring layer 29, non-doped polycrystalline Si is used.
A wiring layer is provided, and polycrystalline S reaching the polycrystalline Si wiring layer is provided.
The i-plug may be formed simultaneously with the polycrystalline Si plug 24, and the polycrystalline Si wiring layer may be substituted with Al at the same time as the polycrystalline Si plug 24 is substituted with Al.

Next, the steps of the eighth embodiment of the present invention will be described with reference to FIG. First, after an element isolation oxide film 52 surrounding an n-type region 51 provided on a semiconductor substrate is provided, a non-doped layer having a thickness of 10 to 200 nm, for example, 50 nm is formed on the entire surface by LPCVD. Is deposited, and B is ion-implanted to be converted into a doped polycrystalline Si layer 53.

Next, a Ti film 54 having a thickness of 10 to 100 nm, for example, 20 nm serving as a contact metal is formed on the entire surface.
After a TiN film 55 having a thickness of 10 to 200 nm, for example, 50 nm serving as a barrier metal is sequentially deposited by a sputtering method, the thickness is again reduced to 1 by an LPCVD method.
A 0-1000 nm, for example 100 nm, non-doped polycrystalline Si layer 56 is deposited and then etched in a predetermined pattern to determine the outer periphery of the base electrode.

Next, a thickness of 0.05
After depositing an SiO ₂ film of about 5 μm, for example, 0.5 μm to form a first interlayer insulating film 57, an opening reaching the n-type region 51 for defining an internal base region is formed,
By performing the heat treatment, the doped polycrystalline Si layer 53 is formed.
To form a p-type external base region 58.

Next, B is ion-implanted into the opening at a low acceleration energy, and heat treatment is performed to form an internal base region 59, and then SiO 2 is formed on the entire surface by CVD.
By depositing _two films and performing anisotropic etching, sidewalls 60 are formed on the side walls of the opening.

Next, a non-doped polycrystalline Si layer having a thickness of 10 to 500 nm, for example, 50 nm is deposited on the entire surface by LPCVD, and then the doped polycrystalline Si layer 61 is ion-implanted with As. Convert to

Next, a Ti film 62 having a thickness of 10 to 100 nm, for example, 20 nm to be a contact metal is formed on the entire surface.
After a TiN film 63 having a thickness of 10 to 200 nm, for example, 50 nm serving as a barrier metal is sequentially deposited by a sputtering method, the thickness is again reduced to 1 by an LPCVD method.
A non-doped polycrystalline Si layer 64 of 0 to 1000 nm, for example, 100 nm is deposited.

Next, after etching so as to define the outer peripheral portion of the emitter electrode, the entire surface is etched by CVD.
An iO ₂ film is deposited and anisotropically etched to form sidewalls 65 on the side walls of the emitter electrode, and then subjected to a heat treatment to form a doped polycrystalline Si layer 6.
An n ⁺ -type emitter region 66 is formed by diffusing As from 1.

Next, by using the CVD method,
After depositing a SiO ₂ film of 0.05 to 5 μm, for example, 0.5 μm to form a second interlayer insulating film 67, a via hole reaching the polycrystalline Si layer 56 and the polycrystalline Si layer 64 is formed. After depositing a non-doped polycrystalline Si layer on the substrate, the polycrystalline Si plugs 68 and 69 are formed by polishing using a CMP method until the surface of the second interlayer insulating film 67 is exposed. Al layer 7 having a thickness of 0.1 to 10 μm, for example, 2 μm,
0 and a thickness of 50 to 2000 nm, for example, 200 nm T
An i-layer 71 is deposited.

Next, as shown in FIG. 9B, in a nitrogen atmosphere at 400 to 660 ° C., for example,
The polycrystalline Si plugs 68 and 69 and the polycrystalline Si layers 56 and 64 connected to them are replaced with Al by performing a heat treatment at 500 ° C. for 1 to 48 hours, for example, 6 hours, and then again using the CMP method. By polishing until the surface of the second interlayer insulating film 67 is exposed, the Al-substituted plugs 72 and 73 and the Al-substituted base electrode 74 and the Al-substituted emitter electrode 75 connected to the Al-substituted plug are formed.

As described above, in the eighth embodiment of the present invention, the self-alignment type bipolar transistor in which the electrode also serves as the solid-phase diffusion source and the use of Al was impossible because of the high-temperature processing step. Since the base electrode and the emitter electrode can be constituted by the substituted Al layer, the operation speed of the bipolar transistor can be improved and the power consumption can be reduced.

In this case, it is not always necessary to replace both the emitter electrode and the base electrode with Al, and only one of them may be replaced with Al.

Next, with reference to FIGS. 10 and 11, a manufacturing process according to the ninth embodiment of the present invention will be described. In addition,
FIGS. 10B and 11 are cross-sectional views taken along a dashed-dotted line connecting AA 'in FIG. 10A, and portions connected by vertical broken lines are omitted. 10A and 10B, first, a polycrystalline Si layer is deposited on a silicon substrate 81 via a base insulating film 82, and then P is ion-implanted to form a doped polycrystalline Si layer. The first quasi-wiring layer 8 is etched by etching into a predetermined pattern.
3, 84 are formed.

Next, after depositing a SiO ₂ film on the entire surface to form a first interlayer insulating film 85, the first layer sub-wiring layer 83 is formed.
Is formed, and then a polycrystalline Si layer is deposited. Then, P is ion-implanted to form a doped polycrystalline Si layer, and then etched into a predetermined pattern to form a second layer semi-interconnect. Layer 8
7, 88 are formed.

Next, after a SiO ₂ film is deposited on the entire surface to form a second interlayer insulating film 89, the second layer quasi-wiring layer 87 is formed.
Is formed, and then the polycrystalline S
An i-layer is deposited and polished by a CMP method to form a polycrystalline Si plug 90 for Al substitution.

Next, as shown in FIG. 11C, the entire surface is formed to a thickness of 0.1 to
After depositing an Al layer (not shown) having a thickness of 10 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 to 2000 nm, for example, 200 nm, the Al layer is deposited in a nitrogen atmosphere at 400 to 200 nm.
660 ° C., for example, at 500 ° C. for 1 to 48 hours,
For example, after performing a heat treatment for 6 hours, the polycrystalline Si plugs 90 and the second-level sub-wiring layers 87 and the first-level sub-wiring layers 83 connected thereto are replaced with Al, and then the second interlayer insulating film 89 is formed by using the CMP method. The Al-substituted plugs 91 and the Al-substituted wiring layers 92 and 93 are formed by polishing until the surface is exposed.

Next, as shown in FIG. 11D, by immersing in an etchant made of hydrochloric acid, an Al-substituted plug 91 substituted with Al,
By removing the replacement wiring layers 92 and 93, the cavity 9 is formed.
4,95 are formed. In this case, since the first-layer sub-wiring layer 84 and the second-layer sub-wiring layer 88 are not substituted with Al, a cavity is not formed by etching with hydrochloric acid.

The cavities 94 and 95 formed in this manner have a dielectric constant of about １ ／ of that of the SiO ₂ film. Therefore, the parasitic capacitance between the remaining first-level sub-wiring layers 84 and the second-level The parasitic capacitance between the wiring layers 88 can be significantly reduced.

Conventionally, an insulating film having a low dielectric constant has been developed to reduce the parasitic capacitance. However, even when such an insulating film having a low dielectric constant is used, the effect of reducing the parasitic capacitance is at most several tens.
Since it is about 0%, the effect of the present invention is remarkable, and there is no problem of generation of cracks due to heat treatment.

In such a removing step, since the etching rate by hydrochloric acid is very high, it is possible to almost completely remove the deep portion of the Al-substituted wiring layer in a relatively short time.

In the conventional manufacturing process, a dummy wiring layer of the same layer level is formed simultaneously with a normal wiring layer in order to facilitate flattening, and the remaining dummy wiring causes parasitic capacitance. However, by applying the technical idea of the ninth embodiment to a dummy wiring layer and using the first-layer sub-wiring layer 83 as a dummy wiring layer, the parasitic capacitance is reduced and the surface is flattened. Will be possible.

In the description of the ninth embodiment, the wiring layers in each layer are formed of a doped polycrystalline Si layer. In the part of the wiring layer which is not to be used, that is, the first sub-wiring layer 84 and the second sub-wiring layer 88 are replaced with Al via another polycrystalline Si plug, and in the etching step for cavitation,
The exposed surface of the polycrystalline Si plug may be covered with an etching resistant film.

In the ninth embodiment,
Although the cavity is formed by the wiring layer, it is not always necessary to be a pure wiring layer, and the cavity may be formed by using a polycrystalline Si plug embedded in the via hole.

The etchant is not limited to hydrochloric acid, but may be an acid other than HF, for example, sulfuric acid, or may be an alkaline solution. SiO ₂ , Si
₃ N _4, BPSG, or, since the SOG (spin on glass) is not etched, it is possible to efficiently remove the Al-substituted moiety.

Next, the steps of the tenth embodiment of the present invention will be described with reference to FIGS. FIG.
2B and FIG. 13 are cross-sectional views taken along a dashed line connecting AA 'in FIG. 12A, and a portion connected by a vertical broken line is omitted. Referring to FIGS. 12A and 12B, first, a polycrystalline Si layer is deposited on a silicon substrate 81 via a base insulating film 82, and then etched into a predetermined pattern to form a first-level sub-wiring layer 83. Form.

Next, after depositing a SiO ₂ film on the entire surface to form a first interlayer insulating film 85, the first layer sub-wiring layer 83 is formed.
Is formed, and then a polycrystalline Si layer is deposited, followed by etching into a pattern substantially orthogonal to the first sub-wiring layer 83 to form a second sub-wiring layer 87.

Next, after depositing an SiO ₂ film on the entire surface to form a second interlayer insulating film 89, the second layer quasi-wiring layer 87 is formed.
Is formed, and then a polycrystalline Si layer is deposited. Then, P is ion-implanted to form a doped polycrystalline Si layer, and then etched into a predetermined pattern to form a third-layer quasi-wiring layer. 97,
98 are formed. In FIG. 12A, for simplicity of illustration, a third region near the contact hole 96 is shown.
Elements other than the layer / semi-wiring layer 97 are omitted.

Next, after a SiO ₂ film is deposited on the entire surface to form a third interlayer insulating film 99, the third layer quasi-wiring layer 97 is formed.
Is formed, and then the polycrystalline S
An i-layer is deposited and polished by a CMP method to form a polycrystalline Si plug 100 for Al substitution.

Next, as shown in FIG. 13C, the entire surface is formed to a thickness of 0.1 to
After depositing an Al layer (not shown) having a thickness of 10 μm, for example, 2 μm and a Ti layer (not shown) having a thickness of 50 nm to 2000 nm, for example, 200 nm, 40 nm is formed in a nitrogen atmosphere.
By performing a heat treatment at 0 to 660 ° C, for example, 500 ° C for 1 to 48 hours, for example, 6 hours, the polycrystalline S
i-plug 100 and third-layer quasi-wiring layer 9 connected thereto
7, after replacing the second sub-wiring layer 87 and the first sub-wiring layer 83 with Al, the third interlayer insulating film 9 is formed by using the CMP method.
9 is exposed until the surface of the Al.sub.9 is exposed.
02 is formed.

Next, as shown in FIG. 13 (d), the Al-substituted plug 101, which has been substituted by Al, is immersed in an etchant made of hydrochloric acid.
The cavities 94, 95, 103 are formed by removing the l-substitution wiring layers 92, 93, 102. In this case, since the third sub-wiring layer 98 is not substituted with Al,
No cavity is formed by etching with hydrochloric acid.

The cavities 94, 95, 103 thus formed
Has a dielectric constant of about の of that of the SiO ₂ film. Therefore, the parasitic capacitance generated between the remaining third quasi-wiring layer 98 and an active region, an electrode, or a wiring layer provided on the silicon substrate 81. Can be greatly reduced.

In the tenth embodiment, the cavities are formed in a mesh using two wiring layers. However, the cavities may be formed in the interlayer insulating film by only one wiring layer. In particular, a mesh-like cavity can be formed by patterning one wiring layer into a mesh.

In the description of the tenth embodiment, the third sub-wiring layers 97 and 98 are
Although it is composed of an i-layer, it may be composed of a non-doped polycrystalline Si layer. In that case, the wiring layer of the portion that is not hollowed, that is, the third quasi-wiring layer 98 is formed of another polycrystalline Si layer. In the etching step for cavitation, the exposed surface of the polycrystalline Si plug may be covered with an etching resistant film in the etching step for cavitation.

The technical idea of the tenth embodiment can be used to reduce the parasitic capacitance between the layers in the multilayer wiring structure. In that case, the ninth embodiment can be used. In the same manner as in the above embodiment, a wiring layer which is not partially hollowed may be left and used as a normal wiring layer or a resistor.

Next, the steps of the eleventh embodiment of the present invention will be described with reference to FIGS. 14 (b) and FIG. 15 (d) show A-
FIG. 1 is a sectional view of a portion taken along a dashed line connecting A ′, and FIG.
4 (c), FIG. 15 (e) and FIG. 15 (f)
It is sectional drawing of the part along the dashed-dotted line which connects BB 'of (a).

Referring to FIGS. 14A to 14C, as in the conventional case, first, a predetermined region of the p-type silicon substrate 111 is formed.
Element isolation oxide film 112 was formed in the region by selective oxidation.
After that, a p-type silicon substrate surrounded by an isolation oxide film 112
The exposed surface of plate 111 is thermally oxidized to form gate oxide film 113.
And then deposit a non-doped polycrystalline Si layer
After that, P is ion-implanted to form a doped polycrystalline Si layer.
Then, a protective film 115 is formed on the entire surface by CVD.
Becomes SiO _TwoAfter depositing the film,
To form a gate electrode 114.

Next, the gate electrode 114 and the protective film 11
5 is used as a mask to ion-implant As to form an n-type source / drain region 116. Then, an insulating film 117 made of a thin SiO ₂ film is deposited on the entire surface by CVD, and then non-doped polycrystalline Si. The layers are deposited and polycrystalline Si sidewalls 118 are formed by anisotropic etching.

Next, the polycrystalline Si sidewall 118
With the mask as a mask, the exposed portion of the thin insulating film 117 is etched.
To remove the n-type source / drain region 116.
After that, the etching process is performed on the entire surface by CVD.
Si with a thickness of 10-100 nm to be a topper film_ThreeN_FourMembrane 1
After depositing 19, Si is deposited on the entire surface by CVD. _Three
N_FourThickness 100 to 5 with different etching characteristics from film 119
00nm SiO_TwoA film is deposited to form an interlayer insulating film 120
After that, on the element isolation oxide film 112, the first
On the polycrystalline Si sidewall 118 on the interlayer insulating film 120
The opening 121 which reaches is provided.

15 (d) and (e). Next, non-doped polycrystalline S
After the i-layer is deposited, the opening 1 is polished by a CMP method until the first interlayer insulating film 120 is exposed.
A polycrystalline Si plug (not shown) is formed on 21.

Next, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm and a thickness of 50 to 2000 nm, for example, 200 nm
Is deposited in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C., after depositing a Ti layer (not shown).
The polycrystalline Si plug and the polycrystalline Si sidewall 118 connected thereto are replaced with Al by performing a heat treatment for up to 48 hours, for example, 6 hours, and then until the surface of the first interlayer insulating film 120 is exposed using the CMP method. Grind.

Next, by immersing in an etchant made of hydrochloric acid, an Al-substituted plug
By removing the l-substitution sidewall, a cavity 122 is formed on the side of the gate electrode. In this case,
Since the gate electrode 114 is covered with the protective film 115 and the insulating film 117, the gate electrode 114 is not replaced with Al, and does not become hollow due to etching with hydrochloric acid.

Next, a via hole reaching the n-type source / drain region 116 is provided in the first interlayer insulating film 120, and a source / drain electrode 123 is formed by embedding Al or the like.

As described above, in the eleventh embodiment of the present invention, since the source / drain electrodes 123 are provided on the sides of the gate electrode via the low dielectric constant cavities 122,
Parasitic capacitance between the gate electrode 114 and the source / drain electrode 123 can be significantly reduced, thereby making it possible to further increase the operation speed of the element.

In the description of the eleventh embodiment, the polycrystalline Si side wall 118 is not
Although the Al substitution and removal are performed before the formation of the drain electrode 123, the Al substitution and removal step may be performed in a step close to the final step.

In this case, the gate electrode or the gate insulating film may be replaced with Al in the same manner as in the above-described fourth or fifth embodiment. The drain electrode is formed as a polycrystalline Si plug as in the fourth embodiment,
Alternatively, it may be connected to an Al-substituted plug via a stopper pad.

Next, the steps of the twelfth embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a schematic plan view of a memory cell region of a DRAM. First, on an exposed surface of a silicon substrate surrounded by an element isolation oxide film 137, doped polycrystalline Si is provided via a gate insulating film. The source / drain region 1 is formed by ion implantation using the word line 131 made of a layer as a mask.
33 are formed.

Next, after providing the first interlayer insulating film, a via hole reaching the contact portion 134 of the source / drain region 133 is provided, and a lower plug 135 made of doped polycrystalline Si is formed in the via hole. Metal thickness of 10 to 100 nm, for example,
A 20 nm Ti film (not shown), and then a 10 to 200 nm thick, for example, 50 nm
After sequentially depositing an N film (not shown) by a sputtering method, a non-doped polycrystalline Si layer is deposited on the entire surface and patterned to form a bit line 132 connected to each lower plug.

Next, after a second interlayer insulating film is provided, a via hole reaching the bit line 132 is formed, and the via hole is filled with an upper plug 136 made of polycrystalline Si. 0.1 ~
A 10 μm, for example 2 μm, Al layer (not shown) and a 50-2000 nm, for example, 200 nm, Ti layer (not shown) are deposited, and then 400 nm in a nitrogen atmosphere.
The upper plug 136 and the bit line 132 connected to the upper plug 136 are subjected to heat treatment at a temperature of 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours, and then the second interlayer insulating film is formed by a CMP method. Polish until the surface is exposed.

When the lower plug 135 is replaced with Al, as shown in FIG. 17A, a contact metal having a thickness of 10 to 100 nm, for example, 20 nm is formed on the surface of the via hole 139 as a contact metal.
i-film 140 and thickness 10 to 200 n to be barrier metal
m, for example, a 50 nm TiN film 141 may be provided, and the lower plug 135 may be provided simultaneously with the bit line 132.
In this case, an Al substitution treatment at a low temperature is required.

As shown in FIG. 17B, when the lower plug 135 is not replaced with Al, as in the embodiment, the bit line 132 itself is replaced with a thick contact metal as in the third embodiment. 10-1
A Ti film 140 having a thickness of 00 nm, for example, 20 nm and a thickness of 10 to 200 nm, for example, 50 nm serving as a barrier metal
And a non-doped polycrystalline Si layer 142 having a thickness of 10 to 1000 nm, for example, 300 nm, deposited through a stopper made of the TiN film 141.

In the case where only the word line 131 or both the word line 131 and the bit line 132 are replaced with Al, the word line 131 or the gate insulating film is replaced with the fourth line at the time of replacing the word line 131 with Al. Alternatively, similarly to the fifth embodiment, an upper plug may be provided also for the word line 131, and the word line 131 may be replaced with Al.

Also, in FIG. 16, for simplicity of description, a storage electrode forming a capacitor and a plug for connecting the storage electrode to the source / drain region 133 are not shown. The storage electrode and the upper plug may be replaced with Al simultaneously with the replacement of the bit line 132 or the like by forming the upper plug with a stopper pad between the two.

FIG. 18A is a diagram showing IGFE constituting a peripheral circuit of a DRAM.
T schematically shows T, the source / drain region 133 and the gate contact region 144 for the gate electrode 143 and the lower plug 135 that are not desired to be replaced with Al.
In this case, the upper pad 136 may be provided on the conductive lower pad 135 via the cushion-shaped stopper pad 145 as in the second embodiment, and only the upper pad 136 may be replaced with Al.

FIG. 18B shows a schematic configuration of a resistor using a part of the bit line 132. The resistor includes a non-doped polycrystalline Si layer or a doped polycrystalline Si layer. Plug 13 having conductivity in contact regions 146 at both ends of the resistor
5, the upper pad 136 is provided via a cushion-shaped stopper pad 145, and only the upper pad 136 may be replaced with Al.

As described above, in the twelfth embodiment of the present invention, at least one of the bit line 132 and the word line 131 is replaced with Al, so that the DRAM can operate at a high speed. In addition, the backing contact, which is provided to avoid a signal delay due to the high resistance of the bit line or word line made of polycrystalline Si, becomes unnecessary.

The bit line 132 or the word line 1
The Al substitution of 31 is effective as the degree of integration is improved. That is, although the distance of Al substitution is about 100 μm, when the integration degree is improved, not only the width of the wiring layer is reduced, but also the length of one continuous wiring layer is shortened. As a result of reducing the size of one cell, the length of the bit line 132 or the word line 131 is also reduced. Therefore, such a reduction in the resistance of the bit line 132 or the word line 131 due to the Al substitution is 256 Mbit DRA.
It becomes possible only after M.

In a DRAM of an earlier generation, the length of the bit line 132 or the word line 131 is too long, which is not possible, and becomes possible only with the progress of the generation and the miniaturization.

The bit line 132 or the word line 13
With the reduction of the resistance of 1, the thickness of the bit line 132 or the word line 131 can be reduced, whereby the parasitic capacitance between the adjacent bit lines 132 or between the word lines 131 can be reduced.

Further, the bit line 132 or the word line 1
As the resistance of the memory device 31 decreases, the number of cells that can be connected to one bit line 132 or one word line 131 can be increased, so that the degree of integration of a memory device such as a DRAM can be improved.

By providing a stopper pad in a portion where Al substitution is not desired, such as a resistance element,
Since Al does not diffuse, circuit elements having arbitrary characteristics can be separately formed by the stopper pads.

Although the embodiments of the present invention have been described above, the present invention can be modified in various ways. For example, the Ti layers 26 and 71 provided on the replacement Al layers 25 and 70 are not necessarily required. Not something.

The polycrystalline S in each of the above embodiments is
In the i-plugs 20, 24, etc., after forming a via hole in the interlayer insulating film, a polycrystalline silicon film is deposited and removed by a CMP method to form a plug embedded in the via hole. May be patterned into a columnar shape, and the periphery thereof may be buried with an insulating film, and the “plug” in the present specification means both electrodes.

Also, a step of forming a plug, and
In the step of removing the layer, a CMP method is used.
The present invention is not limited to the CMP method, but may employ an etch back by dry etching.

In the first to seventh and eleventh embodiments, the source / drain regions have a single structure for the sake of simplicity.
An LDD (Lightly Doped Drain) structure may be adopted. In this case, ions are implanted using the gate electrode and the protective film as a mask to form an LDD region, and then ions are implanted using the sidewalls as a mask. Thus, the source / drain regions may be formed.

In the first to fourth, sixth, and seventh embodiments, the lower polycrystalline Si plug 2
Although a stopper pad made of a Ti film and a TiN film is provided so as to be in contact with 0, when the surface of the polycrystalline Si plug 20 is silicided in advance, the Ti film 21 as a contact metal is not necessary. Absent.

In the description of the above embodiments, Ti is used as the contact metal.
The silicide containing W, Co, Ni, Ta, or Ti can be used.

The barrier metal is not limited to TiN, but may be any conductive film that can prevent the diffusion of Al. For example, TaN, WN, or SiC can be used.

In each embodiment of the present invention,
Al-substituted polycrystalline Si layers are almost non-doped layers, but the doped polycrystalline Si layers may be substituted with Al as in the ninth and tenth embodiments.

In each embodiment of the present invention,
In consideration of low resistivity characteristics and versatility, Al is used as the replacement metal, but Cu, Ag, Ru, Pt, or the like may be used, and when Cu is used, Al
A wiring layer having a lower specific resistance than the wiring layer and a high electromigration resistance can be formed.

In the description of each embodiment of the present invention, the region to be replaced is made of polycrystalline silicon. However, the present invention is not limited to polycrystalline silicon, but may be made of microcrystalline silicon or amorphous silicon. However, in some cases, single crystal silicon may be used.

In the description of each embodiment of the present invention, As is doped into the polycrystalline Si layer by ion implantation or the like in order to form a shallow diffusion region or the like, but P may be used. In the case where the conductivity type is inverted, B may be doped.
Although an O ₂ film is used, Si ₃ N ₄ may be used.

In the description of each embodiment of the present invention, a conductor film other than polycrystalline silicon is deposited by a sputtering method. However, the present invention is not limited to the sputtering method. It may be used.

In each embodiment of the present invention, an n-channel IGFET or an npn transistor has been described.
It goes without saying that the present invention is also applied to the np transistor.

The PAS technology of the present invention is applied to various contact plugs and capacitor plugs in addition to the contact plugs in the embodiment.

[0244]

According to the present invention, since the high-temperature processing step is involved in the subsequent steps, the wiring layer and the electrode in the portion where Al could not be used are subjected to the polysilicon-aluminum replacement method after the high-temperature processing step is completed. Since the resistance is reduced by replacing the Al with Al, the operating speed of various semiconductor devices can be greatly increased, and power consumption is greatly reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a process according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory view of a process according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a process according to a sixth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a process according to a seventh embodiment of the present invention.

FIG. 9 is an explanatory diagram of a process according to an eighth embodiment of the present invention.

FIG. 10 is an explanatory view of a step in the middle of a ninth embodiment of the present invention.

FIG. 11 is an explanatory view of a step subsequent to FIG. 10 in a ninth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a process in the middle of a tenth embodiment of the present invention.

FIG. 13 is an explanatory diagram of the steps following FIG. 12 in the tenth embodiment of the present invention.

FIG. 14 is an explanatory diagram of a step in the middle of an eleventh embodiment of the present invention.

FIG. 15 is an explanatory view of a step after FIG. 14 in the eleventh embodiment of the present invention.

FIG. 16 is an explanatory diagram of a twelfth embodiment of the present invention.

FIG. 17 is an explanatory diagram of a modification of the twelfth embodiment of the present invention.

FIG. 18 is an explanatory diagram of a peripheral circuit section according to a twelfth embodiment of the present invention.

FIG. 19 is an explanatory view of a conventional PAS step.

FIG. 20 is an explanatory diagram of an application example of the conventional PAS technology.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 gate insulating film 3 gate electrode 4 source / drain region 5 lower plug 6 stopper 7 upper plug 8 replacement metal 9 silicon absorber layer 10 metal replacement plug 11 p-type silicon substrate 12 element isolation oxide film 13 gate oxide film Reference Signs List 14 gate electrode 15 protective film 16 sidewall 17 n-type source / drain region 18 Si ₃ N ₄ film 19 first interlayer insulating film 20 polycrystalline Si plug 21 Ti film 22 TiN film 23 second interlayer insulating film 24 polycrystalline Si plug 25 Al layer 26 Ti layer 27 Al substitution plug 28 W pad 29 W wiring layer 30 Al substitution plug 31 Polycrystalline Si pad 32 Polycrystalline Si wiring layer 33 Polycrystalline Si plug 34 Al substitution pad 35 Al substitution wiring layer 36 Doped polycrystalline Si layer 37 Ti film 38 TiN film 39 Al substitution Lug 40 Al-substituted wiring layer 41 Al-substituted gate electrode 42 Channel region 43 Oxynitride film 44 Al-substituted wiring layer 45 Polycrystalline Si wiring layer 46 Al wiring layer 47 SiO ₂ film 48 Wiring layer groove 51 N-type region 52 Element isolation Oxide film 53 Doped polycrystalline Si layer 54 Ti film 55 TiN film 56 Polycrystalline Si layer 57 First interlayer insulating film 58 External base region 59 Internal base region 60 Sidewall 61 Doped polycrystalline Si layer 62 Ti film 63 TiN film 64 Multi Crystal Si layer 65 Side wall 66 Emitter region 67 Second interlayer insulating film 68 Polycrystalline Si plug 69 Polycrystalline Si plug 70 Al layer 71 Ti layer 72 Al substitution plug 73 Al substitution plug 74 Al substitution base electrode 75 Al substitution emitter electrode 81 Silicon substrate 82 Base insulating film 83 First quasi-wiring layer 84 First quasi-wiring layer 85 First interlayer insulating film 86 Contact hole 87 Second quasi-wiring layer 88 Second quasi-wiring layer 89 Second interlayer insulating film 90 Polycrystalline Si plug 91 Al substitution Plug 92 Al-substituted wiring layer 93 Al-substituted wiring layer 94 Cavity 95 Cavity 96 Contact hole 97 Third layer quasi-wiring layer 98 Third layer quasi-wiring layer 99 Third interlayer insulating film 100 Polycrystalline Si plug 101 Al-substituted plug 102 Al Replacement wiring layer 103 cavity 111 p-type silicon substrate 112 element isolation oxide film 113 gate oxide film 114 gate electrode 115 protective film 116 n-type source / drain region 117 insulating film 118 polycrystalline Si sidewall 119 Si ₃ N ₄ film 120 interlayer insulation Film 121 opening 122 cavity 123 source / drain electrode 131 word line 1 2 Bit line 133 Source / drain region 134 Contact part 135 Lower plug 136 Upper plug 137 Element isolation oxide film 138 First interlayer insulating film 139 Via hole 140 Ti film 141 TiN film 142 Polycrystalline Si layer 143 Gate electrode 144 Gate contact region 145 Stopper Pad 146 Contact region 201 Silicon substrate 202 SiO ₂ film 203 Contact hole 204 Polycrystalline Si layer 205 Polycrystalline Si plug 206 Al layer 207 Al substitution plug 211 P-type silicon substrate 212 Element isolation oxide film 213 Gate oxide film 214 Gate electrode 215 protective film 216 sidewall 217 n-type source and drain regions 218 Si ₃ n ₄ film 219 interlayer insulating film 220 Ti film 221 TiN film 222 polycrystalline Si plug 22 Al layer 224 Ti layer 225 Al substituted plug

Claims (33)

[Claims] 1. A semiconductor device comprising a stopper serving as a barrier to a replacement metal, at least between a lower plug and a metal replacement plug. 2. The semiconductor device according to claim 1, wherein the stopper serving as a barrier to the replacement metal also serves as a wiring layer. 3. The semiconductor device according to claim 2, wherein said wiring layer comprises a conductor layer serving as a stopper and a metal substitution layer provided on said conductor layer. 4. A semiconductor device, wherein a gate electrode has a multilayer structure including a metal substitution layer, a conductor layer serving as a stopper for a substitution metal, and an impurity-doped silicon layer from an upper layer side. 5. A semiconductor device, wherein a gate electrode is formed of a metal substitution layer, and a gate insulating film is formed of an insulating film containing nitrogen. 6. An electrode which is in contact with a semiconductor substrate has a multilayer structure including a metal replacement layer, a conductor layer serving as a stopper for a replacement metal, and a silicon layer doped with impurities from the upper layer side. Semiconductor device. 7. The semiconductor device according to claim 6, wherein the electrode in contact with the semiconductor substrate is a base extraction electrode of a bipolar transistor. 8. A semiconductor device wherein a bit line of a dynamic random access memory is formed of a metal substitution layer. 9. The semiconductor device according to claim 8, wherein a word line of the dynamic random access memory is formed of a metal substitution layer. 10. The semiconductor device according to claim 1, wherein the metal replacement plug or the metal replacement layer contains 0.1 to 50% of silicon. 11. The semiconductor device according to claim 1, wherein the metal-substituted plug or the metal-substituted layer contains strontium or lithium. 12. The method according to claim 1, wherein a main component of the metal substitution plug or the metal substitution layer is any one of Al, Cu, Ag, Ru, and Pt. 13. The semiconductor device according to claim 1. 13. A semiconductor device according to claim 1, wherein a stopper serving as a barrier to a replacement metal is provided at least between the lower plug and the upper plug made of silicon, and the upper plug is replaced with the replacement metal. Production method. 14. The method according to claim 1, wherein the stopper serving as a barrier to the replacement metal also serves as a wiring layer.
4. The method for manufacturing a semiconductor device according to item 3. 15. The wiring layer includes a conductor layer serving as a stopper and a silicon layer provided on the conductor film, a silicon plug reaching the silicon layer is provided, and the silicon layer is replaced with a replacement metal. The method for manufacturing a semiconductor device according to claim 14, wherein: 16. A gate electrode formed from a silicon layer on an upper layer side,
A conductive layer serving as a stopper for the replacement metal, and a multilayer structure including a silicon layer doped with impurities, wherein only the upper silicon layer of the gate electrode is replaced with the replacement metal. A method for manufacturing a semiconductor device. 17. A gate electrode comprising a silicon layer, a gate insulating film comprising a nitrogen-containing insulating film,
A method for manufacturing a semiconductor device, wherein the gate electrode is replaced with a replacement metal. 18. An electrode in contact with a semiconductor substrate has a multilayer structure including a silicon layer from the upper side, a conductor layer serving as a stopper for a replacement metal, and a silicon layer doped with impurities. A method for manufacturing a semiconductor device, comprising using a silicon layer as a diffusion source and replacing the upper silicon layer with a replacement metal. 19. The method according to claim 18, wherein the electrode in contact with the semiconductor substrate is a base extraction electrode of a bipolar transistor. 20. The method according to claim 13, wherein after replacing the upper plug or the silicon layer with a replacement metal, the replacement metal is etched into a predetermined shape and used as a wiring layer. 13. The method for manufacturing a semiconductor device according to item 5. 21. Prior to providing the replacement metal, an insulating film is provided with a wiring layer groove for exposing the upper plug or silicon plug in at least a part thereof, and the upper plug or silicon layer is formed of the replacement metal. 20. The method for manufacturing a semiconductor device according to claim 13, wherein after the replacement, the replacement metal is reduced so as to be embedded in the wiring layer groove and used as a wiring layer. . 22. A wiring layer composed of a silicon layer,
A method for manufacturing a semiconductor device, comprising: performing a heat treatment process at a temperature of 00 ° C. or higher, and then replacing with a replacement metal 8. 23. The method according to claim 22, wherein the wiring layer formed of the silicon layer is a bit line of a dynamic random access memory. 24. The method according to claim 22, wherein the wiring layer made of the silicon layer is a word line of a dynamic random access memory. 25. A stopper pad is provided in a portion of a plug or a wiring layer of a circuit element constituting a peripheral circuit of the dynamic random access memory in which a replacement metal enters in a non-replacement portion. A method for manufacturing a semiconductor device according to claim 23. 26. The method of manufacturing a semiconductor device according to claim 25, wherein the non-replaced portion forms a resistor. 27. The method according to claim 13, wherein the metal replacement plug or the metal replacement wiring layer after replacement with the replacement metal contains 0.1 to 50% of silicon. A method for manufacturing a semiconductor device. 28. The method according to claim 13, wherein the replacement metal contains strontium or lithium. 29. After replacing a silicon plug or a silicon wiring layer provided on a semiconductor substrate via an insulating film with a replacement metal, at least a part or the whole of the metal-substituted plug or the metal-substituted wiring layer is replaced. A method for manufacturing a semiconductor device, comprising: removing a hollow portion to form a hollow portion. 30. The method of manufacturing a semiconductor device according to claim 29, wherein the cavity separates wiring layers of the same level in the cavity. 31. The method according to claim 29, wherein the cavity separates a wiring layer between layers different from the cavity. 32. The semiconductor device according to claim 29, wherein the cavity is formed by replacing a side wall made of a silicon layer provided on a side wall of the gate electrode with a metal for replacement and then removing the side wall. The manufacturing method of the semiconductor device described in the above. 33. The replacement metal is Al, Cu, A
33. The method for manufacturing a semiconductor device according to claim 13, wherein the method is any one of g, Ru, and Pt.