JP4715065B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a TAT DRAM cell and a method for manufacturing the same, and more specifically, a TAT DRAM cell having a structure in which a gate electrode and a diffusion layer take-out electrode have a high withstand voltage and a gate electrode resistance is low. And a method for manufacturing the same.
[0002]
[Prior art]
As a semiconductor device that processes a large amount of information at high speed, an Emb (Embeded) DRAM in which a large-capacity DRAM and a high-speed logic integrated circuit are embedded in one chip has been put into practical use.
However, in response to demands for miniaturization of semiconductor devices that are accelerating year by year, various problems as described below have become apparent in Emb DRAMs.
[0003]
(1) In order to maintain the high performance of the transistor against the reduction of the DRAM memory cell, the substrate concentration of the semiconductor substrate on which the semiconductor device is formed is increasing, and as a result, the concentration of the junction portion of the DRAM portion is increased. The change is also becoming steep.
For this reason, the electric field applied to the junction is becoming stronger and it is difficult to suppress the junction leakage to the ppm order in a megabit DRAM. As a result, it has been difficult to maintain the data retention characteristics (generally referred to as tail characteristics) of a DRAM that has been conventionally controllable with a margin as in the prior art.
In this situation, there is no effective measure other than increasing the capacitor capacity for each generation.
[0004]
(2) With the reduction in the size of DRAM cells, the contact area between the diffusion layer take-out contact (take-out electrode) and the diffusion layer is narrowed, and the contact resistance is increasing at about twice the rate of generation. In the generation after 0.1 μm, the contact resistance is expected to be several kilo ohms, and the resistance value is expected to be comparable to the on-resistance of the memory cell transistor.
As the contact resistance increases, the contact resistance variation greatly affects not only the memory cell / transistor but also the operation of the DRAM, particularly the high-speed operation. Therefore, higher positioning accuracy between the contact and the diffusion layer is achieved in the DRAM manufacturing process. Required. In particular, in DRAMs that require high-speed operation, improvement in positioning accuracy is a problem in securing performance.
[0005]
(3) Also, with the reduction in the size of DRAM cells, the interlayer insulation distance between the word line and the diffusion layer lead-out contact formed on the side of the word line is decreasing year by year. For example, in order to ensure a withstand voltage between the word line and the diffusion layer lead-out contact, in a megabit DRAM, the interlayer insulation distance between the word line and the diffusion layer lead-out contact is 20 to 30 nm. However, if the trend of reducing the area of the DRAM cell continues as it is, the interlayer insulation distance between the word line and the diffusion layer lead-out contact will be 20-30 nm or less in the generation of 0.1 μm and later.
[0006]
(4) Conventionally, the WSi / doped polysilicon polycide structure has been adopted for DRAM word lines to alleviate the problem of signal delay. However, along with recent miniaturization of DRAMs, the aspect ratio of word lines has increased. In addition, it has become difficult to make the wiring structure of the word line sufficiently low in order to suppress the signal delay of the word line. In particular, in an Emb DRAM that requires high-speed operation, this word line delay is a serious problem that affects the access time of the DRAM.
Therefore, salicide structure wiring has been put to practical use in order to reduce the resistance of the gate electrode (word line).
However, when the salicide structure is applied to the gate electrode (word line) of a DRAM cell, the offset SiO₂This becomes an obstacle to the reduction in DRAM cell size. In addition, in order to maintain the data retention characteristics, there is a problem that a process for preventing the formation of salicide in the diffusion layer of the DRAM is required. At present, it is difficult to adopt the salicide structure for the gate electrode. .
[0007]
(5) Further, along with the reduction in the size of the DRAM, it is indispensable to provide an opening with no margin when forming the storage node contact of the DRAM, and, like the diffusion layer contact, the distance between the contact opening and the word line is increased. The distance is almost the limit of the withstand voltage.
As a result, since the contact diameter is reduced, a technique for efficiently suppressing an increase in resistance with a small contact diameter is required.
[0008]
(6) On the other hand, the transistor performance in the logic part has been improved remarkably, and in particular, P in which boron ions are ion-implanted to suppress off-leakage of the P-channel transistor.⁺A gate electrode has been commonly used.
By the way, P⁺For the gate electrode, P by heat treatment⁺When the gate electrode is activated, there is a problem of so-called “penetration” in which impurity boron diffuses to the substrate side. This causes serious problems such as variations in characteristics of P-channel transistors, depletion of gate electrodes, and deterioration of gate insulation.
In addition, doped polysilicon, which is widely used for DRAM diffusion layer contacts, is an indispensable material for activation by heat treatment, and attention must be paid to consistency when mixed.
[0009]
[Problems to be solved by the invention]
In the future 0.1 μm generation and beyond, it is necessary to further reduce the thickness of the gate oxide film, and as described above, there is a possibility that the technology that can be tolerated in the current 0.18 μm generation cannot be applied.
Therefore, in order to maintain the trend of chip performance improvement, it is expected that a fundamental improvement of the Emb / DRAM structure itself is required.
[0010]
Therefore, the word line of the DRAM part is formed on the substrate as an element structure that can solve all the above-mentioned six problems that are expected to be manifested in Emb. DRAM of 0.1 μm or more and can maintain the trend of improving chip performance. A Trench Access Transistor (TAT) DRAM cell has been proposed that is buried in the “groove”.
[0011]
Here, with reference to FIG. 11, a configuration of a semiconductor device in which a DRAM memory unit and a logic unit are mixedly mounted, and the DRAM memory unit is composed of TAT / DRAM cells will be described. FIG. 11 is a cross-sectional view showing a configuration of a transistor portion of a TAT / DRAM cell. Note that since the logic portion of the semiconductor device is not directly related to the present invention, the illustration and description of FIG. 11 are omitted.
The transistor section 10 of the TAT / DRAM cell is an N-channel transistor, and as shown in FIG. 11, a gate electrode 18 embedded in a trench 14 formed in a semiconductor substrate, for example, a Si substrate 12 via a gate insulating film 16. And a diffusion layer 20 formed in the upper layer of the substrate on the side of the groove 14, and a diffusion layer extraction electrode 22 connected to the diffusion layer 20.
[0012]
Further, the configuration of the TAT / DRAM cell 10 will be described with reference to FIG.
As shown in FIG. 11, the element isolation region 24 is formed in the Si substrate 12 at a depth of, for example, about 0.1 μm to 0.2 μm by, for example, STI (Shallow Trench Isolation) technique. A trench 14 is formed in the Si substrate 12 and the element isolation region 24 at a depth of, for example, about 50 nm to 100 nm, and a word line (gate electrode) 18 is formed in the trench 14 via a gate insulating film 16. .
[0013]
A P well 26 is provided in a region between the two element isolation regions 24, that is, a transistor formation region. A region of the Si substrate 12 between the P well 26 and the trench 14 has a high concentration, for example, 1.. 0x10¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^ThreeChannel diffusion layer 28 is formed.
On the other hand, the semiconductor substrate regions on both sides and the upper part of the groove 14 are almost at a substrate concentration and extremely low, for example, 1.0 × 10.¹⁷/ Cm^Three~ 1.0 × 10¹⁸/ Cm^ThreeIt has become.
As the gate insulating film 16, a silicon oxide film obtained by thermal oxidation of silicon can be used. As the gate insulating film 16, a silicon oxide film having a thickness of, for example, about 1.5 nm to 2 nm is formed.
[0014]
Further, the word line (gate electrode) 18 is formed so that the surface thereof is at least 30 nm to 50 nm, preferably 40 nm to 50 nm below the surface of the Si substrate 12 above the groove 14. A breakdown voltage with respect to the diffusion layer extraction electrode 22 is secured.
The word line (gate electrode) 18 has a conventional WSi in order to suppress signal delay.₂Instead of the polycide structure made of / polysilicon, for example, a heat-resistant polymetal gate structure made of tungsten / tungsten nitride / polysilicon or cobalt / cobalt silicide / polysilicon is used. Thus, problems such as boron penetration and segregation at the tungsten nitride interface do not occur.
In FIG. 11, 18a indicates tungsten / tungsten nitride or cobalt / cobalt silicide.
[0015]
In addition, in the semiconductor substrate region above the groove 14, 1 × 10¹⁸cm^-3~ 3x10¹⁸cm^-3A source / drain diffusion layer 20 having a moderate concentration is formed.
Since it is desirable to relax the electric field strength with the Si substrate 12, the semiconductor substrate region at the junction with the diffusion layer 20 is set to a low concentration together with the diffusion layer 20, and a junction with a low electric field strength is formed.
[0016]
Since the Si substrate 12 under the diffusion layer 20 is a region where ions are hardly implanted, 1 × 10¹⁶cm^-3~ 5x10¹⁷cm^-3The concentration is very thin.
Thereby, the NP junction of this example becomes a super graded junction. This ultra-graded junction reduces the electric field at the time of reverse bias, and can thereby suppress a junction leak that is worse by about two digits than usual, which occurs in a defective bit of the order of only ppm in a megabit class DRAM. This data retention characteristic of defective bits dominates the chip performance of the DRAM, and is an important technique for maintaining the data retention characteristic in future DRAMs.
Substrate concentration is 5 × 10¹⁶cm^ThreeIf so, data retention characteristics of 500 msec or more at 85 ° C. can be expected. This is a performance comparable to the data retention characteristics of DRAMs that are 4-5 generations before.
[0017]
As described above, since the gate electrode 18 is embedded in the Si substrate 12 through the gate insulating film 16 and the diffusion layer 20 is formed in the upper layer of the Si substrate 12, the gate electrode 18 is formed in the channel. It is formed so as to go around the substrate region on the bottom side of the groove 14.
As a result, the transistor portion of the DRAM can form a channel by rounding the groove 14 to ensure a long effective channel length. Therefore, a DRAM having a remarkable short channel effect that is used by applying a back bias. The transistor transistor characteristics of the cell can also be stabilized.
[0018]
On the Si substrate 12 including the diffusion layer 20, except for the groove 14, a CVD / SiO film having a thickness of 20 nm to 40 nm is formed.₂A film 32 is formed. SiO₂The membrane 32 is
(1) Plays the role of a buffer film when performing ion implantation to form a P-well,
(2) At the time of ion implantation for adjusting the substrate concentration of the DRAM cell transistor to be performed later, it acts as a stopper against ion implantation, realizing a reduction in the substrate concentration of the junction portion of the DRAM,
(3) When salicide is formed on the surface of the word line embedded in the groove 14 in a later process, it plays a role of preventing the salicide from being formed in the diffusion layer of the DRAM portion.
[0019]
Further, the upper part of the groove wall of the groove 14 has a 10 nm-thickness SiO.₂The film 34 is SiO as a side wall protective wall of the groove 14.₂Provided up to the upper surface of the film 32, and further SiO₂On the film 32, SiO₂A SiN cap layer 36 having a thickness of 20 to 30 nm is provided along the film 34 and on the gate electrode 18.
[0020]
A first interlayer insulating film 38 is formed on the SiN cap layer 36, and the surface is flattened.
First interlayer insulating film 38, SiN cap layer 36, and CVD / SiO 2₂A diffusion layer extraction electrode 22 that penetrates the film 32 and is connected to the diffusion layer 20 is formed in a plug shape from phosphorous doped polysilicon. The lead-out electrode 22 is formed as large as possible so that the entire surface of the diffusion layer 20 contacts and the contact resistance is reduced.
The extraction electrode 22 is connected to a capacitor and a bit line (not shown) according to the design.
[0021]
By the way, as described above, when applying the structure of the TAT / DRAM cell, in order to maintain the withstand voltage between the diffusion layer extraction electrode 22 and the gate electrode 18, it is necessary to secure a physical distance between them. However, since the physical distance provided between the diffusion layer take-out electrode 22 and the gate electrode 18 is determined from the electrode arrangement and the transistor characteristics of the TAT / DRAM cell, it is difficult to increase the physical distance.
On the other hand, in order to reduce the resistance of the gate electrode 18 of the TAT / DRAM cell, it is necessary to increase the cross-sectional area of the gate electrode 18, but in this case, the distance between the gate electrode 18 and the diffusion layer extraction electrode 22 is increased. Is reduced, and it becomes difficult to secure sufficient insulation between the diffusion layer extraction electrode 22 and the gate electrode 18.
In other words, in the TAT DRAM cell structure described above, there is a trade-off relationship between lowering the resistance of the gate electrode of the TAT DRAM cell and securing the breakdown voltage between the diffusion layer take-out electrode and the gate electrode.
[0022]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a TAT DRAM cell having a low-resistance gate electrode and ensuring a sufficient withstand voltage between the diffusion layer extraction electrode and the gate electrode, and a method for manufacturing the same. is there.
[0023]
[Means for Solving the Problems]
  A semiconductor device according to the present invention includes a groove formed in a semiconductor substrate, a gate electrode embedded in the groove via a gate insulating film, and a gate insulating film provided on the gate electrode along the inner wall of the groove And a sidewall made of a thick insulating film. The source / drain diffusion region formed in the region excluding the groove on the surface of the semiconductor substrate, and the semiconductor substrate, directly below the gate electrode through the gate insulating filmonlyAnd a channel diffusion layer formed on the substrate.The gate electrode is composed of a silicide layer provided in the region between the sidewalls at the upper part of the groove portion, and a conductive polysilicon layer provided between the groove wall of the groove portion and the silicide layer. Has been.
[0024]
The gate electrode of the TAT / DRAM cell of the semiconductor device according to the present invention includes an silicide layer provided in a region between the sidewalls and an upper portion of the groove portion, and a groove wall of the groove portion according to an etching mode described later. A conductive polysilicon layer provided between the silicide layer and the upper part of the groove portion, and a region extending between the side walls and under the lower end of the side walls. A distinction is made between a silicide layer provided and a conductive polysilicon layer provided between the groove wall of the groove portion and the silicide layer.
The gate oxide film is, for example, SiO₂Alternatively, it is made of SiON, and the side walls are made of SiN.
[0025]
The resistance of the gate electrode of the TAT DRAM cell is reduced by the self-aligned salicide technique for the conductive polysilicon layer in the trench.
The present invention prevents a breakdown voltage failure between the diffusion layer extraction electrode and the gate electrode by the thick sidewall, and by making the gate electrode a salicide structure, the gate electrode has a low resistance and suppresses signal delay, This enables high-speed operation of the DRAM. Further, it is possible to realize a TAT DRAM cell having a gate electrode structure in which the silicide layer and the diffusion layer are separated by a thick insulating film (side wall) and the area of the silicide formation is ensured widely. .
The present invention is applicable not only to Emb (Embeded) DRAM but also to general-purpose DRAM devices.
[0026]
  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove for forming a gate electrode in a field region of a semiconductor substrate, and ion implantation from an opening of the formed groove,onlyForming a channel diffusion layer. A step of oxidizing the surface of the semiconductor substrate to form a gate insulating film; a step of embedding a gate electrode layer in the trench to form a gate electrode; and a surface of the semiconductor substrate.onlyAnd forming a source / drain diffusion region by ion implantation. Further, the method includes a step of forming a sidewall made of an insulating film having a thickness larger than that of the gate insulating film on the inner wall of the groove on the gate electrode. In addition, the gate electrode is etched using an anisotropic etching method using the sidewall as a mask, and a U-shaped second groove is formed in the gate electrode, and a silicide layer is formed in the second groove. Process.
[0027]
In the hole forming step, an isotropic etching method may be applied instead of the anisotropic etching method.
The depth of the second groove is set to a depth optimized according to the resistance value of the gate electrode. In the method of the present invention, silicide can be formed on the gate electrode by a salicide technique using a sidewall as a mask.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings. It should be noted that the film formation method, the composition and thickness of the insulating layer, the conductive layer, etc., the process conditions, etc. shown in the following embodiment examples are merely examples for facilitating the understanding of the present invention. It is not limited to this illustration.
Embodiment 1 of Semiconductor Device
This embodiment is an example of an embodiment of a semiconductor device according to the present invention. FIG. 1 is a cross-sectional view showing a configuration of a TAT / DRAM cell portion of the semiconductor device of this embodiment, and FIG. -It is an enlarged view of the gate electrode of a DRAM cell.
As shown in FIG. 1, the transistor section 40 of the TAT / DRAM cell of the semiconductor device of the present embodiment has the same configuration as the transistor section 10 of the conventional TAT / DRAM cell described above except for the following. ing.
[0029]
The difference from the transistor part 10 is that
(1) The side wall 42 made of SiN thicker than the gate insulating film 16 is provided on the upper part of the groove wall of the groove 14. The thickness of the sidewall 42 is, for example, 20 nm to 30 nm when the thickness of the gate insulating film 16 is 10 nm.
(2) The gate electrode 44 is provided in the lower part of the groove 14 by embedding a groove part below the lower end of the sidewall 42.
(3) The gate electrode 44 is an upper portion of the groove portion and is provided in a silicide layer 44a provided in a region between the sidewalls 42, and a phosphorus-doped polycrystal provided between the groove wall of the groove portion and the silicide layer 44a. And the silicon layer 44b.
[0030]
In this embodiment, the gate electrode 44 has a large cross-sectional area and has a salicide structure, so that the resistance is low, and the upper portion of the groove wall of the groove 14 is made of SiN thicker than the thickness of the gate insulating film 16. By providing the side wall 42, it is possible to sufficiently ensure the withstand voltage between the diffusion layer extraction electrode 22 and the gate electrode 44.
[0031]
Embodiment 1 of Manufacturing Method of Semiconductor Device
This embodiment is an example of an embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to the manufacture of the transistor portion 40 of the TAT / DRAM cell of the semiconductor device described above. 3 (a) to 3 (c), FIG. 4 (d) to (f), FIG. 5 (g) to (i), and FIG. 6 show the transistors of the TAT DRAM cell by the method of this embodiment. FIG. 6 is a cross-sectional view for each process when the part 40 is manufactured.
In the method of this embodiment, first, as shown in FIG. 3A, an element isolation region 24 is formed on the Si substrate 12 by shallow trench isolation (STI), and CVD / SiO 2 is formed on the substrate surface.₂A film 32 is deposited.
Next, ions are implanted into the DRAM formation region to form a P well 26 in the lower layer portion of the Si substrate 12. If necessary, punch-through stop ion implantation is performed. At this stage, ion implantation for adjusting the substrate concentration of the transistor section 40, that is, channel doping is not yet performed.
[0032]
Next, CVD ・ SiO₂A photoresist film is formed on the film 32, and then a resist mask 46 having a pattern covering a region other than the word line is formed as shown in FIG.
Next, as shown in FIG. 3C, the resist mask 46 is used to form SiO.₂The film 32 is etched, and then the Si substrate 12 is continuously etched to form the groove 14 having a groove depth of about 100 to 150 nm in the Si substrate 12 in the field region.
Note that, as shown in FIG. 3C, it is desirable that the groove 14 has a rounded bottom and a round shape in order to prevent electric field concentration of the transistor. Further, since the width of the groove 14 becomes the channel length of the transistor, it is desirable to process the groove 14 as vertically as possible.
[0033]
The resist mask 46 is removed, and a sacrificial oxide film 47 having a thickness of 10 nm to 20 nm is formed as shown in FIG.
Next, ion implantation is performed to form a channel diffusion layer 28 of the transistor portion 40 under the trench 14 as shown in FIG. As the channel diffusion layer 28 of the transistor unit 40, the region to be highly concentrated is a substrate region below the trench 14, and the substrate on the side of the trench 14 and the upper layer portion of the Si substrate 12 is mostly a substrate. It is not necessary to perform ion implantation for adjusting the concentration.
CVD / SiO₂Since the film 32 serves as a stopper for ion implantation, effective ion implantation is possible only in the substrate region below the groove 14 without a mask. Further, since the ion implantation is not performed on the upper layer portion of the substrate, it is possible to form a very low concentration region.
[0034]
Next, as shown in FIG. 4E, the sacrificial oxide film 47 is removed and SiO 2 is removed.₂Alternatively, a gate oxide film 16 made of SiON is formed, and a phosphorus-doped polysilicon layer 48 is deposited on the entire surface of the gate oxide film 16.
Next, the phosphorus-doped polysilicon layer 48 is etched back to form a gate electrode (word line) 49 made of a phosphorus-doped polysilicon layer in the trench 14 as shown in FIG.
When performing the etch back, etch back is performed so that the upper surface of the gate electrode 49 in the trench 14 is located about 50 to 100 nm below the surface of the Si substrate 12, and between the diffusion layer extraction electrode 22 to be formed later. The distance for maintaining the withstand voltage is secured.
In the present embodiment, the transistor unit 40 is an Nch transistor and uses a polysilicon layer only for the word line of the DRAM unit.⁺Phosphorous doped polysilicon, which is a gate material, can be applied. Further, the film thickness of the gate electrode 49 is about 50 to 150 nm, and a film thickness optimized only for forming the “groove” -like word line can be set.
[0035]
Next, as shown in FIG. 5G, phosphorus ions are implanted to form a diffusion layer 20 in the source / drain region. The ion implantation is performed with the sharpest possible profile only on the diffusion layer 20.
In ion implantation, CVD and SiO provided in advance₂Since it suffices to penetrate the film 32, it is performed with an implantation energy of 20 to 50 KeV, and 1 × 10¹⁸~ 3x10¹⁸cm^-3Make the concentration to the extent. The Si substrate region under the diffusion layer 20 is a region where ions are hardly implanted and is 1 × 10 6.¹⁶~ 5x10¹⁷cm^-3The concentration can be very thin. Thereby, the np junction between the diffusion layer 20 and the region of the Si substrate 12 becomes a super graded junction.
[0036]
Subsequently, as shown in FIG. 5H, a SiN layer is formed on the entire surface of the substrate, and then etched, so that the sidewall 42 made of SiN thicker than the gate insulating film 16 is formed above the gate electrode 49. Formed in the groove wall. The thickness of the sidewall 42 is, for example, 20 nm to 30 nm when the thickness of the gate insulating film 16 is 10 nm.
Next, using the sidewalls 42 as a mask, the gate electrode 49 exposed from between the sidewalls 42 is etched by anisotropic etching such as a plasma etching method, and as shown in FIGS. A second groove 50 having a U-shaped groove wall is formed in the gate electrode 49.
The remaining gate electrode 49 formed with the second trench 50 becomes a gate electrode portion 44b made of phosphorus-doped polysilicon. FIG. 7 is an enlarged view around the second groove 50.
[0037]
Next, as shown in FIG. 6, a silicide layer 44 a is formed in the second groove 50 so as to fill the second groove 50 by a salicide technique using the sidewall 42 as a mask. After the silicide layer 44a is formed, the SiN cap layer 36 is deposited.
As a result, the salicide-structured gate electrode 44 composed of the silicide layer 44a and the phosphorus-doped polysilicon layer 44b can be formed in the trench 14. FIG. 8 is an enlarged view of the gate electrode 44.
The SiN cap layer 36 is effective in suppressing junction leakage in the silicide formation portion, and serves as an etching stopper when opening the connection hole 47 for forming the diffusion layer extraction electrode 22.
[0038]
Next, although not shown, a first interlayer insulating film 38 is deposited, planarized using a planarization technique such as CMP, and the diffusion layer reaching the diffusion layer 20 through the first interlayer insulating film 38 is extracted. The electrode 22 is formed.
Through the above steps, the transistor portion 40 of the TAT DRAM cell having a structure in which the resistance of the gate electrode 44 is low and the insulation distance between the diffusion layer extraction electrode 22 and the gate electrode 44 is sufficiently secured can be manufactured. it can.
[0039]
Embodiment 2 of Semiconductor Device
This embodiment is another example of the embodiment of the semiconductor device according to the present invention. FIG. 9 is an enlarged view of a gate electrode of a TAT / DRAM cell provided in the semiconductor device of this embodiment.
As shown in FIG. 1, the transistor portion of the TAT / DRAM cell of the semiconductor device of this embodiment has the same configuration as the transistor portion 40 of the TAT / DRAM cell of Embodiment 1 except for the following. ing.
As shown in FIG. 9, the transistor portion 40 is different from the transistor portion 40 in that the gate electrode 60 extends not only to the region between the sidewalls 42 but also to the region that has entered under the lower end portion of the sidewall 42. 60a, and a phosphorus-doped polysilicon layer 60b provided between the groove wall of the groove 14 and the silicide layer 60a.
The semiconductor device according to the present embodiment can achieve the same effects as the semiconductor device according to the first embodiment.
[0040]
Second Embodiment of Manufacturing Method of Semiconductor Device
This embodiment is an example of an embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to the manufacture of a transistor portion of a TAT / DRAM cell of the semiconductor device of Embodiment 2. FIGS. 10A and 10B are cross-sectional views of an etching process and a salicide process when a transistor portion of a TAT / DRAM cell is manufactured by the method of this embodiment, respectively.
In the present embodiment example, the groove 14 is formed in the Si substrate 12, and then ion implantation is performed to form the channel diffusion layer 28 under the groove 14, and then the entire surface of the substrate is formed as in the first embodiment example. A gate oxide film 16 is formed, a gate electrode layer 48 is deposited on the entire surface of the gate oxide film 16, and then the gate electrode layer 48 is etched back to form a gate electrode 49 in the trench 14.
Next, as shown in FIG. 5H, a SiN layer is formed on the entire surface of the substrate, and then etched, so that the sidewall 42 made of SiN thicker than the gate insulating film 16 is formed above the gate electrode 49. Formed in the groove wall.
[0041]
Next, in this embodiment, the gate electrode 49 exposed from between the sidewalls 42 is etched by isotropic etching such as a wet etching method, and as shown in FIG. A second groove 62 having a hemispherical groove wall is formed. The remaining gate electrode 49 formed with the second trench 62 becomes a gate electrode portion 60b made of phosphorus-doped polysilicon.
Next, as shown in FIG. 10B, a silicide layer 60a is formed in the second groove 62 so as to fill the second groove 62 by the salicide technique. Thereby, the gate electrode 60 having a salicide structure including the silicide layer 60a and the phosphorus-doped polysilicon layer 60b can be formed in the trench 14. Next, a SiN cap layer 36 is deposited on the entire surface.
Hereinafter, the gate shown in FIG. 9 has a shape in which the silicide layer and the semiconductor substrate are separated by a thick insulating film through the same steps as in the first embodiment, and the area of the silicide formation portion is ensured widely. A semiconductor device having an electrode can be manufactured.
[0042]
【The invention's effect】
According to the present invention, a sidewall made of an insulating film thicker than the thickness of the gate insulating film is provided on the upper portion of the groove wall of the groove, and the groove portion below the groove and below the sidewall is buried. By providing the gate electrode, the withstand voltage between the gate electrode (word line) and the diffusion layer extraction electrode can be increased, and the misalignment margin in the process of forming the diffusion layer extraction electrode can be increased. Furthermore, the sidewall thickness can be easily controlled by increasing the thickness of the sidewall.
Further, by forming a second groove in the gate electrode and providing a silicide layer having a large cross-sectional area constituting the salicide structure, the resistance of the gate electrode can be reduced and signal delay can be prevented.
The method of the present invention realizes an optimum method for manufacturing a semiconductor device according to the present invention.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a TAT / DRAM cell portion of a semiconductor device according to Embodiment 1;
2 is an enlarged view of a gate electrode of a TAT DRAM cell of the semiconductor device of Embodiment 1; FIG.
FIGS. 3A to 3C are cross-sectional views for each process when a transistor portion of a TAT DRAM cell is manufactured by the method of Embodiment 1. FIG.
4 (d) to 4 (f) are cross-sectional views for each step when manufacturing a transistor portion of a TAT / DRAM cell by the method of Embodiment 1 following FIG. 3 (c), respectively. It is.
5 (g) to 5 (i) are cross-sectional views for each step when manufacturing a transistor portion of a TAT / DRAM cell by the method of Embodiment 1 following FIG. 4 (f). It is.
FIG. 6 is a cross-sectional view for each step of manufacturing the transistor portion of the TAT • DRAM cell by the method of Embodiment 1 following FIG.
FIG. 7 is an enlarged view around the second groove.
FIG. 8 is an enlarged view of a gate electrode.
9 is an enlarged view of a gate electrode of a TAT DRAM cell provided in the semiconductor device of Embodiment 2. FIG.
FIGS. 10A and 10B are cross-sectional views of an etching process and a salicide process in manufacturing a transistor portion of a TAT DRAM cell by the method of Embodiment 2, respectively.
FIG. 11 is a cross-sectional view showing a configuration of a transistor portion of a TAT DRAM cell.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Transistor part of TAT DRAM cell, 12 ... Si substrate, 14 ... Groove, 16 ... Gate insulating film, 18 ... Gate electrode, 18a ... Silicide, 20 ... Diffusion layer, 22 ... Diffusion Layer extraction electrode, 24... Element isolation region, 26... P well, 28... Channel diffusion layer, 32.₂Membrane 34 …… SiO₂36... SiN cap layer 38... First interlayer insulating film 40. TAT DRAM cell transistor portion of semiconductor device of embodiment, 42 .. Side wall 44... Gate electrode 44 a ...... Silicide layer, 44b ... Phosphorus doped polysilicon layer, 46 ... Resist mask, 47 ... Sacrificial oxide film, 48 ... Phosphorus doped polysilicon layer, 49 ... Gate electrode, 50 ... Second groove, 60... Gate electrode, 60a... Silicide layer, 60b... Phosphorus doped polysilicon layer

Claims (5)

A groove formed in a semiconductor substrate;
A gate electrode embedded in the trench through a gate insulating film;
A sidewall made of an insulating film thicker than the gate insulating film provided on the gate electrode along the groove inner wall;
A source / drain diffusion region formed in a region excluding the groove on the surface of the semiconductor substrate;
A channel diffusion layer formed only directly under the gate electrode through the gate insulating film in the semiconductor substrate ,
The gate electrode is an upper part of the groove part, and a silicide layer provided in a region between the sidewalls, and a conductive polysilicon layer provided between the groove wall of the groove part and the silicide layer And a semiconductor device.   The gate electrode is an upper portion of the groove portion, and a silicide layer provided over a region between the sidewalls and a region that extends under a lower end portion of the sidewalls; a groove wall of the groove portion; 2. The semiconductor device according to claim 1, comprising a conductive polysilicon layer provided between the silicide layer. The semiconductor device according to claim 1, wherein the gate insulating film is formed of SiO ₂ or SiON, and the sidewall is formed of SiN. Forming a groove for forming a gate electrode in a field region of a semiconductor substrate;
A step of ion-implanting from the opening of the groove formed to form a channel diffusion layer only under the groove;
Oxidizing the surface of the semiconductor substrate to form a gate insulating film;
Embedding a gate electrode layer in the trench to form a gate electrode;
Forming source / drain diffusion regions by ion implantation only on the surface of the semiconductor substrate;
Forming a sidewall made of an insulating film thicker than the gate insulating film on the inner wall of the groove on the gate electrode;
Using the sidewall as a mask, etching the gate electrode using an anisotropic etching method, and forming a U-shaped second groove in the gate electrode;
Forming a silicide layer in the second groove. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 4 , wherein an isotropic etching method is applied instead of the anisotropic etching method in the step of forming the second groove.

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