JPH1164450A - Semiconductor-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily diagnose a GO/NO-GO of a tester bus via a plurality of units by latching address data on an AD bus that returns to the reception terminal of a bus controller using a data latch register. SOLUTION: First, a selector 34 sets a mode-switching register 36 in advance so that a signal at the side of an OR gate 32 can be outputted. Address data and a write control signal are outputted at the same clock timing from the transmission of a bus controller onto an ADO bus. Therefore, a write control signal received at the reception terminal side of the bus controller is supplied to a data latch register 62 via an OR gate 32 and a selector 34. As a result, the address data on the ADO bus at the reception terminal side are latched. A GO/NO-GO can be judged by allowing a CPU to read the data. If the data is not matched with the value of an address register 52 that is a transmission terminal side, it can be easily judged that some sort of transmission failure has occurred at the AND transmission line of a tester bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pass / fail diagnosis of a transmission bus line passing through a plurality of units in a bus interface of a semiconductor test apparatus.

[0002]

2. Description of the Related Art A prior art example will be described below with reference to a bus interface configuration example of FIG. 3 and a write / read timing diagram of FIG. The bus interface of the semiconductor test device is called a tester bus, and has a connection configuration in which a large number of units Ui (here, i = 1 to n) are sequentially connected in series by a bus cable of several meters as shown in FIG. This tester bus transfer is a handshake transfer by a control signal for both writing and reading in order to support units operating at high speed to low speed.

For this reason, the dedicated bus controller 50 controls the writing / reading of the tester bus. As shown in FIG. 3, the principle configuration of the bus controller 50 according to the present invention includes an address register 52 and a data register 5.
4, the multiplexer 56, and the bus drivers 72 and 74
, Bus receivers 82 and 84, a data latch register 62, a status latch register 64, and a timer 68.

On the other hand, the signal lines of the tester bus are AD
A bus, a clock, a write control signal WT, a read control signal RD, a data strobe signal DTSTRB,
A write response signal WTACK and others. The AD bus is composed of 32 signal lines.
Bit write / read data is transmitted in a time-division manner. The bus controller 50 switches the contents of the address register 52 and the data register 54 by the multiplexer 56 and
Time-division output to the D bus. The contents of the address register 52 and the data register 54 can be read and confirmed from the CPU via the internal bus 90.

[0005] A handshake operation at the time of writing will be described. As shown in FIG. 4A, a write control signal WTO is output from the sending end of the bus controller 50, address data Ax is output from the address register 52 on the ADO bus at this clock timing, and data is output in the next clock cycle. The write data Dx is output from the register 54.
On the other hand, the unit Ui corresponding to the address data Ax, after recognizing the address and receiving the write data Dx, sends out a write response signal WTACK onto the bus. On the bus controller 50 side, the write response signal WTA
After receiving the CK at the receiving end, the CPU notifies the CPU of the write end and ends the write cycle. Note that the timer 68 is for monitoring the timeout time, and starts counting the clock time at the start of writing. First, when the write response signal WTACK is received before the elapse of the predetermined count time, the process ends normally, and secondly, when the count value exceeds the predetermined count time, an error flag is notified to the CPU as a timeout. Here, the absence of the write response signal WTACK means that
It is detected whether the unit Ui at the corresponding address is malfunctioning, the address space is unused in the unit Ui, or the tester bus system is defective.

Next, a handshake operation at the time of reading will be described. As shown in FIG. 4B, the bus controller 50
The read control signal RDO is output from the sending end of the address register A, and the address data Ax from the address register 52 is output to the ADO bus at this clock timing. On the other hand, the unit Ui corresponding to the address data Ax recognizes this address and reads the read data Dx and the data strobe signal DTSTR.
B in the same clock cycle. On the bus controller 50 side, the data strobe signal DTSTRB
Is received, the read data Dx on the AD bus is latched in the data latch register 62, and the read cycle is completed. Thereafter, the CPU reads the contents of the data latch register 62 via the internal bus 90. Note that the timeout period is monitored by the timer 68 in the same manner as at the time of writing. In this case, data strobe signal DTSTR
It monitors whether B has been received.

Note that the status latch register 64
At the receiving end of the tester bus, various control signals, ie, WT
This flip-flop latches whether or not I, RDI, WTACKI, DTSTRBI, etc. have been detected at the receiving end. By reading this status by the CPU, it is possible to monitor whether various control signals are operating normally. I have. The circuit of the bus controller 50 operates in synchronization with the clock.

[0008]

By the way, when the above-mentioned tester bus is normally connected and the address data Ax corresponding to the unit Ui is transmitted, there is no response from the corresponding unit Ui and a time-out occurs. May be. As described above, each unit Ui recognizes whether or not it is in its own address space and sends out a response signal. Therefore, in order to identify a defect, it is necessary to first check whether normal address data is supplied to the corresponding unit Ui. For this purpose, the AD bus line immediately before or immediately after the relevant unit Ui is directly connected to the logic analyzer. Or an oscilloscope for monitor inspection. This inspection method has a practical difficulty because the inspection takes time.
Therefore, an object of the present invention is to provide a semiconductor test apparatus that easily realizes a good / bad diagnosis of a tester bus passing through a plurality of units.

[0009]

In order to solve the above-mentioned problems, according to the configuration of the present invention, a bus signal transmitted in one direction is output from a transmitting end of a bus controller 50, and a bus signal is transmitted between a plurality of units Ui. In a semiconductor test apparatus which is a transmission bus that is received by a receiving end of the controller 50 and has a transmission bus configuration for outputting time-division address data Ax and write data Dx from an AD bus line of the bus controller 50, The receiving end of the bus controller 50 receives the time-division address data Ax output from the end and passing through the plurality of units Ui at the receiving end of the bus controller 50. First, at the time of the writing operation, the write control signal WTI received at the receiving end of the bus controller 50 is received. Latches the address data Ax, and at the second time, in the read operation, the read control signal RD received at the receiving end of the bus controller 50. Address data A by
It is a configuration means provided with a means for latching x. As described above, the coincidence / mismatch between the address signals Ax on the transmitting end and the receiving end can be determined, and a semiconductor test apparatus can be realized which easily realizes the quality of transmission bus lines passing through a plurality of units.

FIG. 1 shows address signal latch means. As a means for latching the address data Ax, the write control signal WTI and the read control signal RDI are
A means for adding R (for example, an OR gate 32);
A mode switching register 36 is provided to enable the CPU to control the selection of the input 1 output switching means. Upon receiving a switching signal from the mode switching register 36, the output signal of the OR adding means or the data at the receiving end is received. A means (selector 34) for selecting and outputting any one of the strobe signals DTSTRBI is provided. Upon receiving an output signal from the selection output means, a time-division address data Ax or a time-division data on the AD bus on the receiving end side is received. There is a configuration unit including a unit (data latch register 62) for latching any one of the read data Dx. In this case, the circuit configuration is used for both address signal latching and data signal latching.
U can be selected and latched by setting control from U.

FIG. 2 shows another means for latching the address signal. As a means for latching the address data, the write control signal WTI and the read control signal RDI are
An OR gate 32 for adding R;
There is a configuration means which includes an address latch register 63 which receives the output signal of No. 2 and exclusively latches the time-division address signal Ax on the AD bus at the receiving end. In this case, the address data Ax on the AD bus can be latched simultaneously with the latching of the read data Dx according to the conventional configuration.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

The present invention will be described below with reference to the bus interface configuration diagram of FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals. In the present invention, the address latch Ax on the AD bus returned to the receiving end of the bus controller 50 is also used as the data latch register 62 as a data latch.
A configuration is provided in which means for latching by the latch register 62 is added.

The configuration of the present invention is different from the conventional configuration in that the OR gate 32, the selector 34, and the mode switching register 36
Is added. The OR gate 32 OR-adds the write control signal WTI and the read control signal RDI and supplies the result to one end of the selector 34. The selector 34 selects either the output signal from the OR gate 32 or the data strobe signal DTSTRBI and supplies it to the data latch register 62 as a latch control signal. The mode switching register 36 is a 1-bit operation mode switching register that can be set from the CPU side, and supplies its output to a selection control input terminal of the selector 34.

The data latch register 62 normally stores the read data D on the AD bus during a read operation.
The register x is used for latching the address data Ax on the AD bus.

The operation of latching the address data Ax on the AD bus will be described. First, the selector 34 sets the mode switching register 36 in advance so as to output the signal on the OR gate 32 side. First, the latch operation of the address data Ax at the time of writing will be described. Address data Ax is sent from the sending end of the bus controller 50 onto the ADO bus.
And the write control signal WTO are output at the same clock timing as shown in FIG. Therefore, the write control signal WTI received on the receiving end side of the bus controller 50 is ORed.
The data is supplied to the data latch register 62 via the gate 32 and the selector 34. As a result, the address data Ax on the ADO bus on the receiving end is latched. The quality can be determined by reading this from the CPU. If the value does not match the value of the address register 52 on the sending end side, it can be easily determined that there is some transmission failure in the AD bus transmission line of the tester bus.

Second, the address data A at the time of reading is
The latch operation of x will be described. The address data Ax and the read control signal RDO are output from the sending end of the bus controller 50 onto the ADO bus at the same clock timing as shown in FIG. Then, in the same manner as at the time of writing, the address data Ax on the ADO bus on the receiving end is latched by the read control signal RDI received on the receiving end. Similarly, in the case of a mismatch, the tester bus AD
It is possible to easily determine that there is some transmission failure in the bus transmission path.

According to the above-mentioned invention, since the data latch A is provided with means for latching the address data Ax on the AD bus returned to the receiving end of the bus controller 50 in the data latch register 62, the AD bus transmission Since the quality of the transmission of the address data Ax on the path can be easily detected, there is an advantage that a defect relating to the address data Ax can be easily specified.

In the above description of the embodiment, a specific example in which the data latch register 62 is diverted to latch the address data Ax on the AD bus has been described. However, as shown in FIG. Address latch register 6
3 may be provided and individually latched. In this case, the advantage is obtained that the address data Ax and the read data Dx on the AD bus can be latched at the same time, and the advantage that the failure of the AD bus transmission path can be more easily specified.

[0020]

According to the present invention, the following effects can be obtained from the above description. According to the configuration of the above-described invention, a configuration is provided in which the address data Ax on the AD bus returned to the receiving end of the bus controller 50 is latched in the data latch register. Since the quality of the transmission of Ax can be easily detected from the CPU, there is obtained an advantage that a defect relating to the address data Ax can be easily specified.

[Brief description of the drawings]

FIG. 1 is an example of a bus interface configuration according to the present invention.

FIG. 2 is another bus interface configuration example of the present invention.

FIG. 3 is an example of a conventional bus interface configuration.

FIG. 4 is a write / read timing diagram of a tester bus.

[Explanation of symbols]

 32 OR gate 34 Selector 36 Mode switch register 50 Bus controller 52 Address register 54 Data register 56 Multiplexer 62 Data latch register 63 Address latch register 64 Status latch register 68 Timer 72, 74 Bus driver 82, 84 Bus receiver 90 Internal bus

Claims (3)

[Claims] 1. A semiconductor test apparatus having a transmission bus form for outputting time-division address data and write data from a sending end of a bus controller, when a signal is output from a sending end of the bus controller and passes through a plurality of units. Divided address data is received at the receiving end of the bus controller. First, the address data is latched by a write control signal received at the receiving end of the bus controller during a write operation, and secondly, during a read operation. Means for latching the address data in response to a read control signal received by a receiving end of the bus controller; and a semiconductor test apparatus comprising: 2. An address data latching means, a means for ORing a write control signal and a read control signal, a mode switching register for controlling selection of a two-input, one-output switching means, and switching from the mode switching register. Upon receiving the signal, the OR
Means for selecting and outputting either the output signal of the adding means or the data strobe signal on the receiving end side, and receiving the output signal from the selected output means and receiving a time-division address on the AD bus at the receiving end side 2. The semiconductor test apparatus according to claim 1, further comprising: means for latching either data or time-division read data. 3. An address data latching means, comprising: means for OR-adding a write control signal and a read control signal;
2. A semiconductor test apparatus according to claim 1, further comprising: means for latching a time division address signal on the D bus.