JPH11220124A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make threshold voltage equal to other elements around it, and to obtain a load element and a lagging element having a little leakage current by a method wherein a plurality of gate electrodes are electrically connected to a gate insulating film, and the gate electrodes are arranged along the gate insulating film separately with each other. SOLUTION: A rectangular gate insulating film 4 is formed on a P-type semiconductor substrate 1, and a plurality of gate electrodes 6a, 6b and 6c are formed on the gate insulating film 4. As the length of each channel region is determined by each gate electrode 6 even when the channel length is made longer by increasing the number of the gate electrodes, their threshold voltage Vt is constant even when the gate electrode 6 is formed in an optional number, and the threshold voltage of the gate electrode is equal to that of other plurality of MOS transistors located in the circuit. That is, the semiconductor element is substantially functions as the MOS transistors having a long channel length, and the channel length can be adjusted by the number of the gate electrodes 6, and they function as an individual transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a high-resistance MOS transistor element used as a load element or a delay element of a delay circuit.

[0002]

2. Description of the Related Art With the recent progress in miniaturization of semiconductor integrated circuit structures, 0.25 μm design rules have recently been put to practical use. The design rule here refers to the minimum line width that can be processed in a semiconductor integrated circuit, and generally,
The channel length (Gate Length) of the transistor is used as the measure. Therefore, the 0.25 μm design rule means that the minimum channel length of a transistor in a semiconductor integrated circuit is
It means 0.25 μm. By shortening the channel length of the MOS transistor, not only the size of the circuit can be reduced, but also the speed of the element can be increased by reducing the resistance of the channel, and the power supply voltage can be reduced.

However, various elements are incorporated in a semiconductor integrated circuit, including a load element for adjusting a voltage drop in the circuit, a delay circuit for adjusting the operation timing of the entire circuit, and the like. May be included. The load element needs to have a high resistance value, and a MOS transistor having a long channel length is generally used in a semiconductor integrated circuit. This is based on the fact that the electrical resistance of the channel when a voltage is applied to the gate electrode and the channel is conductive is larger than that of the surrounding impurity diffusion region. Call. The resistance of the load MOS can be adjusted by adjusting the channel length. The longer the channel length, the higher the resistance. Since the load MOS is a MOS transistor, it can be formed easily and simultaneously with other semiconductor devices when manufacturing a semiconductor integrated circuit, and the use / non-use of a resistor can be controlled by ON / OFF of a gate electrode. Etc. The delay circuit is an MO with a long channel length.
It is configured by combining an S transistor and a capacitor. Like the load MOS, the resistance value of the MOS transistor can be increased by increasing the channel length, so that the delay time can be adjusted, and the use and non-use can be controlled by turning on / off the gate electrode. FIG. 6 shows a conventional MOS transistor having a long channel length.

[0004]

Conventionally, the channel length
When GL is shortened, the threshold voltage (V
t) is reduced, a phenomenon called the so-called short channel effect is known. However, when the concentration of the impurity added to the substrate becomes high or when the punch-through stopper 55 having a high impurity concentration is formed as in the conventional MOS transistor shown in FIG. It has become clear that a so-called inverse short channel effect, which decreases, occurs.

FIG. 4 shows the change in Vt with respect to the channel length when the inverse short channel effect occurs. The current Ids flowing through the MOS transistor is the transistor width GW and channel length G
It is a function of L, the voltage Vgs between the gate and the source, the threshold voltage Vt, and the voltage Vds between the source and the drain, and has a relationship of Ids∝GW · (Vgs−Vt) / GL. Therefore, it can be seen that the resistance of the MOS transistor can be increased, in other words, the GL can be increased to reduce Ids. However, since the reverse short channel effect occurs, increasing GL decreases Vt,
The effect is offset.

In general, even when the voltage of a gate electrode is lower than Vt, a MOS transistor generally has a gate voltage region in which a base immediately below a gate is weakly inverted, and a voltage is applied between a source and a drain. By doing
A so-called weak inversion current is generated. The gate voltage Vgs and the current I flowing between the drain and the source in such a weak inversion region
FIG. 5 shows the relationship with ds. As can be seen from the figure, when the channel length increases and the threshold voltage decreases, the current value does not become 0 A even when Vgs is 0 V, and a so-called leak current flows.

The load MOSs and delay elements described above are rarely incorporated into a single chip in a large number. Most MOS transistors in the chip have short channel lengths, and the threshold voltage is set by using elements having short channel lengths as standard. Is set as At this time, for the above-described reason, Vt of the transistor having a long channel length decreases, and the leak current cannot be ignored.

[0008] If the miniaturization of the circuit further advances in the future, it is expected that the above-mentioned problems will become more apparent, and a solution is required.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a transistor having a long channel length is not constituted by a single transistor, but a diffusion layer is inserted in the middle of a channel. The gate electrode is divided into a plurality of gate electrodes to obtain an effective long channel length. Each channel separated by a diffusion layer is an inverse short channel, effectively acting as one transistor having a short channel length, and each gate electrode forming each channel is the same as another short channel transistor in an integrated circuit. As such, the threshold voltage of the gate is also equal to other transistors in the integrated circuit.

According to a first aspect of the present invention, there is provided a semiconductor substrate of a first conductivity type, a gate insulating film formed in a strip shape on the semiconductor substrate, and a gate insulating film formed on the semiconductor substrate around the gate insulating film. And a plurality of gate electrodes that are electrically connected to each other on the gate insulating film, and are disposed apart from each other along the gate insulating film. A second conductivity type source region and a drain region formed on the surface of the semiconductor substrate outside gate electrodes disposed at both ends, and a second region formed on the surface of the semiconductor substrate between the plurality of gate electrodes; This is a semiconductor device including a conductive diffusion region.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the plurality of gate electrodes are electrically connected to each other by a connecting portion provided integrally with the plurality of gate electrodes. The semiconductor device is characterized by being performed via a semiconductor device. According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the connection portion is formed on the element isolation film along at least a part of the gate insulating film. It is a semiconductor device.

[Detailed Description of the Invention]

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below. FIG. 1A is a plan view of the semiconductor device of the present embodiment, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. A rectangular gate insulating film 4 is formed on a p-type semiconductor substrate 1, and a plurality of gate electrodes 6a, 6b, 6c are formed on the gate insulating film 4. An n-type source region 9 and a drain region 10 are formed on the semiconductor substrate 1 outside the gate electrodes 6a and 6c at both ends, and a source electrode and a drain electrode are extracted from each region. N on the semiconductor substrate 1 between the individual gate electrodes
A mold diffusion region 11 is formed. A punch-through stopper 7 for preventing a short channel effect is formed at the end of the source region 9 and the drain region 10 and at both ends of the diffusion region 11. Outside the gate insulating film 4, an element isolation film 3 of a LOCOS oxide film is formed. The individual gate electrodes are formed on the element isolation film 3 by the respective gate electrodes 6a, 6b, 6c.
Are electrically connected via a connecting portion 6d formed integrally with the second member.

In the following, each gate electrode 6a, 6b, 6
c and the connection portion 6d are integrally formed, and are generally referred to as a gate electrode 6. Each gate electrode 6a, 6b, 6c not including the connection portion 6d is abbreviated as each gate electrode 6. In this embodiment, three gate electrodes 6 are shown as an example, but two or more gate electrodes may be formed according to a required channel length.
In this case, a diffusion region 11 is formed between each gate electrode 6.

Next, the operation of this embodiment will be described. When a gate voltage Vg larger than Vt is applied to the gate electrode 6, an inversion layer is generated on the surface of the semiconductor substrate 1 immediately below each gate electrode 6,
A channel region is formed and becomes conductive. Each gate electrode 6
Since the diffusion region 11 is formed between the source and drain regions, the source region 9 and the drain region 10 become conductive by application of the gate voltage Vg. That is, it can be said that the basic operation of this embodiment is almost the same as that of the conventional MOS transistor. Here, when the respective channel lengths are equal (the channel length at this time is often equal to the channel length of the other elements in the circuit), the resistance of each channel is equal. The resistance value R of the entire device is expressed as R = n · r since the resistance of the diffusion region is sufficiently higher than the channel resistance and can be ignored. n is the number of gate electrodes, and n = 3 in FIG. Therefore, by increasing the number n of the gate electrodes, the resistance value of the element can be increased in units of r. In the delay circuit, the delay time can be increased by increasing the number of gate electrodes.

On the other hand, even if the channel length is increased by increasing the number of gate electrodes, the length of each channel region is determined by each gate electrode. It is constant and equal to many other MOS transistors present in the circuit. In other words, in other words, from the viewpoint of operation in a circuit, the semiconductor element of the present invention behaves as a MOS transistor having a substantially long channel length, and the channel length can be adjusted by the number of gate electrodes, and the threshold voltage From the viewpoint of, it can be said that the transistor behaves as an individual transistor.

The manufacturing method according to the present embodiment will be described below with reference to FIG. 2 based on, for example, a 0.5 μm design rule. Step 1: As shown in FIG. 2A, a pad oxide film 2 is formed on a p-type semiconductor substrate 1 to a thickness of 250 ° by using a thermal oxidation method. The pad oxide film 2 is a silicon oxide film formed for the purpose of protecting the semiconductor substrate 1. Next, a silicon nitride film as an oxidation-resistant film (not shown) is formed, and an opening is formed in a region where an element is to be formed. Next, LOCOS (Local Oxidation Of
Using the silicon nitride film as a mask, the semiconductor substrate 1 is oxidized using a silicon (Si) method to form an element isolation film 3 having a thickness of 3000.degree., And the silicon nitride film is removed. Step 2: As shown in FIG. 2 (b), the pad oxide film 2 is removed, and a thermal oxidation method or a CVD (Chemical Vapor Depositi) method is used.
On) method, a gate insulating film 4 is formed to a thickness of 100 °. Next, a polysilicon film is formed to a thickness of 2000 Å using a CVD method, and a p-type impurity such as P is ion-implanted over the entire surface to form a conductive film 5. Step 3: As shown in FIG. 2C, a predetermined region of the conductive film 5 is etched to form a gate electrode 6. At this time, the channel length GL of each gate electrode 6 is 0.5 μm. The area for forming the diffusion area 11 is 0.5 μm. Next, a p-type impurity is implanted with high energy using the gate electrode 6 as a mask to form a punch-through stopper 7. Step 4: As shown in FIG.
An insulating film made of O2 is formed, and the entire surface is etched back to form a sidewall 8. Step 5: As shown in FIG. 1B, an n-type impurity is ion-implanted using the gate electrode 6 and the sidewall 8 as a mask to form a source region 9, a drain region 10, and a diffusion region 11. Next, an annealing process is performed to activate the impurities implanted into each layer. Next, the entire surface is covered with an interlayer insulating film (not shown), a predetermined region is opened, a contact hole is formed, and source and drain electrodes are formed. As described above, the semiconductor device of the present embodiment is formed. The semiconductor device of the present invention is incorporated as needed in forming a semiconductor integrated circuit, and can be formed at the same time as forming many other elements in the circuit by forming as described above.

Hereinafter, a second embodiment of the present invention will be described. FIG. 3A is a plan view of the semiconductor device of the second embodiment, and a cross-sectional view taken along line AA of this embodiment is the same as FIG. 1B. In the present embodiment, each gate electrode of the gate electrode 6 is provided on the element isolation film 3.
The third embodiment differs from the first embodiment in that they are connected by two connection portions 6d. The shape of the gate electrode 6 of the present embodiment can also be described as an opening provided in a part of the rectangular gate electrode on the gate insulating film 4. The operation and manufacturing method of this embodiment are almost the same as those of the first embodiment.

Hereinafter, a third embodiment of the present invention will be described. FIG. 3B is a plan view of the semiconductor device according to the third embodiment. The present embodiment is an application example of the present invention in the case where the gate length is long, that is, the number of gate electrodes is increased. For example, the gate insulating film 4 is formed to be bent due to a circuit layout or the like. I have. Along with the bent gate insulating film 4, the connecting portion 6d of the gate electrode 6 is formed substantially parallel to the longitudinal direction of the gate insulating film 4, and is located at the center of the gate insulating film 4 bent in a U-shape. ing. Each gate electrode 6 extends on the gate insulating film 4 from the connecting portion 6d, and a diffusion region 11 is formed on the semiconductor substrate 1 between each gate electrode 6. The operation and manufacturing method of this embodiment are almost the same as those of the first embodiment.

The shape of the gate electrode 6 may be such that the connecting portion 6d is provided outside the gate insulating film 4, as shown in FIG. Further, two or more connection portions 6d may be provided. The operation and the manufacturing method of the semiconductor device according to the present embodiment do not greatly change depending on such a shape of the gate electrode 6. Also,
The bending of the gate insulating film 4 is not limited to the U-shape, but can be formed arbitrarily according to the L-shape, S-shape, or other circuit layout.

The embodiment described above is merely an example of the embodiment of the present invention, and may have any shape as long as a plurality of gate electrodes are electrically connected. For example, FIG.
As shown in (1), the connection portion 6d may be provided on each gate electrode. For example, the connection portion 6d may be connected to an individually formed gate electrode via a contact or directly by a metal wiring or the like. Good. However, these cases lead to an increase in the number of manufacturing steps.

In the above-described manufacturing process, the materials, thicknesses, and the like of the respective films are exemplified using the existing technology, and are not limited to them. That is, the material may be amorphous silicon instead of polysilicon, for example, or n-type or well instead of the p-type semiconductor substrate. In addition, although each film thickness has been described using the 0.5 μm design rule as an example, it is needless to say that the thickness is not limited to this and can be set arbitrarily.

In the embodiment described above, the channel length of each gate electrode is equal to that of the other transistors in the integrated circuit. However, the gate electrode may be formed as large as possible within a range in which a change in the threshold of the gate voltage can be ignored. By taking each gate electrode as large as possible, the number of gate electrodes can be reduced, so that the device can be miniaturized. In addition, the interval between the gate electrodes is preferably smaller from the viewpoint of miniaturization of the element, but is generally equal to the channel length because the channel length is the minimum size that can be processed.
The narrower is better.

[0024]

According to the first aspect of the present invention, a semiconductor device of the first conductivity type and a gate insulating film formed on the semiconductor substrate are electrically connected and separated from each other. A plurality of gate electrodes disposed; a second conductivity type source region and a drain region formed on the surface of the semiconductor substrate outside the gate electrodes disposed at both ends of the plurality of gate electrodes; And a second conductive type diffusion region formed on the surface of the semiconductor substrate between the gate electrodes of the semiconductor device, so that the semiconductor device behaves as a single transistor having a long channel length in a semiconductor integrated circuit. Since the channel length itself has the same channel length as other elements in the semiconductor integrated circuit, there is no difference from the other elements of the threshold voltage Vt due to the inverse short channel effect. Therefore, it is possible to obtain a load element and a delay element having a small leak current with Vt equal to other surrounding elements. Further, as shown in FIG. 2D, since the ion implantation is performed using the gate electrode 6 as a mask, the diffusion region 11 can be formed in a self-aligned manner.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the plurality of gate electrodes are electrically connected to each other by a connecting portion provided integrally with the plurality of gate electrodes. Since the semiconductor device is characterized in that the semiconductor device is manufactured through the steps described above, the same effects as those of the invention described in claim 1 can be obtained, and the semiconductor device can be manufactured in a smaller number of steps, and other components in the integrated circuit can be manufactured. It can be manufactured simultaneously with the device.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the connection portion is formed on the element isolation film along at least a part of the gate insulating film. A semiconductor device characterized by the fact that, even when the number of gate electrodes increases and the element region becomes longer, the element region is formed by bending and the connection part of the gate electrode is formed along a part of the bent element region. By forming the semiconductor device, the semiconductor device of the present invention can be formed with a minimum area.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram illustrating a relationship between a channel length and a threshold voltage when an inverse short channel effect occurs.

FIG. 5 is a diagram showing a relationship between a current between a source region and a drain region with respect to a voltage between a gate electrode and a source region.

FIG. 6 is a diagram showing a conventional MOS transistor having a long channel length.

Claims (3)

[Claims] A semiconductor substrate of a first conductivity type; a gate insulating film formed in a strip shape on the semiconductor substrate; an element isolation film formed on the semiconductor substrate around the gate insulating film; A plurality of gate electrodes electrically connected to each other on the gate insulating film and arranged apart from each other along the gate insulating film, and gate electrodes arranged at both ends of the plurality of gate electrodes A source region and a drain region of the second conductivity type formed on the surface of the semiconductor substrate outside the semiconductor device, and a diffusion region of the second conductivity type formed on the surface of the semiconductor substrate between the plurality of gate electrodes. Equipped semiconductor device. 2. The semiconductor device according to claim 1, wherein
The semiconductor device according to claim 1, wherein the plurality of gate electrodes are electrically connected to each other through a connection portion provided integrally with the plurality of gate electrodes. 3. The semiconductor device according to claim 2, wherein
The semiconductor device according to claim 1, wherein the connection portion is formed on the element isolation film along at least a part of the gate insulating film.