JPH088431A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide an SOI-MOSFET wherein channel contact is enabled without causing the increase of junction capacitance and contact resistance, and stable voltage-current characteristics free from kink are obtained. CONSTITUTION:A FET is formed in a silicon film on insulator. A transistor region 1 consists of a first region 1A and a second region 1B which are arranged in the gate width direction and a constricted part 1C which connects the regions 1A and 1B. A source region of a first conductivity type a channel region of a second or opposite conductivity type, and a drain region of the first conductivity type are formed in the first region 1A. A gate electrode 2 stretching as far as the constricted region 1C is formed on a channel region. A channel contact region composed of a diffused layer of the second conductivity type is formed in the second region 1B. As to the constricted region 1C, the width in the gate length direction is smaller than the width of the first region 1A, and a semiconductor device has a width greater than the gate length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a thin film SOI (Silicon On Insu-lator) type semiconductor device.

[0002]

2. Description of the Related Art Since thin-film SOI-MOS FETs are excellent in suppressing the short-channel effect, they are expected to be high-speed devices that can form shorter channels than bulk MOSFETs and have a small parasitic capacitance. However, because of the SOI structure, the channel region is in an electrically floating state and kinks appear in the current-voltage characteristics, which makes operation unstable.

In order to solve this problem, the channel region
It is known that a contact region is provided (here, the region between the source and drain of the silicon film) and fixed at a constant voltage. Conventionally, as a method of providing a contact region in the channel region, the transistor region (element forming region surrounded by the field insulating film) is simply extended in the gate electrode direction (gate width direction) to draw out the channel region.

A conventional channel contact is used for the constricted transistor region of the present invention shown in FIG.
It was provided in the transistor region without a waist.

[0005]

However, in this structure, the conductivity types of the source / drain region and the channel contact region are different, so that a large p ⁺ n is formed in the transistor.
⁺ Junction capacitance is created, which hinders high-speed operation of the transistor.

Further, since the channel contact region has not been silicidized conventionally, there is a problem that the resistance of the lead portion is large and the channel potential at a position apart from the contact cannot be sufficiently fixed.

An object of the present invention is to provide a SOI-MOS FET which enables a channel contact without an increase in junction capacitance and contact resistance and has stable characteristics without kinks.

[0008]

[Means for Solving the Problems] To solve the above problems, 1) a FET formed on a silicon film on an insulator is
First region 1A in which transistor region 1 is arranged in the gate width direction
And second area 1B and constricted area 1C connecting these areas
A source region of one conductivity type, a channel region of opposite conductivity type, and a drain region of one conductivity type are formed in the first region, and a gate electrode 2 extending to the constricted region 1C is formed on the channel region. A channel contact region formed of a diffusion layer of opposite conductivity type is formed in the second region 1B, and the constricted region 1C has a width in the gate length direction of the first region.
A semiconductor device having a width smaller than a width of 1A and having a width equal to or larger than a gate length, or 2) in manufacturing the semiconductor device described in the above 1, a mask 6 that covers the constricted region 1C and a part of the gate electrode 2 is formed, This is achieved by a method for manufacturing a semiconductor device, which includes a step of etching the surfaces of the first region 1A and the second region 1B.

[0009]

In the present invention, when forming the transistor region, a constriction is provided between the source / drain region and the channel contact region, and the mask during the formation of the source / drain region and the mask during the formation of the channel contact region are constricted regions. I tried to separate them within the range.

By doing so, the p ⁺ n ⁺ junction formed at the interface between the source / drain region and the channel contact region is formed in the constricted region, so that the area thereof is small and the p of the constricted region is p. Impurities for source / drain and channel contacts are not implanted between the ⁺ n ⁺ junctions, and the capacitance value can be reduced because the region is a low concentration region.

Further, by adding a step of masking a part of the constricted region, the source / drain / gate / channel contact regions can be silicidized collectively, and the resistance of the lead portion can be lowered.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an illustration of an embodiment of the present invention. The figure is a plan view of an SOI MOS FET according to the present invention having an LDD (Lightly Doped Drain) structure.

In the figure, 1 is a boundary line between a transistor region (inner side) and a felt region (outer side), 1A is a source region, a channel region, a drain region, 1B is a second region and a channel contact region, and 1C is a constricted region. , 2 is a gate electrode, 3 is a contact hole, 4 is a source / drain formation mask (the inside is an opening), 5 is a channel contact formation mask (the inside is an opening), and 6 is a sidewall etching cover mask (the outside is an opening). Opening).

The structure will be described below in order along with the process. A field region having a constricted region is formed on the SOI substrate by a conventional selective oxidation (LOCOS) method or mesa etching.

The region surrounded by the field region becomes the transistor region 1. The transistor region 1 is composed of a source, channel, drain region 1A, a channel contact region 1B and a constricted region 1C. Implant channel impurity ions into the transistor region 1. The gate electrode 2 is formed. The gate electrode 2 extends to the constricted region 1C. A mask that opens the source / drain regions made of a resist film by the ordinary lithography process and etching
4 is formed and ions of the opposite conductivity type to the channel are implanted to form a low concentration layer (LDD part) in the source / drain region 1A.

Similarly, a mask 5 having an opening in the channel contact region made of a resist film is formed by a lithography process and etching, and ions of the same conductivity type as the channel are implanted to form a channel contact region 1B.

At this time, the opening portions of both masks are in the constricted area 1C and are separated from each other by more than the alignment margin. In addition, the end of the gate electrode 2 must be outside the source / drain formation mask 4 as a matter of course. An insulating film for sidewall formation is grown on the substrate and
A sidewall etching cover mask 6 is formed on 1C. This mask is necessary to prevent the source and drain from short-circuiting through the channel contact region when the substrate is silicidized. The sidewall insulating film is anisotropically etched to form sidewalls on the side surfaces of the gate electrode. At this time, the insulating film remains under the side wall etching cover mask 6.

Here, again using the source / drain forming mask 4 and the channel contact forming mask 5, respectively, the source / drain region 1A and the channel contact region are formed.
A high-concentration layer is formed on 1B, and then a tungsten film or the like is grown on the exposed silicon surface and the gate electrode (made of a polysilicon film) and heated to perform silicidation.
After that, an interlayer insulating film is grown on the substrate and a contact hole 3 is opened in this. After this, the contact is made at each electrode section and wiring is performed using a normal process.

[0019]

According to the present invention, it is possible to form a channel contact without an increase in junction capacitance and contact resistance, and a high-speed S having a stable current-voltage characteristic without kinks.
OI-MOSFET is obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

[Explanation of symbols]

1 Border line between transistor region (inside) and field region (outside) 1A Source, channel, drain region in the first region 1B Channel contact region in the second region 1C Constriction region 2 Gate electrode 3 Contact hole 4 Mask for source / drain formation (Inner opening) 5 Channel contact formation mask (Inner opening) 6 Sidewall etching cover mask (Outer opening)

Claims (2)

[Claims] 1. A FET formed in a silicon film on an insulator
And the transistor region (1) surrounded by the field insulating film is arranged in the gate width direction in the first region (1A) and the second region.
(1B) and a constricted region (1C) connecting both of these regions, in which a source region of one conductivity type, a channel region of opposite conductivity type, and a drain region of one conductivity type are formed. A gate electrode (2) extending to the constricted region (1C) is formed on the upper part of the region, and a channel contact region composed of a diffusion layer of opposite conductivity type is formed in the second region (1B).
The constricted region (1C) has a width in the gate length direction that corresponds to the first region (1C).
A semiconductor device having a width smaller than the width A) and having a width equal to or larger than the gate length. 2. In manufacturing the semiconductor device according to claim 1, a mask (6) is formed to cover the constricted region (1C) and a part of the gate electrode (2), and the mask is formed into the first region (1A). A method of manufacturing a semiconductor device, comprising the step of etching the surface of the second region (1B).