JPH11195784A - Insulated-gate semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase latch-up resistance of a semiconductor element, and at the same time, to lower the on-state voltage of the element. SOLUTION: Gate electrodes 13a and 13b associated with insulating films 14a and 14b are arranged in a base region 12 where carriers are diffused so as to narrow a carrier diffusing flow passage. In addition, emitter regions 15a and 15b are provided at the upper end sections of the insulating films 14a and 14b, in such shapes and arrangements that holes which passed through the carrier diffusing flow passage are apt to collect on an emitter electrode 18 nor on the emitter regions 15a and 15b of a parasitic transistor, and the resistance of a base region 16 becomes smaller. When an insulated-gate semiconductor element is constructed in such a structure, the hole concentration near the narrowed flow passage is increased and the on-state voltage of the element can be reduced by a conductivity modulating effect. In addition, the parasitic transistor does not operate and an increase in latch-up resistance and a decrease in on-state voltage can be realized at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for controlling a current flowing between the other electrodes by applying a voltage to a gate electrode, and more particularly to a high latch-up withstand voltage and a low on-voltage. The present invention relates to a structure of an insulated gate semiconductor device.

[0002]

2. Description of the Related Art An insulated gate transistor changes electric conductivity of a semiconductor by an electric field effect of a gate voltage and controls a current flowing between other regions provided at both ends of a gate region. IGBT (Insulated Gate Bipolar) used especially as a power transistor
Transistor) requires high latch-up capability and low on-state voltage. Conventionally, as a semiconductor element in consideration of a high latch-up resistance and a low on-voltage, a vertical IGBT shown in FIG. 8 which enables miniaturization and high density, or a gate structure having a trench structure having substantially the same structure. 2. Description of the Related Art A semiconductor device characterized by a gate electrode (Japanese Patent Laid-Open No. 1-198076) is known.

The conventional vertical IGBT shown in FIGS. 8 and 9
And its equivalent circuit. The vertical IGBT is p
A silicon substrate doped with ^{+ -type} impurities is used as a collector region 70, on which an n ^{+ -type} buffer is sequentially formed by a so-called planar technology such as an epitaxial growth technology, a lithography technology, an ion implantation technology, a diffusion technology, and an etching technology. Region 71, n ^- type base region 72, p-type base region 7
3, n ^{+ type} emitter region 74, p ^{+ type} emitter region 8
0, an insulating gate film 76 is formed, and finally CVD (Chem)
ical Vapor Deposition), etc.
An emitter electrode 77 and a collector electrode 78 are respectively formed. In some cases, the n-type buffer region 71 may not be formed.

In this device, a field-effect transistor (Tr1) is formed by an n ⁺ -type emitter region 74, a p-type base region 73, and an n ^-- type base region 72, and a p-type base region 7 is formed.
The bipolar transistor (Tr2) is constituted by the 3, n ^--type base region 72 and the p ^{+ -type} collector region 70, and at the same time, the n ⁺ -type emitter region 74, the p-type base region 73, n
^A bipolar transistor (Tr3) composed of a-shaped base region 72 is parasitic.

When the emitter electrode 77 is grounded and a positive voltage of, for example, several hundred volts is applied to the collector electrode 78 and a positive voltage of several volts to tens of volts is applied to the gate electrode 75, a field effect type shown in FIG. The transistor (Tr1) is turned on, and electrons flow into the n ^-type base region 72. Thus, the p ⁺ -type collector region 70 n ^- Katachibe - Hall to the source region 72 are injected, the high resistivity n ^- Katachibe - source region 72 electron concentration and conductivity modulation effect of increasing equal hole concentration of Occurs.
The IGBT is an element capable of reducing the on-state voltage by this conductivity modulation effect.
One order of magnitude faster than a power transistor, its current capacity is
It is characterized by being one to two orders of magnitude larger than a MOS transistor. Since the switching speed is high, it is increasingly required in recent years to increase the current capacity.

[0006]

However, generally, as described above, an IGBT generally has an npn-type parasitic transistor including an n ⁺ -type emitter region 74, a p-type base region 73, and an n ⁻ -type base region 72. When Tr3 is present and a large current I flows, the resistance Rp is present in the p ⁺ -type emitter region 80, so that ΔV is applied to the emitter electrode 77 and the p-type base region 73.
(= I · Rp). This Δ
When V exceeds the threshold voltage (approximately 0.7 V), Tr3 is turned on, and the parasitic thyristor composed of Tr2 and Tr3 shown in FIG. 9 is turned on (latch-up state). There was a problem that control was lost.

Therefore, in the conventional example, a p ⁺ -type emitter region 80 with an even higher impurity concentration is provided to lower the resistance value Rp, and in some cases, the p ⁺ -type emitter region 80 is removed, and instead, an electrode having a trench structure is formed ( For example, Japanese Unexamined Patent Publication (Kokai) No. 1-198076) has proposed a technique in which an electrode is directly joined to the p-type base region 73 to avoid latch-up. However, in the conventional example, although the latch-up withstand capability is certainly improved, a structure in which a hole current is easily injected into the pn junction surface by the p-type base region 73 and the n ⁺ -type emitter region 74 is adopted. When a larger current flows, the parasitic thyristor is turned on as before,
The high latch-up withstand capability and the low on-voltage required in recent years are not always satisfied at the same time, and further higher performance is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in consideration of an insulated gate type semiconductor device, particularly an IG device.
In order to achieve high latch-up resistance and low on-voltage of the BT, an n ⁺ -type emitter region, a gate electrode and a p-type base are required.
Focusing on how the hole current flows due to the positional relationship of the source region,
An object of the present invention is to provide an insulated gate semiconductor device having a large latch-up resistance and a low on-voltage.

[0009]

In order to achieve this object, an insulated gate type semiconductor device according to the first aspect of the present invention has a channel formed by a first conductivity type minority carrier which is joined to an emitter electrode. In the region near the emitter electrode in the base region including the second conductivity type base region to be formed and the first conductivity type base region joined to the second conductivity type base region, a gate with an electrically insulating film forming a channel. A second conductivity type carrier injected into the first conductivity type base region from the second conductivity type collector region diffuses through the second conductivity type base region; In order to make it difficult for the second conductivity type carrier to reach the emitter region and to easily reach the emitter electrode, the carrier is in contact with the emitter electrode and the second conductivity type base region on the electrical insulating film facing the emitter electrode. Characterized in that the formation of the first conductive type emitter region.

When a voltage is applied to the gate of the insulated gate type semiconductor device, first, the field effect transistor constituting the device is turned on, and accordingly, the second conductivity type collector region of the device is turned on. A second conductivity type carrier is injected into the one conductivity type base region, and diffuses as a minority carrier in the second conductivity type base region. The diffused second conductivity type carrier passes through the flow path narrowed by the gate electrode with the electrically insulating film, and the position and direction of diffusion are restricted. On the other hand, the first conductivity type emitter region also serving as the emitter of the parasitic transistor is formed at a location away from the diffusion flow, that is, on the insulating film of the gate electrode on the emitter electrode side. Therefore, the carrier of the second conductivity type subjected to this limitation hardly flows into the emitter region of the first conductivity type, and the majority flows directly into the emitter electrode. (Recombines with majority carriers.)

That is, the parasitic transistor does not turn on within a predetermined maximum current value, and a high latch-up tolerance is realized. Further, since the flow path is narrowed by the gate electrode with the electric insulating film, the density of the second conductivity type carrier in the flow path in the first conductivity type base region is increased. The conductivity modulation effect in the region near the emitter electrode in the region is also enhanced, and the ON voltage can be substantially reduced.

Further, according to the present invention, the second conduction type carrier injected from the collector region is supplied to the second conduction type base region near the junction of the first conduction type base region with the second conduction type base region. It is characterized in that an electrically insulating region for narrowing a route to be reached is formed. Since the electrically insulating region is formed in the flow path of the second conductivity type carrier of the first conductivity type base region narrowed by the gate electrode, the second conduction type that is the minority carrier injected from the collector region is formed. The carrier is accumulated in the high resistance base region, which is the first conductivity type base region, and its concentration is improved. In the high-resistance base region close to the emitter region, the concentration of minority carriers is improved, so that the conductivity modulation is increased, and as a result, the on-voltage is reduced. Therefore, as in the case of the insulated gate semiconductor device according to the first aspect, the high latch-up withstand capability is maintained, and further lowering of the on-state voltage can be realized. In the above description, if the first conductivity type is n-type, the first conductivity type carrier is an electron, the second conductivity type is a p-type, and the second conductivity type carrier is a hole. Conversely, if the first conductivity type is p-type, the first conductivity type carrier is a hole, the second conductivity type is n-type,
The second conductivity type carrier is an electron.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. The present invention is not limited to the following embodiments. First Embodiment In the following description, the first conductivity type is an n-type, the first conductivity type carrier is an electron, the second conductivity type is a p-type, and the second conductivity type carrier is a hole. 1 and 2 are a cross-sectional view showing one cell configuration of an IGBT according to a specific embodiment of the present invention and an equivalent circuit thereof. An n ^{+ -type} buffer region 11 is formed on the p ^{+ -type} collector region 10, and an n ⁻ -type base region 1, which is a high resistance region, is formed on the n ^{+ -type} buffer region 11.
2 are formed. Electrically insulating films 14a and 14b are provided at both corners of the n ^-type base region 12 on the emitter electrode 18 side.
The gate electrodes 13a and 13b are formed with an electrode distance L so as to narrow the flow path of the carrier. Further, the p-type base region 16 is formed of the electrically insulating films 14a, 14b.
A portion n of ^- Katachibe - formed in the source region 12 on and close contact with the carrier channel central on 12A, electrically insulating film 14a on both sides thereof, n ⁺ -type emitter region 15a on the 14b, 15b
Are formed. Further, the n ^{+ type} emitter region 1
An emitter electrode 18 for providing carriers is formed on 5a, 15b and the adjacent p-type base region 16, and a collector electrode 19 is similarly formed on the collector region 10. Note that the above structure is also manufactured by a planar technique centering on a lithography technique and a solid layer epitaxial technique. The same effect is obtained even in a structure in which the n ^{+ -type} buffer region 11 is not formed.

This device is designed to have a withstand voltage of 600 V and a cutoff voltage of 4 V. The thickness of each region is as follows. The thickness of the n ⁻ -type base region 12 is about 50 μm, the concentration is 1 × 10 ¹⁴ / cm ³ , and the n ⁺ -type emitter regions 15a, 15
The impurity surface concentration of b is 1 × 10 ²⁰ / cm ³ and the thickness is about 0.3 μm. Further, the gate electrodes 13a, 13
The thickness and depth of b are about 1 μm and about 1.3 μm, respectively, and the thickness of the electrically insulating film 14 for insulating the gate electrodes 13a and 13b is about 0.1 μm. Further, the cell pitch is 4 μm.

Next, the operation of the above-structured device will be described. The emitter electrode 18 is grounded, and the collector electrode 19
A positive voltage of, for example, several hundred volts is applied to the gate electrodes 13a and 13b.
When a positive voltage of several volts to tens of volts, which is sufficiently higher than the cutoff voltage, is applied to the p-type base region 16 and the electrical insulating films 14a and 14b, the inversion layer 1
7a and 17b are formed, and the electrons are transferred to the inversion layers 17a and 17b.
Flows from the n ⁺ -type emitter regions 15a and 15b into the n ⁻ -type base region 12 (i.e., Tr1 of the equivalent circuit shown in FIG. 2 turns ON), and is diffused toward the collector region 10 by a strong electric field.

On the other hand, when the diffusion of electrons proceeds sufficiently, the potential of the n ^--type base region 12 decreases, and the pn junction is biased in the forward direction, so that a hole is formed from the p ^{+ -type} collector region 10. The n ^-type base region 12 is implanted. Injected ho
The metal is diffused through the n ^-type base region 12 toward the emitter electrode 18. The diffused holes are used as gate electrodes 13a,
As a result, the concentration increases and the resistance value of the base region 12 decreases due to conductivity modulation.
a, 15b. The holes in the n ^-type base region 12 flow into the p-type base region 16.

At this time, the resistance R is provided in the p-type base region 16.
Because of the existence of p, the parasitic Tr3 is turned on when a large current flows.
A potential difference is generated to cause the state. While securing a large current,
In order not to generate this potential difference, this R
p must be as small as possible. Therefore, in the present invention, in order to minimize the resistance value Rp, the thickness of the p-type base region 16 is reduced to the withstand voltage limit or the processing limit (about 0.3 mm).
3 μm), and the n ⁺ -type emitter regions 15a and 15b are gated.
The structure is provided at both ends of the gate electrode on the insulating film and is spaced apart from the hole flow path, and the junction area between the p-type base region 16 and the emitter electrode 18 is three times or more as compared with the conventional vertical gate structure. Structure.

As a result, the collector current density is 200 A / c
With m ² and a fall time of 300 nsec, the latch-up resistance was improved by 10% as compared with the prior art. Further, as can be seen from FIG. 7 showing the relationship between the distance L between the gate electrodes 13a and 13b for narrowing the flow path of the hole and the on-voltage in this embodiment, the distance L between the electrodes is about 0.2 μm.
At m, the on-state voltage was 1.15 V. As described above, the on-state voltage was able to be reduced by nearly 20% compared to the related art while improving the latch-up resistance.

Second Embodiment FIG. 3 shows a sectional structure of a device according to a second embodiment of the present invention. In this configuration, an electric insulator 20 is embedded in a carrier flow path 12A of an n ^-type base region 12 narrowed by a plurality of gate electrodes of the first embodiment,
Further, the carrier flow path is narrowed. With such a structure, the holes diffused from the collector region 10 are accumulated in the flow path which is further narrowed, so that the conductivity modulation effect is further enhanced. Can be reduced.

Third Embodiment FIG. 4 shows a sectional structure of an element according to a third embodiment of the present invention. In this configuration, the plurality of gate electrodes 13a and 13b of the first embodiment are partially exposed on the semiconductor surface, and the emitter regions 15a and 15b are formed on both ends of the electrically insulating films 14a and 14b as shown in FIG. It is formed in. Even with such a configuration, the emitter region 15
Since a and 15b are located at positions distant from the flow path of the hole and can reduce Rp, a high latch-up resistance can be obtained. Also, as in the first embodiment, the narrowed flow path 1
Since holes of minority carriers are accumulated in 2A, the conductivity modulation effect is enhanced, and the ON voltage can be reduced.

Fourth Embodiment FIG. 5 shows a sectional structure of an element according to a fourth embodiment of the present invention. In this configuration, as shown in the drawing, the p-base region 16 of the first embodiment is extended to the flow path 12A narrowed by the gate electrode 13, and the inversion layer is formed on the electric insulating film on the flow path side during operation. 17a and 17b are formed. Further, the n ⁺ -type emitter regions 15a, 1
5b denotes the electrical insulating films 14a, 14a on the emitter side electrode side.
b. Even with such a configuration, the thickness of the portion of the p base region 16 in contact with the n ⁺ emitter regions 15a and 15b can be reduced, so that Rp can be reduced, and a high latch-up resistance can be obtained. . Further, n ^{− of the} narrowed flow channel 12A as in the first embodiment.
Since holes of minority carriers are accumulated in the base region 12, the conductivity modulation effect is enhanced, and the on-voltage can be reduced.

Fifth Embodiment FIG. 6 shows a sectional structure of an element according to a fifth embodiment of the present invention. In this configuration, as shown in the drawing, the n ⁺ buffer region 11 of the first embodiment is removed, and an n ⁺ drain region 50 is formed instead of the p ⁺ collector region 10.
the n ^- -type base layer 12 n ^- and form the drain region 51, an emitter electrode 18 source - the source electrode 180, a collector electrode 1
9 is a drain electrode 190, and the entire device is a field effect transistor (MOSFET). MOSF
In ET, when driving an inductance load, avalanche destruction caused by the operation of a parasitic bipolar transistor is a major problem, and it is very important to improve the resistance to this. As one method for improving the avalanche withstand capability, an n ^{+ -type} source region 55a,
55b and the p-type base region 56 and the n ^- type drain region 51
There is a method of making it difficult to turn on a parasitic bipolar npn transistor constituted by MO in this embodiment
In the SFET, as in the first embodiment, the p-type base region 5 is formed.
Since the resistance Rp of No. 6 can be made very small, the parasitic bipolar npn transistor is hard to be turned on as compared with the related art, and element destruction can be prevented. Therefore, MOS
Higher avalanche withstand voltage and lower on-state voltage can be realized as compared with the FET. Similarly, MOSFETs having the source, gate, and channel structures shown in FIGS. 2, 3, and 4 may be used.

Further, the present invention can be variously modified. For example, in Examples 1 to 5,
Although a plurality of gate electrodes and a plurality of emitter regions are formed to have a symmetrical structure, a structure having only one side may be used when it is not necessary to obtain a large current. In this embodiment, the IGBT and the MOSFE comprising the n-type field-effect transistor Tr1 and the pnp-type bipolar transistor Tr2 are used.
T has been described as an example, but these polarities are reversed, and p
Field effect transistor Tr1 and npn type bipolar transistor
IGBT and MOSF composed of a transistor Tr2
It may be ET. In this embodiment, the vertical IGB
Although T has been described, the invention is not limited to the vertical type but may be applied to various other types of insulated gate type semiconductor devices such as a horizontal IGBT as long as the characteristic operation principle claimed by the present invention is the same. it can.

[0024]

As is apparent from the above description, according to the insulated gate semiconductor device of the first aspect of the present invention, the second conductivity type carrier is provided in the second conductivity type base region. In the middle of the flow path, a gate electrode with an electric insulating film is
It is formed so as to narrow this flow path. Further, in order to make it difficult for the second conduction type carrier that has passed through the flow path to reach the first conduction type emitter region, the first conduction type emitter region is formed on an electrically insulating film that insulates the gate electrode. It is formed at both ends. Therefore, the field effect transistor is
With N, the concentration of the second conductivity type carrier diffused from the second conductivity type collector region in the first conductivity type base region is increased, so that the conductivity modulation degree is increased and the on-state voltage is reduced. realizable.

Further, with the above structure, the second conductivity type carriers that have passed through the flow path narrowed by the gate electrode are mostly collected at the emitter electrode, and reach near the emitter region which also serves as the emitter of the parasitic transistor. It is difficult to reduce the resistance of the second conductivity type base region, and the parasitic transistor is turned on within a predetermined maximum current value.
And a higher latch-up is realized. Therefore, according to the structure of the insulated gate semiconductor device of the present invention,
Both the required high latch-up withstand voltage and the low on-voltage can be simultaneously realized.

According to a second aspect of the present invention, there is provided an insulated gate type semiconductor device according to the first aspect, wherein the insulated gate type semiconductor device is further provided near the inside of the flow path narrowed by the gate electrode. An electrically insulating region is formed so as not to overlap with the inversion layer. Accordingly, the flow path of the minority carriers injected from the collector is further narrowed, and the concentration of the minority carriers is improved in the high-resistance base region near the emitter, the conductivity modulation is further increased, and the ON voltage is reduced. descend. Therefore, as in the case of the insulated gate semiconductor device according to the first aspect, the enhancement of the latch-up withstand capability is maintained, and further lowering of the on-state voltage can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of an insulated gate semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the insulated gate semiconductor device of the first embodiment.

FIG. 3 is a cross-sectional view of an insulated gate semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of an insulated gate semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a sectional view of an insulated gate semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of an insulated gate semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a characteristic diagram showing a relationship between a dimensional parameter and an on-voltage in the insulated gate semiconductor device of the first embodiment.

FIG. 8 is a cross-sectional view of a conventional insulated gate semiconductor device exhibiting a high withstand voltage and a low on-voltage.

FIG. 9 is an equivalent circuit diagram of a conventional insulated gate semiconductor device.

[Explanation of symbols]

Reference Signs List 10 p ^{+ -type} collector region 11 n ^{+ -type} buffer region 12 n ^--type base region 12A Carrier accumulation region 13a Gate electrode 13b Gate electrode 14a Electrical insulating film 14b Electrical insulating film 15an ⁺ Emitter region 15b n ⁺ Emitter region 16 P-type base region 17a Inversion layer 17b Inversion layer 18 Emitter electrode 19 Collector electrode 20 Electrical insulator

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[Procedure amendment]

[Submission date] March 11, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

FIG. 8 shows a structure of a conventional vertical IGBT.
Its equivalent circuit is the same as FIG. The vertical IGBT is p
A silicon substrate doped with ^{+ -type} impurities is used as a collector region 70, on which an n ^{+ -type} buffer is sequentially formed by a so-called planar technology such as an epitaxial growth technology, a lithography technology, an ion implantation technology, a diffusion technology, and an etching technology. Region 71, n ^- type base region 72, p-type base region 7
3, n ^{+ type} emitter region 74, p ^{+ type} emitter region 8
0, an insulating gate film 76 is formed, and finally CVD (Chem)
ical Vapor Deposition), etc.
An emitter electrode 77 and a collector electrode 78 are respectively formed. In some cases, the n-type buffer region 71 may not be formed.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

When the emitter electrode 77 is grounded and a positive voltage of, for example, several hundred volts is applied to the collector electrode 78 and a positive voltage of several volts to tens of volts is applied to the gate electrode 75, a field effect type shown in FIG. The transistor (Tr1) is turned on, and electrons flow into the n ^-type base region 72. Thus, the p ⁺ -type collector region 70 n ^- Katachibe - Hall to the source region 72 are injected, the high resistivity n ^- Katachibe - source region 72 electron concentration and conductivity modulation effect of increasing equal hole concentration of Occurs.
The IGBT is an element capable of reducing the on-state voltage by this conductivity modulation effect.
One order of magnitude faster than a power transistor, its current capacity is
It is characterized by being one to two orders of magnitude larger than a MOS transistor. Since the switching speed is high, it is increasingly required in recent years to increase the current capacity.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

However, generally, as described above, an IGBT generally has an npn-type parasitic transistor including an n ⁺ -type emitter region 74, a p-type base region 73, and an n ⁻ -type base region 72. When Tr3 is present and a large current I flows, the resistance Rp is present in the p ⁺ -type emitter region 80, so that ΔV is applied to the emitter electrode 77 and the p-type base region 73.
(= I · Rp). This Δ
When V exceeds the threshold voltage (approximately 0.7 V), Tr3 is turned on, and the parasitic thyristor composed of Tr2 and Tr3 shown in FIG. 2 is turned on (latch-up state). There was a problem that control was lost.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] Fig. 9

[Correction method] Deleted

Claims (2)

[Claims] 1. An insulated gate semiconductor device, comprising: a second conductivity type base region joined to an emitter electrode and a channel formed by a first conductivity type minority carrier; and a second conductivity type base region joined to the second conductivity type base region. In a region near the emitter electrode in a base region composed of one conductivity type base region,
A gate electrode with an electrical insulating film forming the channel is formed in a predetermined shape and a predetermined depth, and the second electrode implanted from the second conductivity type collector region into the first conductivity type base region. The electrical insulating film facing the emitter electrode so that the conductive type carriers diffuse in the second conductive type base region, making it difficult for the second conductive type carriers to reach the emitter region and easily reaching the emitter electrode. An insulating gate, wherein a first conductivity type emitter region is formed on said emitter electrode and said second conductivity type base region.
G semiconductor element. 2. A path for a second conductivity type carrier injected from the collector region to reach the second conductivity type base region near a junction of the first conductivity type base region with the second conductivity type base region. 2. The insulated gate semiconductor device according to claim 1, wherein an electrically insulating region to be narrowed is formed.