JP2983110B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2983110B2 JP2983110B2 JP4191578A JP19157892A JP2983110B2 JP 2983110 B2 JP2983110 B2 JP 2983110B2 JP 4191578 A JP4191578 A JP 4191578A JP 19157892 A JP19157892 A JP 19157892A JP 2983110 B2 JP2983110 B2 JP 2983110B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor layer
- conductivity type
- region
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 217
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims description 190
- 150000002500 ions Chemical class 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 238000009766 low-temperature sintering Methods 0.000 claims description 2
- 241000287462 Phalacrocorax carbo Species 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 60
- 239000000758 substrate Substances 0.000 description 27
- 230000000694 effects Effects 0.000 description 12
- 230000005684 electric field Effects 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- -1 oxygen ions Chemical class 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910018125 Al-Si Inorganic materials 0.000 description 2
- 229910018520 Al—Si Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 210000001624 hip Anatomy 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置及びその製
造方法に関し、特にＭＩＳ（Metal Insulator Silicon)
構造の制御電極を有し、該制御電極へのバイアス印加に
よって動作するパワーデバイスにおける、耐圧とスイッ
チング特性の向上を図るための素子構造及び該素子構造
を実現するための製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MIS (Metal Insulator Silicon).
The present invention relates to an element structure for improving a breakdown voltage and switching characteristics of a power device having a control electrode having a structure and operating by applying a bias to the control electrode, and a manufacturing method for realizing the element structure.
【０００２】[0002]
【従来の技術】このような電圧制御型のパワーデバイス
として、例えば文献「アイ イー イー イー トラン
ザクションズ エレクトリカル デバイス (IEEE Tran
sactions Electrical Device), ED-34(11), p.2329, 19
87」に示されたＮチャネルＵ−ＭＯＳＦＥＴがあり、図
１３はこのＭＯＳＦＥＴセルの断面構造を示している。2. Description of the Related Art As such a voltage-controlled power device, for example, a document "IEE Transactions Electrical Device (IEEE Tran
sactions Electrical Device), ED-34 (11), p.2329, 19
87 ", and FIG. 13 shows a cross-sectional structure of this MOSFET cell.
【０００３】図において、２０１はＮチャネルＵ−ＭＯ
ＳＦＥＴセル（以下Ｕ−ＭＯＳＦＥＴとも言う。）で、
これは半導体層内に形成された略Ｕ字型の溝（トレン
チ）内にゲート電極５が埋め込まれた構造を有してい
る。In the figure, reference numeral 201 denotes an N-channel U-MO
In an SFET cell (hereinafter also referred to as a U-MOSFET),
This has a structure in which a gate electrode 5 is embedded in a substantially U-shaped groove (trench ) formed in a semiconductor layer.
【０００４】以下詳述すると、上記Ｕ−ＭＯＳＦＥＴ２
０１のＮ＋半導体基板１上にはＮ−エピタキシャル層２
が形成され、これらのＮ＋半導体基板１及びＮ−エピタ
キシャル層２はドレイン領域として働くようになってお
り、また上記Ｎ−エピタキシャル層２上にはＰウェル領
域３が形成されている。このＰウェル領域３は上記Ｎ−
エピタキシャル層２の表面にＰ型半導体層をエピタキシ
ャル成長することによって得られるものである。さらに
このＰ型半導体層には、これを貫通してその下側のＮ−
エピタキシャル層２の表面に達するＵ字形トレンチが形
成されおり、このトレンチ内にはゲート絶縁膜６を介し
て、例えば高濃度に不純物がドープされたポリシリコン
が埋め込まれており、このポリシリコンがゲート電極５
となっている。[0004] The above-mentioned U-MOSFET 2
01 N + on the semiconductor substrate 1 is N - epitaxial layer 2
The N + semiconductor substrate 1 and the N − epitaxial layer 2 serve as a drain region, and a P well region 3 is formed on the N − epitaxial layer 2. The P-well region 3 is the N -
It is obtained by epitaxially growing a P-type semiconductor layer on the surface of the epitaxial layer 2. Further, the P-type semiconductor layer penetrates the N -type
A U-shaped trench reaching the surface of the epitaxial layer 2 is formed. In this trench , for example, polysilicon doped with a high concentration of impurities is buried via a gate insulating film 6, This polysilicon is used as the gate electrode 5
It has become.
【０００５】また、上記Ｐウェル領域３の上部の周辺部
分にはＮ+ ソース領域４が形成されており、上記Ｐ型ウ
ェル領域３の、上記Ｎ+ ソース領域４とＮ- エピタキシ
ャル層（ドレイン領域）２とで挟まれた、上記絶縁膜６
に近接する部分３ａが、反転層が形成されるべきチャネ
ル領域となっている。そして上記Ｎ- エピタキシャル層
２の表面側には、全面に金属のソース電極７が形成され
ており、該ソース電極７は、上記Ｎ+ ソース領域４及び
Ｐウェル領域３とは直に接触して電気的につながってお
り、またゲート電極５とはゲート絶縁膜６により絶縁さ
れている。また上記Ｎ- エピタキシャル層２の裏面側に
は、金属のドレイン電極８がＮ+ 半導体基板（ドレイン
領域）１と電気的につながるよう形成されている。また
上記各電極５，７，８はそれぞれゲート端子Ｇ，ソース
端子Ｓ，ドレイン端子Ｄに接続されている。Further, an N + source region 4 is formed in a peripheral portion above the P well region 3. The N + source region 4 and the N − epitaxial layer (drain region) of the P type well region 3 are formed. 2) above, the insulating film 6
Is a channel region where an inversion layer is to be formed. A metal source electrode 7 is formed on the entire surface of the N − epitaxial layer 2. The source electrode 7 is in direct contact with the N + source region 4 and the P well region 3. It is electrically connected and is insulated from the gate electrode 5 by the gate insulating film 6. A metal drain electrode 8 is formed on the back side of the N − epitaxial layer 2 so as to be electrically connected to the N + semiconductor substrate (drain region) 1. The electrodes 5, 7, and 8 are connected to a gate terminal G, a source terminal S, and a drain terminal D, respectively.
【０００６】次に動作について説明する。上記ドレイン
端子Ｄが高電位、ソース端子Ｓが低電位（又はアース電
位）となるように両端子間に主電圧を印加する。この状
態でゲート端子Ｇに正のバイアスを印加すると、チャネ
ル領域３ａに反転層が形成され、トランジスタはオン状
態となり、電子電流がＮ+ ソース領域４からチャネル層
３ａを通ってＮ- エピタキシャル層（ドレイン領域）２
に流れる。この状態で、上記ゲート端子Ｇをアースと短
絡させるか、またはゲート端子Ｇを負にバイアスするこ
とによりチャネル領域３ａの反転層は消滅し、トランジ
スタはオフ状態となる。Next, the operation will be described. A main voltage is applied between both terminals so that the drain terminal D has a high potential and the source terminal S has a low potential (or ground potential). When a positive bias is applied to the gate terminal G in this state, an inversion layer is formed in the channel region 3a, the transistor is turned on, and electron current flows from the N + source region 4 through the channel layer 3a to the N − epitaxial layer ( Drain region) 2
Flows to In this state, when the gate terminal G is short-circuited to the ground or the gate terminal G is negatively biased, the inversion layer in the channel region 3a disappears, and the transistor is turned off.
【０００７】このようにチャネルが縦方向に形成される
Ｕ−ＭＯＳＦＥＴ２０１ではチャネルが横方向に形成さ
れるＤ−ＭＯＳＦＥＴ、つまりチャネル領域を２重拡散
（Double diffusion) により形成した一般的なＭＯＳＦ
ＥＴと比べていくつかの利点があるが、その利点を説明
する前にＤ−ＭＯＳＦＥＴの構造について簡単に説明す
る。As described above, the U-MOSFET 201 in which the channel is formed in the vertical direction is a D-MOSFET in which the channel is formed in the horizontal direction, that is, a general MOSF in which the channel region is formed by double diffusion.
There are several advantages over ET, but before describing the advantages, the structure of the D-MOSFET will be briefly described.
【０００８】図１８はＤ−ＭＯＳＦＥＴの一般的な構造
を示しており、図中３０１はＤ−ＭＯＳＦＥＴで、この
Ｄ−ＭＯＳＦＥＴ３０１では、Ｐ+ 半導体基板３１１上
のＮエピタキシャル層３１２内に複数のＰ型半導体領域
３１３が所定の間隔を隔てて形成され、さらに該Ｐ型半
導体領域３１３の表面両端部にはＮ+ 半導体領域３１４
が形成されており、上記Ｐ型半導体領域３１３の表面領
域の、上記Ｎ+ 半導体領域３１４とＮ型エピタキシャル
層３１２との間の部分に横方向にチャネル３１３ｂ1 が
形成されるようになっている。ここで上記Ｐ型半導体領
域３１３は二重拡散により形成されており、つまり最初
のＰ型不純物の拡散により第１のウェル領域３１３ａを
形成し、次のＰ型不純物の拡散によりチャネル領域３１
３ｂ1 を含む第２のウェル領域３１３ｂを形成すること
により上記Ｐ型半導体領域３１３が形成されている。FIG. 18 shows a general structure of a D-MOSFET. In the drawing, reference numeral 301 denotes a D-MOSFET. In this D-MOSFET 301, a plurality of P-MOSFETs are formed in an N epitaxial layer 312 on a P + semiconductor substrate 311. Semiconductor regions 313 are formed at predetermined intervals, and N + semiconductor regions 314 are formed at both ends of the surface of P-type semiconductor region 313.
Is formed, and a channel 313b1 is formed laterally in a portion of the surface region of the P-type semiconductor region 313 between the N + semiconductor region 314 and the N-type epitaxial layer 312. Here, the P-type semiconductor region 313 is formed by double diffusion, that is, the first well region 313a is formed by diffusion of the first P-type impurity, and the channel region 31 is formed by diffusion of the next P-type impurity.
The P-type semiconductor region 313 is formed by forming the second well region 313b including 3b1.
【０００９】なお３１５は上記Ｎ型エピタキシャル層３
１２上に、隣接するＰ型半導体領域３１３のチャネル領
域３１３ｂ1 に跨がるようゲート絶縁膜３１６を介して
形成されたゲート電極、３１７は上記Ｐ型半導体領域３
１３上にＮ+ 領域と電気的につながるよう形成されたエ
ミッタ電極、３１８は上記Ｐ+ 型半導体基板３１１の裏
面に形成されたコレクタ電極である。Reference numeral 315 denotes the N-type epitaxial layer 3
The gate electrode 317 is formed on the gate electrode 12 via a gate insulating film 316 so as to extend over the channel region 313b1 of the adjacent P-type semiconductor region 313.
An emitter electrode 318 formed on the N + region 13 so as to be electrically connected to the N + region is a collector electrode formed on the back surface of the P + type semiconductor substrate 311.
【００１０】このような構造のＤ−ＭＯＳＦＥＴ３０１
と比べて上記Ｕ−ＭＯＳＦＥＴ２０１では、まず、チャ
ネルが縦方向に形成されるため、１つのチャネル領域を
形成するための単位構造，つまり１つのゲート電極５と
その両側のＮ+ ソース領域４を含む１ユニットセルの表
面積を小さくでき、セルの高集積化が可能となる。The D-MOSFET 301 having such a structure
In comparison with the U-MOSFET 201, the channel is first formed in the vertical direction, so that it includes a unit structure for forming one channel region, that is, one gate electrode 5 and N + source regions 4 on both sides thereof. The surface area of one unit cell can be reduced, and the cell can be highly integrated.
【００１１】また、第２にＵ−ＭＯＳＦＥＴでは、Ｄ−
ＭＯＳＦＥＴで問題となるウェル領域３１３相互間で生
じるＪ−ＦＥＴ効果がその構造上存在せず、このため極
めて低いオン抵抗の素子が得られる。Second, in the U-MOSFET, the D-
There is no J-FET effect between the well regions 313, which is a problem in the MOSFET, due to its structure, and an element with extremely low on-resistance can be obtained.
【００１２】すなわち、Ｄ−ＭＯＳＦＥＴ３０１の構造
では、隣接するウェル領域３１３が対向して配置されて
いるため、オン電流Ｉｏｎは図１８に示すように左右の
ウェル領域３１３のＮ ＋ 半導体領域３１４からチャネル
領域３１３ｂ１を介してＮエピタキシャル層３１２の、
ゲート電極３１５の中央直下部分３１２ａに集中して流
れ込むこととなり、またこのＮエピタキシャル層３１２
のゲート電極直下部分３１２ａは、Ｊ−ＦＥＴ効果によ
り、つまりその両側のＰ型ウェル領域３１３とのＰＮ接
合面から延びる空乏層により電流経路Ｗｊが狭くなって
おり、この部分３１２ａの抵抗Ｒｇは大きなものとなっ
ている。この結果ＭＯＳＦＥＴ素子のオン抵抗が大きく
増大していまう。That is, in the structure of the D-MOSFET 301, since the adjacent well regions 313 are arranged facing each other, the ON current Ion is changed from the N + semiconductor region 314 of the left and right well regions 313 as shown in FIG. Of the N epitaxial layer 312 through the region 313b1,
This flows intensively into the portion 312a just below the center of the gate electrode 315, and the N epitaxial layer 312
The portion 312a immediately below the gate electrode has a narrow current path Wj due to the J-FET effect, that is, a depletion layer extending from the PN junction surface with the P-type well region 313 on both sides thereof, and the resistance Rg of this portion 312a is large. It has become something. As a result, the on-resistance of the MOSFET element is greatly increased.
【００１３】これに対し、Ｕ−ＭＯＳＦＥＴ２０１の構
造では、隣接するウェル領域３はトレンチ２０１ａによ
り分離されており、しかも各ウェル領域３は広いＮ- エ
ピタキシャル層２上に位置しているため、オン電流は図
１３に示すように各ウェル領域３からその下側の広いＮ
- エピタキシャル層２に直接流れ出ることとなり、狭い
領域に集中することはなく、またＰ型ウェル領域３とＮ
- エピタキシャル層２とのＰＮ接合面から延びる空乏層
によりオン電流の経路が狭められることもない。この結
果オン抵抗の極めて低いＭＯＳＦＥＴ素子を実現するこ
とができる。On the other hand, in the structure of the U-MOSFET 201, the adjacent well regions 3 are separated by the trench 201a, and each well region 3 is located on the wide N - epitaxial layer 2, so that the on-current is reduced. As shown in FIG. 13, each of the well regions 3 has a large N
- will flow out directly into the epitaxial layer 2, not be concentrated in a narrow region and P-type well region 3 and the N
- it is nor narrowed path of on-state current by a depletion layer extending from PN junction surface between the epitaxial layer 2. As a result, a MOSFET element having an extremely low on-resistance can be realized.
【００１４】またパワーデバイスには、上述したＵ−Ｍ
ＯＳＦＥＴの他に、絶縁ゲート型バイポーラトランジス
タ（ＩＧＢＴ）やサイリスタ等の素子がある。The power device includes the above-described UM
In addition to the OSFET, there are elements such as an insulated gate bipolar transistor (IGBT) and a thyristor.
【００１５】上記ＩＧＢＴの構造は、上記Ｕ−ＭＯＳＦ
ＥＴの構造において、そのＮ+ 半導体基板１をこれに代
えてＰ+ 半導体基板としたもので、その他の構成は上記
Ｕ−ＭＯＳＦＥＴと同一である。このＩＧＢＴでは、動
作電流は上記ＭＯＳＦＥＴのように電子電流だけではな
く、正孔電流も加わることとなり、パワーＭＯＳＦＥＴ
よりさらに大きな電流を扱うことが可能であるが、スイ
ッチング速度が、動作電流に移動度が電子に比べて遅い
正孔の電流成分を含むためＭＯＳＦＥＴに比べて遅いと
いう欠点がある。ただし最近ではＩＧＢＴでも改良が進
み、スイッチング速度もかなり向上している。The structure of the IGBT is the same as that of the U-MOSF
In the structure of the ET, the N + semiconductor substrate 1 is replaced with a P + semiconductor substrate, and other configurations are the same as those of the U-MOSFET. In this IGBT, the operating current includes not only an electron current but also a hole current, as in the above-described MOSFET.
Although an even larger current can be handled, there is a disadvantage that the switching speed is lower than that of the MOSFET because the operating current includes a current component of holes whose mobility is lower than that of the electron. However, recently, improvements have been made in IGBTs, and the switching speed has been considerably improved.
【００１６】以下さらに従来のサイリスタ素子としてエ
ミッタスイッチドサイリスタ（ＥＳＴ）について説明す
る。Hereinafter, an emitter-switched thyristor (EST) will be described as a conventional thyristor element.
【００１７】図１６はＥＳＴ素子の構造の一例を示して
おり、図において２０２はＥＳＴ素子で、そのＰ+ 半導
体基板１０の上主面上にＮ- エピタキシャル層２０が形
成され、Ｎ- エピタキシャル層２０上にはＰ拡散領域１
１ａとＰ+ 拡散領域１１ｂとが隣接して形成されてい
る。またＰ拡散領域１１ａの中央付近の上部には、Ｎ+
拡散領域１２，Ｐ拡散領域１３が下から順に形成されて
おり、さらにＰ拡散領域１３の上部の周辺部分には選択
的にＮ+ 拡散領域１４が形成されている。ここで上記Ｐ
+ 半導体基板１０，Ｎ- エピタキシャル層２０，Ｐ拡散
領域１１ａ，Ｐ+拡散領域１１ｂ及びＮ+ 拡散領域１４
は、ＥＳＴ素子のサイリスタ部分を構成している。[0017] Figure 16 shows an example of a structure of an EST device, in 202 EST elements in FIG, N on the upper major surface of the P + semiconductor substrate 10 - epitaxial layer 20 is formed, N - epitaxial layer P diffusion region 1 on 20
1a and P + diffusion region 11b are formed adjacent to each other. In addition, N + is provided above the vicinity of the center of the P diffusion region 11a.
Diffusion region 12 and P diffusion region 13 are formed in order from the bottom, and N + diffusion region 14 is selectively formed in a peripheral portion above P diffusion region 13. Where P
+ Semiconductor substrate 10, N − epitaxial layer 20, P diffusion region 11a, P + diffusion region 11b, and N + diffusion region 14
Constitutes the thyristor portion of the EST element.
【００１８】一方、上記Ｐ拡散領域１１ａの周辺部の上
部にはポリＳｉ等で形成されたゲート電極１５が形成さ
れており、ゲート電極１５は絶縁膜１６によってその周
りの半導体領域と絶縁分離されている。即ち、ゲート電
極１５は絶縁膜１６，Ｎ+ 拡散領域１４，Ｐ拡散領域１
３，Ｎ+ 拡散領域１２と共に縦型のＭＯＳ構造を形成し
ており、このＭＯＳ構造の部分がＥＳＴ素子のスイッチ
部分となっている。On the other hand, a gate electrode 15 made of poly-Si or the like is formed above the peripheral portion of the P diffusion region 11a, and the gate electrode 15 is insulated and isolated from the surrounding semiconductor region by an insulating film 16. ing. That is, the gate electrode 15 is composed of the insulating film 16, the N + diffusion region 14, and the P diffusion region 1.
A vertical MOS structure is formed together with the 3, N + diffusion region 12, and the portion of the MOS structure serves as a switch portion of the EST element.
【００１９】ここで上記Ｐ+ 拡散領域１１ｂと、Ｎ+ 拡
散領域１４及びＰ拡散領域１３とはＡｌ−Ｓｉ電極１７
によって短絡され、金属電極１８はＰ+ 基板１０の下主
面上に形成され、該基板１０と電気的に接続されてい
る。なお１６ｂは上記Ａｌ−Ｓｉ電極１７とゲート電極
１５とを電気的に分離する絶縁膜である。Here, the P + diffusion region 11b, the N + diffusion region 14 and the P diffusion region 13 are
The metal electrode 18 is formed on the lower main surface of the P + substrate 10 and is electrically connected to the substrate 10. Reference numeral 16b denotes an insulating film for electrically separating the Al-Si electrode 17 from the gate electrode 15.
【００２０】次に動作について説明する。図１７は上記
サイリスタの動作を説明するための図であり、図１６で
示すサイリスタの素子構造において流れる電流の経路を
示しており、図中、実線Ｈ１〜Ｈ４はホールの流れを、
破線Ｅ１，Ｅ２は電子の流れを示している。なお、ここ
では金属電極１８をアノード端子Ａに、Ａｌ−Ｓｉ電極
１７をコレクタ端子Ｃに、ゲート電極１５をゲート端子
Ｇにそれぞれ接続し、上記サイリスタを動作させる場合
について説明する。Next, the operation will be described. FIG. 17 is a diagram for explaining the operation of the thyristor, and shows a path of a current flowing in the element structure of the thyristor shown in FIG. 16. In FIG. 17, solid lines H1 to H4 indicate the flow of holes.
Dashed lines E1 and E2 indicate the flow of electrons. Here, a case will be described in which the metal electrode 18 is connected to the anode terminal A, the Al-Si electrode 17 is connected to the collector terminal C, and the gate electrode 15 is connected to the gate terminal G to operate the thyristor.
【００２１】上記ゲート端子Ｇの電位がコレクタ端子Ｃ
の電位と等しい場合には、アノード端子Ａの電位を上昇
させていくと、Ｐ拡散領域１１ａ及びＰ+ 拡散領域１１
ｂとＮ- エピタキシャル層２０とが作るＰＮ接合は逆バ
イアス状態となり、このＰＮ接合面Ｊから空乏層が延
び、これによってコレクタ端子Ｃとアノード端子Ａの間
の耐圧が保持される。この状態では上記サイリスタ２０
２はオフしている。The potential at the gate terminal G is equal to the potential at the collector terminal C.
When the potential of the anode terminal A is increased, the P diffusion region 11a and the P + diffusion region 11
The PN junction formed by b and the N − epitaxial layer 20 is in a reverse bias state, and a depletion layer extends from the PN junction surface J, whereby the breakdown voltage between the collector terminal C and the anode terminal A is maintained. In this state, the thyristor 20
2 is off.
【００２２】一方、ゲート端子Ｇの電位がコレクタ端子
Ｃの電位よりも高くなると、Ｐ拡散領域１３の、絶縁膜
１６を介してゲート電極１５に近接している部分がＮ型
に反転し、Ｎ型のチャネル１３ａが形成される。この結
果、破線Ｅ１に示すように電子がコレクタ端子ＣからＡ
ｌ−Ｓｉ電極１７、Ｎ+ 拡散領域１４及び上記チャネル
を通ってＮ+ 拡散領域１２へ流れ込む。この時Ｎ+ 拡散
領域１２とＰ拡散領域１１ａとの間には順バイアスがか
かっているので電子はさらにＮ- エピタキシャル層２０
へ注入される（破線Ｅ２参照）。On the other hand, when the potential of the gate terminal G becomes higher than the potential of the collector terminal C, the portion of the P diffusion region 13 which is close to the gate electrode 15 via the insulating film 16 is inverted to N-type. A mold channel 13a is formed. As a result, as shown by the broken line E1, the electrons move from the collector terminal C to A
It flows into the N + diffusion region 12 through the l-Si electrode 17, the N + diffusion region 14 and the channel. At this time, since a forward bias is applied between the N + diffusion region 12 and the P diffusion region 11a, electrons are further transferred to the N − epitaxial layer 20.
(See broken line E2).
【００２３】またこの時、Ｐ+ 基板１０とＮ- エピタキ
シャル層２０との間にも順バイアスがかかっているの
で、ホールがアノード端子Ａから金属電極１８及びＰ+
基板１０を通ってＮ- エピタキシャル層２０へ注入され
る。このＮ- エピタキシャル層２０へ注入されたホール
の一部は実線Ｈ４で示すようにさらにＰ拡散領域１１ａ
を通ってＮ+ 拡散領域１２に注入され、他の一部はＮ-
エピタキシャル層２０から直接、あるいはさらにＰ拡散
領域１１ａを経由して、Ｐ+ 拡散領域１１ｂへと向かう
（実線Ｈ２，Ｈ３参照）。At this time, since a forward bias is also applied between the P + substrate 10 and the N − epitaxial layer 20, holes move from the anode terminal A to the metal electrode 18 and the P +
It is implanted through substrate 10 into N − epitaxial layer 20. Some of the holes injected into the N - epitaxial layer 20 further include a P diffusion region 11a as shown by a solid line H4.
Through the N + diffusion region 12 while the other part is N −.
Directly from the epitaxial layer 20 or further to the P + diffusion region 11b via the P diffusion region 11a (see solid lines H2 and H3).
【００２４】ここで、Ｎ+ 拡散領域１２，Ｐ拡散領域１
１ａ，Ｎ- エピタキシャル層２０及びＰ+ 基板１０によ
ってサイリスタが構成されているので、電流が保持電流
Ｉh以上になると、サイリスタ動作が行われる。このサ
イリスタ動作が行われているとき、Ｐ拡散領域１１ａを
通ってＮ+ 拡散領域１２に注入されるホール（経路Ｈ
４）は、ほとんどＮ+ 拡散領域１２内で再結合し、Ａｌ
−Ｓｉ電極１７へ向かうことはない。即ちＰ拡散領域１
３の、チャネルが形成されていない部分では電子もホー
ルも移動せず、この部分に形成された抵抗Ｒ１３には電
流が流れない。従って、抵抗Ｒ１３においては電圧降下
が生じることもなく、Ｎ+ 拡散領域１４とＰ拡散領域１
３の間に順バイアスがかかることもないので依然とし
て、Ｐ拡散領域１３中を流れる電流の経路はチャネルに
限定される。Here, the N + diffusion region 12 and the P diffusion region 1
Since the thyristor is constituted by 1a, the N − epitaxial layer 20 and the P + substrate 10, a thyristor operation is performed when the current exceeds the holding current Ih. When this thyristor operation is performed, holes (path H) injected into N + diffusion region 12 through P diffusion region 11a
4) recombine almost in the N + diffusion region 12 and
-It does not go to the Si electrode 17. That is, the P diffusion region 1
In No. 3 where no channel is formed, neither electrons nor holes move, and no current flows through the resistor R13 formed in this portion. Accordingly, no voltage drop occurs in the resistor R13, and the N + diffusion region 14 and the P diffusion region 1
Since no forward bias is applied during the period 3, the path of the current flowing through the P diffusion region 13 is still limited to the channel.
【００２５】この結果ラッチアップの発生を招くことな
く、つまり上記Ｐ拡散領域１３を含む寄生サイリスタを
動作させることなく、ゲート電極１５によってコレクタ
端子Ｃとアノード端子Ａの間を流れる電流を制御するこ
とができ、最大可制御電流を高めることができる。しか
も既述のように、電流の経路はＰ拡散領域１３内では、
チャネル１３ａに限定されるので、Ｐ拡散領域１３はそ
の抵抗Ｒ１３を高める等の改善は不要であり、ＯＮ抵抗
を増大させてしまうこともない。As a result, the current flowing between the collector terminal C and the anode terminal A is controlled by the gate electrode 15 without causing latch-up, that is, without operating the parasitic thyristor including the P diffusion region 13. And the maximum controllable current can be increased. In addition, as described above, the current path is within the P diffusion region 13.
Since the P diffusion region 13 is limited to the channel 13a, the P diffusion region 13 does not require any improvement such as increasing the resistance R13 and does not increase the ON resistance.
【００２６】ここで、Ｐ拡散領域１１ｂはＯＮ状態から
ＯＦＦ状態への移行を速やかにする役割を果たすもので
ある。つまりＯＮ状態においてゲート端子Ｇの電圧、即
ちゲート電極１５の電圧を低下させると、前述のサイリ
スタ部分に直列に接続されるチャネルが消失していき、
サイリスタ動作が停止するが、このとき、Ｐ+ 基板１０
からＮ- エピタキシャル層２０に注入されたホールはＰ
拡散領域１１ａのみならず、Ｐ+ 拡散領域１１ｂへも流
入して消滅することとなり、上記Ｐ+ 拡散領域１１ｂか
らのホールの引抜きによりサイリスタ素子のターンオフ
がより早く行われることとなる。Here, the P diffusion region 11b plays a role in speeding up the transition from the ON state to the OFF state. That is, when the voltage of the gate terminal G, that is, the voltage of the gate electrode 15 is reduced in the ON state, the channel connected in series to the thyristor portion described above disappears,
The thyristor operation stops, but at this time, the P + substrate 10
Holes injected into the N - epitaxial layer 20 from P
The thyristor element flows into the P + diffusion region 11b as well as the diffusion region 11b and disappears, and the thyristor element is turned off more quickly by extracting holes from the P + diffusion region 11b.
【００２７】[0027]
【発明が解決しようとする課題】従来のＵ−ＭＯＳＦＥ
Ｔ２０１では、ＭＯＳＦＥＴセルはトレンチ内にゲート
電極を埋め込んだ構造を有し、縦方向にチャネルが形成
されるトレンチセル構造となっているので、セルの高集
積化による低オン抵抗化が容易になるという長所がある
反面、トレンチセルの形成による耐圧の低下という問題
点があり、以下詳述する。SUMMARY OF THE INVENTION Conventional U-MOSFE
In T201, the MOSFET cell has a structure in which a gate electrode is buried in a trench, and has a trench cell structure in which a channel is formed in a vertical direction. Therefore, it is easy to reduce on-resistance by high integration of the cell. On the other hand, there is a problem that the withstand voltage is reduced due to the formation of the trench cell.
【００２８】図１４は耐圧低下の原因となる電界集中の
様子を説明するための図であり、シミュレーションによ
ってコレクタ電極に６２Ｖの逆バイアスを印加した状態
を実現したところ、トレンチの底面コーナー部，つまり
Ｎ- エピタキシャル層２の、ゲート電極５の下部コーナ
部に近接する部分に電界が集中しているのがわかる。こ
の部分の電界強度は４．８×１０5 Ｖ/cm とバルク領域
での電界強度に比べて７〜１０倍高い値であり、耐圧が
このトレンチの底面コーナー部によって律速されること
になる。FIG. 14 is a view for explaining the state of electric field concentration which causes a decrease in withstand voltage. When a state where a reverse bias of 62 V is applied to the collector electrode by simulation is realized, the bottom corner of the trench, that is, It can be seen that the electric field is concentrated on the portion of the N − epitaxial layer 2 close to the lower corner of the gate electrode 5. The electric field intensity at this portion is 4.8 × 10 5 V / cm, which is 7 to 10 times higher than the electric field intensity in the bulk region, and the breakdown voltage is limited by the bottom corner portion of the trench.
【００２９】この耐圧低下に対する改善案として図１５
に示すように、Ｎ- エピタキシャル層２内に、埋込み型
のゲート電極５の底面及びコーナー部が覆われるようフ
ローティングＰ+ 拡散領域９を形成し、上記コーナー部
での電界集中を緩和する方法等も提案されているが、上
記Ｐ+ 拡散領域９を形成する際、横方向拡散を精密に制
御できない等の製造プロセス上の問題があり、上記電界
強度の集中を充分緩和することができないという問題点
があった。FIG. 15 shows an improvement plan for this decrease in withstand voltage.
As shown in FIG. 3, a floating P + diffusion region 9 is formed in the N − epitaxial layer 2 so as to cover the bottom surface and the corner of the buried type gate electrode 5, and a method of alleviating the electric field concentration at the corner described above. However, when the P + diffusion region 9 is formed, there is a problem in the manufacturing process such that the lateral diffusion cannot be precisely controlled, and the concentration of the electric field intensity cannot be sufficiently reduced. There was a point.
【００３０】また図１６，図１７に示したサイリスタの
素子構造では、高ラッチアップ耐性に効果的である反
面、ターンオフ時、再結合によって消滅するホール以外
のホールはＰ+ 領域１１ｂからまとめてカソード端子Ｃ
に引き抜かれる比較的長い経路Ｈ２，Ｈ３を辿ることと
なり、ターンオフ時間の短縮は図れないものであるとい
う問題点があった。The thyristor element structure shown in FIGS. 16 and 17 is effective for high latch-up resistance, but holes other than holes that disappear by recombination at turn-off are collectively formed from the P + region 11b. Terminal C
Therefore, there is a problem that the turn-off time cannot be shortened because of the relatively long paths H2 and H3 that are extracted.
【００３１】この発明は上記のような問題点を解消する
ためになされたもので、ゲート電極をトレンチ内に埋め
込んだ、縦方向にチャネルが形成される素子構造におい
て、電界集中を緩和することができ、耐圧の向上を図る
ことができる半導体装置及びその製造方法を得ることを
目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In an element structure in which a gate electrode is buried in a trench and a channel is formed in a vertical direction, electric field concentration can be reduced. It is an object of the present invention to provide a semiconductor device capable of improving the breakdown voltage and a method for manufacturing the same.
【００３２】またこの発明は、サイリスタの素子構造に
おいて、ターンオフ時に正孔電流を引き抜くためのバイ
パス経路を形成することができ、これによりターンオフ
時間の短縮を図ることができる半導体装置及びその製造
方法を得ることを目的とする。Further, according to the present invention, there is provided a semiconductor device and a method of manufacturing the same, in which a bypass path for extracting a hole current at the time of turn-off can be formed in the element structure of the thyristor, whereby the turn-off time can be reduced. The purpose is to gain.
【００３３】[0033]
【課題を解決するための手段】この発明（請求項１）に
係る半導体装置は、表面の一部分が突出した第１導電型
の半導体層と、 該半導体層の突出部の表面上に形成さ
れた第２導電型のウェル領域と、該第２導電型のウエル
領域の側面、及び上記半導体層の突出部の側面に近接す
るよう形成された制御電極と、該制御電極と上記半導体
層との間に形成された第１の絶縁膜と、上記制御電極と
上記ウエル領域との間に形成された第２の絶縁膜と、該
ウエル領域表面部の周辺部分に形成された第１導電型の
半導体領域と、上記半導体層表面側に該第１導電型の半
導体領域と電気的につながるよう形成された第１の主電
極と、上記半導体層裏面側にこの半導体層と電気的につ
ながるよう形成された第２の主電極とを備え、上記第１
の絶縁膜の少なくとも一部をその基準膜厚に対して薄膜
化して、該第１の絶縁膜を、その膜厚が第２の絶縁膜の
膜厚より薄い薄膜部を有する構造とし、上記制御電極に
所定のオン電位の順バイアスを印加した時、上記第２導
電型のウエル領域の、該制御電極と近接する部分にチャ
ネルが形成され、上記制御電極に所定のオフ電位の逆バ
イアスを印加した時、上記第１導電型の半導体層におけ
る、上記第１の絶縁膜の薄膜部を介して該制御電極に近
接する領域が、第２導電型領域に反転するよう構成した
ものである。Means for Solving the Problems A semiconductor device according to the present invention (Claim 1) includes a first conductive type semiconductor layer portion of the surface protrudes, made form on the surface of the protruding portion of the semiconductor layer A second conductivity type well region, a side surface of the second conductivity type well region , and a side surface of the protrusion of the semiconductor layer.
A control electrode formed as described above, a first insulating film formed between the control electrode and the semiconductor layer, and a second insulating film formed between the control electrode and the well region. A first conductivity type semiconductor region formed in a peripheral portion of the well region surface portion; and a first main electrode formed on the semiconductor layer surface side to be electrically connected to the first conductivity type semiconductor region. And a second main electrode formed on the back side of the semiconductor layer so as to be electrically connected to the semiconductor layer.
At least a part of the insulating film is thinned with respect to the reference film thickness, and the first insulating film has a structure having a thin film portion whose film thickness is smaller than the film thickness of the second insulating film. When a forward bias of a predetermined ON potential is applied to the electrode, a channel is formed in a portion of the second conductivity type well region adjacent to the control electrode, and a reverse bias of a predetermined OFF potential is applied to the control electrode. Then, a region of the semiconductor layer of the first conductivity type, which is close to the control electrode via the thin film portion of the first insulating film, is inverted to a region of the second conductivity type.
【００３４】この発明（請求項２）は、請求項１記載の
半導体装置において、上記第１導電型の半導体層の、上
記第１の絶縁膜を介して上記制御電極の底面に近接する
部分では、その他の部分に比べて不純物濃度が低くなっ
ており、上記逆バイアスの印加時、上記半導体層の、上
記制御電極に隣接する部分には、第２導電型の反転領域
が上記第１の絶縁膜の表面を全て覆うよう形成される構
成としたものである。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a portion of the semiconductor layer of the first conductivity type adjacent to a bottom surface of the control electrode via the first insulating film. Has a lower impurity concentration than the other portions, and when the reverse bias is applied, a second conductivity type inversion region is formed in a portion of the semiconductor layer adjacent to the control electrode. The structure is formed so as to cover the entire surface of the insulating film.
【００３５】この発明（請求項３）は、請求項１記載の
半導体装置において、上記第１導電型の半導体層の、上
記第１の絶縁膜を介して上記制御電極の底面及びその底
面側端のコーナ部に近接する部分には、第２導電型の半
導体領域が形成され、上記第１の絶縁膜の上記制御電極
の側面と接する部分が上記薄膜部となっており、上記第
１の絶縁膜の上記制御電極の底面と接する部分は、上記
薄膜部に比べて厚くなっており、上記逆バイアスの印加
時、上記半導体層の、第１の絶縁膜に近接する第１導電
型領域が第２導電型に反転して、上記第２導電型のウエ
ル領域と上記第２導電型の半導体領域とが上記第２導電
型反転領域により短絡される構成としたものである。According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the bottom surface of the control electrode and the bottom end of the semiconductor layer of the first conductivity type via the first insulating film. A semiconductor region of the second conductivity type is formed in a portion adjacent to the corner portion, and a portion of the first insulating film in contact with the side surface of the control electrode is the thin film portion. The portion of the film that is in contact with the bottom surface of the control electrode is thicker than the thin film portion, and when the reverse bias is applied, the first conductivity type region of the semiconductor layer adjacent to the first insulating film is the second conductive type region. The second conductivity type well region and the second conductivity type semiconductor region are short-circuited by the second conductivity type inversion region after being inverted to the two conductivity type.
【００３６】この発明（請求項４）は、請求項３記載の
半導体装置において、上記第２導電型のウェル領域は、
その上面側の両端部間の距離がその底面側の両端部間の
距離より小さくなるようその側面が傾斜した断面形状と
なっており、上記制御電極は、その上面側の両端部間の
距離がその底面側の両端部間の距離より大きくなるよう
その側面が傾斜して、上記ウエル領域の側面と一定間隔
を隔てて対向する断面形状となっており、上記ウエル領
域と上記制御電極との間には上記第２の絶縁膜が介在し
ている構成としたものである。According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the well region of the second conductivity type is
The distance between both ends on the top side is between the two ends on the bottom side
Distance has become smaller than so as the cross-sectional shape that the side surface is inclined, the control electrode is between the ends of the upper surface
The side surface is inclined so that the distance is larger than the distance between both end portions on the bottom surface side, and has a cross-sectional shape facing the side surface of the well region at a fixed interval, and The second insulating film is interposed between the control electrode and the control electrode.
【００３７】この発明（請求項５）は、請求項１ないし
４のいずれかに記載の半導体装置において、上記第２の
絶縁膜を、その基準膜厚に対してその膜厚を増大し、か
つその第２導電型のウェル領域と接する部分にイオンを
注入して固定電荷を形成した構造とし、上記第２の絶縁
膜の基準膜厚に対する膜厚増大による制御電極の容量の
基準値に対する減少分を、上記第１の絶縁膜の基準膜厚
に対する薄膜化による制御電極の容量の基準値に対する
増大分と等しくし、かつ上記第２の絶縁膜の基準膜厚に
対する膜厚増大によるしきい値電圧の基準値に対する増
大分を、上記第２の絶縁膜での固定電荷の形成によるし
きい値電圧の基準値に対する減少分と等しくしたもので
ある。 The present invention (Claim 5) is characterized by Claims 1 to
4. The semiconductor device according to claim 4, wherein the thickness of the second insulating film is increased with respect to the reference thickness.
A structure in which fixed charges are formed by implanting ions into a portion in contact with the well region of the second conductivity type;
The capacitance of the control electrode is increased by increasing the film thickness relative to the reference film thickness.
The amount of decrease with respect to the reference value is calculated as the reference thickness of the first insulating film.
To the reference value of the control electrode capacitance by thinning
Equal to the increase and the reference thickness of the second insulating film
Increase of threshold voltage with respect to reference value
Oita is largely due to the formation of fixed charges in the second insulating film.
Threshold voltage equal to the decrease from the reference value
is there.
【００３８】この発明（請求項６）に係る半導体装置の
製造方法は、請求項４記載の半導体装置を製造する方法
において、第１導電型の第１半導体層上に第２導電型の
第２半導体層を形成し、該第２半導体層内に第１導電型
の第３半導体層を選択的に形成する工程と、上記第１な
いし第３半導体層を選択的に除去して、上記第２及び第
３半導体層を貫通する断面逆台形形状の第１の溝を形成
するとともに、断面台形形状の第２導電型のウェル領域
及び上記第１導電型の半導体領域を形成する工程と、上
記第１の溝の底面部分を選択的に除去して、上記第１半
導体層の表面部分に断面長方形形状の第２の溝を形成す
る工程と、上記第１及び第２の溝の内壁面上に絶縁膜を
所定の膜厚でもって形成し、その後全面に酸素イオンビ
ームを照射する工程と、熱処理により、上記第１の溝内
壁面上及び第２の溝底面上の絶縁膜を、第２の溝側壁面
上の絶縁膜より厚くする工程と、その後制御電極を上記
第１及び第２の溝内に埋め込み、上記ウェル領域上に上
記第１導電型の半導体領域と電気的につながるよう第１
の主電極を、上記第１半導体層の裏面側にこれと電気的
につながるよう第２の主電極を形成する工程とを含むも
のである。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect, wherein the second conductive type second semiconductor layer is formed on the first conductive type first semiconductor layer. Forming a semiconductor layer and selectively forming a third semiconductor layer of the first conductivity type in the second semiconductor layer; and selectively removing the first to third semiconductor layers to form the second semiconductor layer. and to form a first groove cross-sectional inverted trapezoidal shape extending through the third semiconductor layer, forming a second conductivity type well region and the semiconductor region of the first conductivity type of the cross-sectional surface trapezoidal, the Selectively removing a bottom portion of the first groove to form a second groove having a rectangular cross section in a surface portion of the first semiconductor layer; and forming an inner wall of the first and second grooves on an inner wall surface of the first and second grooves. Forming an insulating film with a predetermined thickness, and then irradiating the entire surface with an oxygen ion beam And a step of making the insulating film on the first groove inner wall surface and the second groove bottom surface thicker than the insulating film on the second groove side wall surface by heat treatment. And a first conductive type semiconductor region on the well region so as to be electrically connected to the first conductive type semiconductor region.
Forming a second main electrode on the back side of the first semiconductor layer so as to be electrically connected thereto.
【００３９】この発明（請求項７）は、上記請求項６記
載の半導体装置の製造方法において、上記制御電極の形
成後、主電極を形成する前に、軽イオンをその飛程距離
が上記ウェル領域内に収まるよう１０１０〜１０１３個
／ｃｍ２の照射量で第１半導体層の第１主面側から照射
する工程と、その後低温シンターを３００〜４００゜温
度で１〜５時間行う工程とを追加して、上記絶縁膜の、
上記第２導電型のウェル領域と接する部分に固定電荷を
形成し、上記絶縁膜の、第１の溝内壁面上及び第２の溝
底面上の部分の厚膜化によるしきい値電圧の基準値に対
する増大分と、上記絶縁膜の、上記第２導電型のウェル
領域と接する部分での固定電荷の形成によるしきい値電
圧の基準値に対する減少分とが等しくなるようにしたも
のである。 [0039] The present invention (Claim 7), the above claim 6 Symbol
In the method of manufacturing a semiconductor device described above, after forming the control electrode and before forming the main electrode, light ions are irradiated at 10 10 to 10 13 / cm 2 so that the range of the light ions falls within the well region. A step of irradiating the first semiconductor layer from the first main surface side in an amount, and a step of thereafter performing low-temperature sintering at a temperature of 300 to 400 ° C. for 1 to 5 hours,
A fixed charge is applied to a portion in contact with the second conductivity type well region.
And forming the insulating film on the inner wall surface of the first groove and the second groove.
Compared to the reference value of threshold voltage by thickening the part on the bottom
And the second conductivity type well of the insulating film
Threshold charge due to the formation of fixed charge at the area in contact with the region
The amount of decrease in the pressure relative to the reference value is made equal.
It is.
【００４０】この発明（請求項８）に係る半導体装置
は、第１導電型の第１半導体層の第１主面上に第２の導
電型の第２半導体層及び第１導電型の第３半導体層を順
次形成し、該第３半導体層上に選択的に第２導電型の第
４半導体層を、該第４半導体層上に第１導電型の第５半
導体層を形成し、該第５半導体層の上部の周辺部分に選
択的に第２導電型の第６半導体層を形成してなる半導体
層構造を有するとともに、上記第４及び第５の半導体層
の側面に近接するよう形成された制御電極と、該制御電
極と上記第４及び第５の半導体層の間に形成された絶縁
膜と、上記第５及び第６の半導体層上に跨がって形成さ
れた第１の主電極と、上記第１半導体層の第２主面上に
形成された第２の主電極とを備え、上記絶縁膜を、上記
第４半導体層と接する部分の膜厚を、基準膜厚であるそ
の他の部分の膜厚に比べて薄くした構造とし、上記制御
電極に所定のオン電位の順バイアスを印加した時、上記
第５半導体層の、上記絶縁膜近傍部分にチャネルが形成
され、上記制御電極に所定のオフ電位の逆バイアスを印
加した時、上記第１導電型の第４半導体層の、該絶縁膜
近傍部分が第２導電型領域に反転するよう構成したもの
である。 In the semiconductor device according to the present invention (claim 8) , the second semiconductor layer of the second conductivity type and the third semiconductor layer of the first conductivity type are formed on the first main surface of the first semiconductor layer of the first conductivity type. Forming a semiconductor layer in sequence, selectively forming a second conductive type fourth semiconductor layer on the third semiconductor layer, and forming a first conductive type fifth semiconductor layer on the fourth semiconductor layer; It has a semiconductor layer structure in which a sixth semiconductor layer of the second conductivity type is selectively formed in a peripheral portion above the fifth semiconductor layer, and is formed so as to be close to the side surfaces of the fourth and fifth semiconductor layers. Control electrode and the control electrode
Insulation formed between the pole and the fourth and fifth semiconductor layers
And a film formed over the fifth and sixth semiconductor layers.
The first main electrode and the second main surface of the first semiconductor layer.
And a second main electrode formed, wherein the insulating film is
The thickness of the portion in contact with the fourth semiconductor layer is set to the reference thickness.
The structure is made thinner than the film thickness of other parts of
When a forward bias of a predetermined ON potential is applied to the electrode,
A channel is formed in a portion of the fifth semiconductor layer near the insulating film.
When a reverse bias of a predetermined off-potential is applied to the control electrode , the insulating film of the fourth semiconductor layer of the first conductivity type is
The vicinity portion is configured to be inverted to the second conductivity type region
It is.
【００４１】この発明（請求項９）は、上記請求項８記
載の半導体装置において、上記絶縁膜を、その上記第
３，第５及び第６半導体層と接する部分の膜厚を、その
基準膜厚であるその他の部分の膜厚に対して増大し、か
つその上記第５半導体層と接する部分にイオンを注入し
て固定電荷を形成した構造とし、上記絶縁膜の第４半導
体層と接する部分の、基準膜厚に対する薄膜化による制
御電極の容量の基準値に対する増大分を、その第３，第
５及び第６半導体層と接する部分の、基準膜厚に対する
膜厚増大による制御電極の容量の基準値に対する減少分
と等しくし、かつ上記絶縁膜の基準膜厚に対する膜厚増
大によるしきい値電圧の基準値に対する増大分を、該絶
縁膜での固定電荷の形成によるしきい値の基準値に対す
る減少分と等しくしたものである。 The present invention (claim 9) is based on claim 8 described above.
In the semiconductor device of the mounting, the insulating film, the film thickness of the portion in contact with the said third, fifth and sixth semiconductor layer, the
Increased relative to the thickness of the other portion is the reference thickness, and a structure forming a fixed charge by implanting ions into a portion in contact with the said fifth semiconductor layer, a fourth semiconductor of the insulating film
Control of the part in contact with the body layer by reducing the thickness to the reference film thickness
The increase in the capacitance of the control electrode with respect to the reference value
The portion in contact with the fifth and sixth semiconductor layers with respect to the reference film thickness
Decrease in control electrode capacitance from reference value due to increase in film thickness
And increase the thickness of the insulating film with respect to the reference film thickness.
The increase of the threshold voltage with respect to the reference value due to the large
Reference value of threshold value due to formation of fixed charge in the rim
This is equal to the decrease.
【００４２】[0042]
【作用】この発明（請求項１，２，３）においては、制
御電極と第１導電型の半導体層との間に介在する第１の
絶縁膜の所定部分の膜厚を、制御電極と第２導電型の、
チャネルが形成される領域との間に介在する第２の絶縁
膜の膜厚より薄くし、上記制御電極に逆バイアスを印加
した時、上記第１導電型の半導体層の、制御電極に近接
する部分に第２導電型の反転が形成されるようにしたか
ら、逆バイアス印加時には、上記第１の絶縁膜の、制御
電極に接する部分が第２導電型の反転領域で覆われるこ
ととなり、これにより高耐圧化を図ることができる。[Action] In the present invention (Claim 1, 2, 3), control
A first conductive layer between the control electrode and the first conductive type semiconductor layer;
The thickness of a predetermined portion of the insulating film is set between the control electrode and the second conductivity type.
Second insulation interposed between the region where the channel is formed
When the reverse bias is applied to the control electrode, the second conductive type inversion is formed in a portion of the semiconductor layer of the first conductive type adjacent to the control electrode when the reverse bias is applied to the control electrode. When a reverse bias is applied, the portion of the first insulating film that is in contact with the control electrode is covered with the inversion region of the second conductivity type, thereby increasing the breakdown voltage.
【００４３】この発明（請求項４，６）においては、上
記第２導電型のウェル領域を、その上面側の両端部間の
距離がその底面側の両端部間の距離より小さくなるよう
その側面が傾斜した断面形状とし、上記制御電極を、そ
の上面側の両端部間の距離がその底面側の両端部間の距
離より大きくなるようその側面が傾斜して、上記ウエル
領域の側面と一定間隔を隔てて対向する断面形状とした
ので、上記ウェル領域形成後、制御電極を形成する前に
全面に絶縁膜を形成すると、該絶縁膜の上記ウェル領域
上の部分が斜めに傾斜して配置されることとなり、基板
表面側に表面に対して垂直な方向から酸素イオンを注入
し熱処理を行うことにより、上記絶縁膜のウェル領域上
の部分を、従来のプロセスフローを大幅に変更すること
なく簡単に厚膜化することができる。In the present invention (claims 4 and 6), the well region of the second conductivity type is formed between both ends on the upper surface side.
Distance and its bottom surface side of <br/> to be smaller than the distance between the two ends the cross-sectional shape that its side surface is inclined, the control electrode, its
The distance between both ends on the top side is the distance between both ends on the bottom side.
Since the side surface is inclined so as to be larger than the separation and has a cross-sectional shape facing the side surface of the well region at a constant interval, an insulating film is formed on the entire surface after the formation of the well region and before the formation of the control electrode. Then, the portion of the insulating film on the well region is arranged obliquely obliquely, and oxygen ions are implanted into the substrate surface side in a direction perpendicular to the surface, and heat treatment is performed. Can be easily thickened without significantly changing the conventional process flow.
【００４４】この発明（請求項５，７）においては、上
記第２の絶縁膜の膜厚を、上記第１の絶縁膜の薄膜化に
よる制御電極の容量増大分が相殺されるよう増大し、か
つこの膜厚の増大によるしきい値電圧の変動が相殺され
るよう、上記第２の絶縁膜の、ウェル領域と接する部分
にイオンを注入して固定電荷を形成したので、ゲート絶
縁膜の膜厚に関してトレードオフの関係にあるしきい値
電圧の増大とスイッチング速度の低下とをともに抑えつ
つ、高耐圧化を図ることができる。In the present invention (claims 5 and 7) , the thickness of the second insulating film is increased so that the increase in capacitance of the control electrode due to the thinning of the first insulating film is offset, In addition, ions are implanted into portions of the second insulating film that are in contact with the well regions to form fixed charges so that fluctuations in threshold voltage due to the increase in film thickness are offset. High breakdown voltage can be achieved while suppressing both increase in threshold voltage and reduction in switching speed, which are in a trade-off relationship with respect to thickness.
【００４５】この発明（請求項８）においては、サイリ
スタ構造を第１〜第４半導体層により構成するととも
に、上記サイリスタ構造に電流を供給する経路を第５及
び第６半導体層により構成し、第４半導体層と制御電極
との間に介在する絶縁膜を、チャネルが形成される第５
半導体層と制御電極との間に介在する絶縁膜より薄く
し、上記制御電極に逆バイアスを印加した時、上記第１
導電型の第４半導体層の、制御電極に近接する部分に第
２導電型の反転層が形成されるようにしたので、ターン
オフ時には、第３半導体層から第４半導体層の反転層を
介して第５半導体層へ到る、ホールを引き抜くためのバ
イパス経路が形成されることとなり、つまりターンオフ
時の電流経路が短縮されることとなり、これにより高速
化を図ることができる。In the present invention (claim 8) , the thyristor structure is constituted by the first to fourth semiconductor layers, and the path for supplying current to the thyristor structure is constituted by the fifth and sixth semiconductor layers. 4 The insulating film interposed between the semiconductor layer and the control electrode is
When the insulating film interposed between the semiconductor layer and the control electrode is made thinner and a reverse bias is applied to the control electrode, the first
Since the second conductivity type inversion layer is formed in a portion of the fourth conductivity type semiconductor layer close to the control electrode, at the time of turn-off, the third semiconductor layer passes through the fourth semiconductor layer inversion layer. A bypass path leading to the fifth semiconductor layer for extracting holes is formed, that is, the current path at the time of turn-off is shortened, and thus the speed can be increased.
【００４６】この発明（請求項９）においては、上記第
４半導体層と接する絶縁膜の薄膜化による制御電極の容
量増大分が相殺されるよう、上記第３，第５，第６半導
体層と接する絶縁膜の厚膜を増大し、かつこの膜厚の増
大によるしきい値電圧の変動が相殺されるよう、上記第
５半導体層と接する絶縁膜にイオンを注入して固定電荷
を形成したので、しきい値電圧の増大を招くことなく上
記ターンオフ時間の短縮を図ることができる。[0046] In the invention of this (claim 9), so that the increased capacity amount of the control electrode by a thin film of the insulating film in contact with the fourth semiconductor layer are offset, the third, fifth, sixth semiconductor layer The fixed charge is formed by implanting ions into the insulating film in contact with the fifth semiconductor layer so that the thickness of the insulating film in contact with the fifth semiconductor layer is increased and the fluctuation of the threshold voltage due to the increase in the film thickness is offset. Therefore, the turn-off time can be reduced without increasing the threshold voltage.
【００４７】[0047]
【実施例】以下、この発明の実施例を図について説明す
る。 実施例１．図１はこの発明の第１の実施例による半導体
装置を説明するための図であり、Ｕ−ＭＯＳＦＥＴの断
面構造を示している。図において、１０１は本実施例の
Ｕ−ＭＯＳＦＥＴで、このＵ−ＭＯＳＦＥＴ１０１で
は、Ｎ- エピタキシャル層２と上記ゲート電極５との間
に介在している第１ゲート絶縁膜（第１の絶縁膜）６ａ
を、ウェル領域３とゲート電極５との間に介在している
第２ゲート絶縁膜（第２の絶縁膜）６ｂより薄くすると
ともに、上記Ｎ- エピタキシャル層２の、上記ゲート電
極５の底面部と近接している部分を特に濃度が低いＮ--
領域２ａとしている。なお、６ａ1 及び６ａ2 は、それ
ぞれ上記第１ゲート絶縁膜６ａの、上記ゲート電極５ａ
の側面と接する側面部、及び上記ゲート電極５ａの底面
と接する底面部であり、その他の部分は図１３に示した
従来のＵ−ＭＯＳＦＥＴ２０１と同一構成である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. Embodiment 1 FIG. FIG. 1 is a view for explaining a semiconductor device according to a first embodiment of the present invention, and shows a cross-sectional structure of a U-MOSFET. In the figure, reference numeral 101 denotes a U-MOSFET according to the present embodiment. In this U-MOSFET 101, a first gate insulating film (first insulating film) interposed between the N − epitaxial layer 2 and the gate electrode 5 described above. 6a
Is thinner than a second gate insulating film (second insulating film) 6 b interposed between the well region 3 and the gate electrode 5, and the bottom of the N − epitaxial layer 2 of the gate electrode 5 is formed. particularly concentration portion in proximity with the lower N -
The area 2a is set. 6a1 and 6a2 are the gate electrodes 5a of the first gate insulating film 6a, respectively.
And a bottom surface portion in contact with the bottom surface of the gate electrode 5a, and the other portions have the same configuration as the conventional U-MOSFET 201 shown in FIG.
【００４８】次に動作について説明する。上記Ｕ−ＭＯ
ＳＦＥＴのオフ状態において、ゲート電極９を負にバイ
アスすると、図２に示すようにＮ- エピタキシャル層
（ＭＯＳＦＥＴではＮ- ドリフト層とも言う。）２の、
薄いゲート絶縁膜側壁部６ａ1 近傍に位置する領域がＰ
型領域２ｂに反転し、また上記薄いゲート絶縁膜底面部
６ａ2 直下のＮ--領域２ａはＰ型領域２ｃに反転するこ
ととなる。これによりドリフト層２に突出したトレンチ
壁，つまり第１のゲート絶縁膜６ａは全てＰ型半導体領
域で覆われることになり、ドレイン（またはコレクタ）
電極８に逆バイアスが印加された時に発生する空乏層に
より従来トレンチ壁のコーナー部で発生していた電界集
中が緩和される。Next, the operation will be described. The above U-MO
When the gate electrode 9 is negatively biased in the off state of the SFET, as shown in FIG. 2, the N - epitaxial layer (also referred to as N - drift layer in MOSFET) 2
The region located near the thin gate insulating film side wall 6a1 is P
The N − region 2a immediately below the thin gate insulating film bottom surface 6a2 is inverted to the P type region 2c. Thereby, the trench wall protruding into the drift layer 2, that is, the first gate insulating film 6a is entirely covered with the P-type semiconductor region, and the drain (or the collector) is formed.
The depletion layer generated when a reverse bias is applied to the electrode 8 alleviates the electric field concentration that has conventionally occurred at the corner of the trench wall.
【００４９】またＵ−ＭＯＳＦＥＴのオン状態において
ゲート電極５を正にバイアスすると、図３に示すように
ウェル領域３の第２ゲート絶縁膜６ｂに近接する部分に
チャネル３ａが生じるとともに、薄いゲート絶縁膜６ａ
1 及び６ａ2 の近傍のＮ- ドリフト層２が各々Ｎ+ 半導
体領域２ｄ，Ｎ- 半導体領域２ｅに変化し、上記ソース
電極７からチャネル３ａを通過してＮ- ドリフト層２に
注入された電子が従来のトレンチ型ＭＯＳＦＥＴと同様
にＪ−ＦＥＴ効果の影響を受けることなく流れることと
なる。When the gate electrode 5 is biased positively in the ON state of the U-MOSFET, a channel 3a is formed in a portion of the well region 3 close to the second gate insulating film 6b as shown in FIG. Membrane 6a
1 and in the vicinity of the 6a2 N - drift layer 2 are each N + semiconductor regions 2d, N - changes in the semiconductor regions 2e, through the channel 3a from the source electrode 7 N - electrons injected into the drift layer 2 It flows without being affected by the J-FET effect like the conventional trench MOSFET.
【００５０】このように本実施例では、ゲート電極５と
Ｎ- エピタキシャル層２との間に介在する第１ゲート絶
縁膜６ａを、ゲート電極５とウェル領域３との間に介在
する第２ゲート絶縁膜６ｂより薄くし、上記ゲート電極
５に逆バイアスを印加した時、上記Ｎ- エピタキシャル
層２の、第１ゲート絶縁膜６ａに近接する部分に反転層
が形成されるようにしたので、逆バイアス印加時には、
上記第１ゲート絶縁膜６ａがＰ型半導体領域により覆わ
れることとなり、これにより主電極７，８間に逆バイア
スが印加された時に発生する空乏層による電界集中を緩
和することができる。As described above, in the present embodiment, the first gate insulating film 6a interposed between the gate electrode 5 and the N − epitaxial layer 2 is replaced with the second gate insulating film interposed between the gate electrode 5 and the well region 3. When a reverse bias is applied to the gate electrode 5 when the thickness is smaller than that of the insulating film 6b, an inversion layer is formed in a portion of the N − epitaxial layer 2 close to the first gate insulating film 6a. At the time of bias application,
The first gate insulating film 6a is covered with the P-type semiconductor region, whereby the electric field concentration due to the depletion layer generated when a reverse bias is applied between the main electrodes 7 and 8 can be reduced.
【００５１】実施例２．図４は本発明の第２の実施例に
よる半導体装置を説明するための図であり、Ｕ−ＭＯＳ
ＦＥＴの断面構造を示している。図において、１０２は
本実施例のＵ−ＭＯＳＦＥＴで、ここでは上記第１実施
例のＵ−ＭＯＳＦＥＴの構造において、上記Ｎ- エピタ
キシャル層２の、上記ゲート電極５の底面部及びコーナ
部に近接する部分にＰ+ 型フローティング領域９を、該
領域９によりゲート電極５ａが埋め込まれているトレン
チの底面部が覆われるように形成するとともに、第１ゲ
ート絶縁膜６ａの底面部６ａ2 を、第１ゲート絶縁膜６
ａの側面部６ａ1 より厚くし、上記ゲート電極５ａに逆
バイアスを印加した時、上記Ｎ- エピタキシャル層２
の、第１ゲート絶縁膜６ａの側壁部分６ａ1 に近接する
部分にＰ型反転層２ｂが生じて、上記Ｐ型ウェル領域３
と上記Ｐ+ 型フローティング領域９とが短絡するように
している。Embodiment 2 FIG. FIG. 4 is a diagram for explaining a semiconductor device according to a second embodiment of the present invention.
1 shows a cross-sectional structure of an FET. In the drawing, reference numeral 102 denotes a U-MOSFET according to the present embodiment. In this embodiment, in the structure of the U-MOSFET according to the first embodiment, the N − epitaxial layer 2 is close to the bottom portion and the corner portion of the gate electrode 5. A P + -type floating region 9 is formed in such a manner that the bottom of the trench in which the gate electrode 5a is buried is covered by the region 9 and the bottom 6a2 of the first gate insulating film 6a is Insulating film 6
When the reverse bias is applied to the gate electrode 5a, the thickness of the N - epitaxial layer 2 is increased.
Of the first gate insulating film 6a, a P-type inversion layer 2b is formed in a portion adjacent to the side wall portion 6a1.
And the P + -type floating region 9 is short-circuited.
【００５２】次に動作について説明する。上記Ｕ−ＭＯ
ＳＦＥＴのオフ状態において、ゲート電極９を負にバイ
アスすると、図５に示すように、Ｎ- ドリフト層２の、
薄いゲート絶縁膜側面部６ａ1 近傍の部分２ｂがＮ- 型
からＰ型に反転して、Ｐ型ウェル領域３とＰ型フローテ
ィング領域９が上記反転領域２ｂにより短絡する。これ
によりドリフト層２に突出したトレンチ壁，つまり第１
ゲート絶縁膜６ａは全てＰ型半導体領域で覆われること
になり、ドレイン（またはコレクタ）電極８に逆バイア
スが印加された時に発生する空乏層により従来トレンチ
壁のコーナー部で発生していた電界集中が緩和される。Next, the operation will be described. The above U-MO
In the off state of the SFET, when biasing the gate electrode 9 in the negative, as shown in FIG. 5, N - drift layer 2,
The portion 2b near the thin gate insulating film side surface 6a1 is inverted from N - type to P-type, and the P-type well region 3 and the P-type floating region 9 are short-circuited by the inverted region 2b. As a result, the trench wall protruding into the drift layer 2, that is, the first
The gate insulating film 6a is entirely covered with the P-type semiconductor region, and the electric field concentration that has conventionally occurred at the corner of the trench wall due to the depletion layer generated when a reverse bias is applied to the drain (or collector) electrode 8 Is alleviated.
【００５３】またＵ−ＭＯＳＦＥＴのオン状態において
ゲート電極５を正にバイアスすると、図６に示すように
ウェル領域３の第２の絶縁膜６ｂに近接する部分にチャ
ネル３ａが生じるとともに、Ｎ- ドリフト層２のゲート
絶縁膜側壁部分６ａ1 近傍がＮ+ 半導体領域２ｄに変化
し、上記チャネル３ａを通過してきた電子がＪＦＥＴ効
果の影響を受けることなくＮ- ドリフト層２に注入する
こととなる。[0053] Further, when positively biased to the gate electrode 5 in the on-state of the U-MOSFET, with the channel 3a is generated in the portion close to the second insulating film 6b of the well region 3, as shown in FIG. 6, N - drift The vicinity of the side wall portion 6a1 of the gate insulating film of the layer 2 changes to the N + semiconductor region 2d, and the electrons passing through the channel 3a are injected into the N − drift layer 2 without being affected by the JFET effect.
【００５４】この実施例においても、上記第１実施例と
同様、逆バイアス印加時には、上記第１ゲート絶縁膜６
ａがＰ型半導体領域により覆われることとなり、これに
より主電極７，８間に逆バイアスが印加された時に発生
する空乏層による電界集中を緩和することができる効果
がある。In this embodiment, as in the first embodiment, when the reverse bias is applied, the first gate insulating film 6
Since a is covered with the P-type semiconductor region, there is an effect that the electric field concentration caused by the depletion layer generated when a reverse bias is applied between the main electrodes 7 and 8 can be reduced.
【００５５】実施例３．図７は本発明の第３の実施例に
よる半導体装置を説明するための図であり、図におい
て、１０３は本実施例のＵ−ＭＯＳＦＥＴで、ここでは
上記第２の実施例のＵ−ＭＯＳＦＥＴの構造において、
上記ウェル領域３を、断面台形形状の領域３３とし、上
記ゲート電極５に代えて、その上半部分を断面逆台形形
状としたゲート電極３５を用いており、ここでは上記ウ
ェル領域３３とゲート電極３５との間の上記第２ゲート
絶縁膜６ｂは斜めに傾斜している。なお３４は上記断面
台形形状のウェル領域３３上部の周辺部分に形成された
Ｎ+ 領域である。Embodiment 3 FIG. FIG. 7 is a view for explaining a semiconductor device according to a third embodiment of the present invention. In the figure, reference numeral 103 denotes a U-MOSFET according to the present embodiment. In structure
The well region 3 is a region 33 having a trapezoidal cross section. Instead of the gate electrode 5, a gate electrode 35 having an upper half portion having an inverted trapezoidal cross section is used. The second gate insulating film 6b between the first gate insulating film 35 and the second gate insulating film 35 is inclined. Reference numeral 34 denotes an N + region formed in a peripheral portion above the well region 33 having the trapezoidal cross section.
【００５６】このような構成の第３の実施例のＵ−ＭＯ
ＳＦＥＴにおいても、オン時及びオフ時の動作について
は上記第２実施例と同様である。The U-MO of the third embodiment having such a configuration is described.
The ON and OFF operations of the SFET are the same as those of the second embodiment.
【００５７】次に製造方法について説明する。まず、Ｎ
+ 半導体基板１上にＮ- エピタキシャル層２を形成し、
Ｐ型半導体層を形成し、さらに該Ｐ型半導体層内に選択
的にＮ+ 半導体層を形成した後、該Ｎ型及びＰ型半導体
層を貫通して上記エピタキシャル層２に達する、傾斜し
た側壁を有する断面Ｖ字型溝１０３ａを形成する。これ
により上記Ｐ型ウェル領域３３が上記Ｎ- エピタキシャ
ル層２上に選択的に形成される（図８(a) ）。Next, the manufacturing method will be described. First, N
+ Forming an N − epitaxial layer 2 on a semiconductor substrate 1,
After forming a P-type semiconductor layer and further selectively forming an N + semiconductor layer in the P-type semiconductor layer, an inclined side wall penetrating the N-type and P-type semiconductor layers and reaching the epitaxial layer 2 A V-shaped groove 103a having a cross section is formed. Thus, the P-type well region 33 is selectively formed on the N - epitaxial layer 2 (FIG. 8A).
【００５８】次に上記半導体基板表面側にレジスト３１
を上記Ｎ- エピタキシャル層２が露出するよう形成し
（図８(b) ）、該レジスト３１をマスクとして上記Ｎ-
エピタキシャル層２を異方性エッチングして、垂直な側
壁を有するトレンチ（溝）１０３ｂを形成する（図８
(c) ）。Next, a resist 31 is formed on the surface of the semiconductor substrate.
The N - said N formed as an epitaxial layer 2 is exposed (FIG. 8 (b)), the resist 31 as a mask -
The epitaxial layer 2 is anisotropically etched to form a trench 103b having vertical side walls (FIG. 8).
(c)).
【００５９】続いて上記レジスト３１を除去した後、Ｖ
字溝１０３ａの斜面、トレンチ溝１３ｂ表面を含む半導
体基板の表面側を酸化して酸化膜３６を形成し（図８
(d) ）、半導体基板の表面側に酸素イオン３３を基板１
０に対して垂直な方向から照射すると、上記酸化膜３６
の、トレンチ１０３ｂの側壁部を除く部分のみに注入さ
れる。これにより上記ウェル領域３３の表面の水平部分
及び傾斜部分にはイオン注入領域３７ａが、また上記ト
レンチの底面部にはイオン注入領域３７ｂが形成される
（図８(e) ）。Subsequently, after removing the resist 31, V
The oxide film 36 is formed by oxidizing the surface of the semiconductor substrate including the slope of the groove 103a and the surface of the trench 13b (FIG. 8).
(d)) Oxygen ions 33 are applied to the substrate 1 on the front side of the semiconductor substrate.
When irradiated from a direction perpendicular to 0, the oxide film 36
Is implanted only into the portion excluding the side wall of the trench 103b. As a result, an ion-implanted region 37a is formed on the horizontal and inclined portions of the surface of the well region 33, and an ion-implanted region 37b is formed on the bottom of the trench (FIG. 8E).
【００６０】その後、１２００〜１３００℃程度の適当
な熱処理を施し、これにより上記酸化膜３６の、トレン
チ１０３ｂの側壁部を除く部分を厚くし、上記第２ゲー
ト酸化膜６ｂ及び第１ゲート酸化膜６ａの底面部分６ａ
2 を形成する（図８(f) ）。Thereafter, an appropriate heat treatment at about 1200 to 1300 ° C. is performed, thereby increasing the thickness of the oxide film 36 except for the side wall of the trench 103b, and forming the second gate oxide film 6b and the first gate oxide film. 6a bottom part 6a
2 is formed (FIG. 8 (f)).
【００６１】その後は、図示していないが、上記溝１０
３ｂ及び１０３ａ内にゲート電極５を埋め込み、半導体
基板の表面側及び裏面側に主電極を形成して、図７に示
すＵ−ＭＯＳＦＥＴ１０３を形成する。Thereafter, although not shown, the groove 10
The gate electrode 5 is buried in 3b and 103a, and the main electrodes are formed on the front side and the back side of the semiconductor substrate, thereby forming the U-MOSFET 103 shown in FIG.
【００６２】このような構成の第３の実施例では、Ｐ型
ウェル領域３３を断面台形形状とし、ゲート電極３５の
上半分を該ウェル領域３３の形状に合った断面逆台形形
状としたので、Ｐ型ウェル領域３３の形成後全面に絶縁
膜３６を形成すると、該絶縁膜３６の、上記ウェル領域
３３側面上の部分が斜めに傾斜して配置されることとな
り、その後基板表面側に表面に対して垂直な方向から酸
素イオンを注入し、熱処理を施すことにより、上記絶縁
膜３６の、上記ウェル領域側面上の部分を従来のプロセ
スフローを大幅に変更することなく簡単に厚膜化するこ
とができる。つまり上記第１ゲート絶縁膜６ａの底面部
分６ａ2 及び第２ゲート絶縁膜６ｂの厚膜化を簡単に行
うことができる。In the third embodiment having such a structure, the P-type well region 33 has a trapezoidal cross section, and the upper half of the gate electrode 35 has an inverted trapezoidal cross section which matches the shape of the well region 33. When the insulating film 36 is formed on the entire surface after the formation of the P-type well region 33, the portion of the insulating film 36 on the side surface of the well region 33 is arranged obliquely and thereafter, the surface is formed on the substrate surface side. Oxygen ions are implanted in a direction perpendicular to the direction, and a heat treatment is performed to easily increase the thickness of the portion of the insulating film 36 on the side surface of the well region without significantly changing the conventional process flow. Can be. In other words, the thickness of the bottom surface portion 6a2 of the first gate insulating film 6a and the thickness of the second gate insulating film 6b can be easily increased.
【００６３】実施例４．図９はこの発明の第４の実施例
による半導体装置を説明するための図であり、サイリス
タ素子の断面構造を示している。図において、１０４は
本実施例のサイリスタ素子で、この素子１０４では、ゲ
ート絶縁膜４６を、そのＮ+ 拡散領域１２と接する部分
４６ｂを他の部分４６ａ及び４６ｃに比べて薄くした構
造とし、ゲート電極１５に逆バイアスを印加した時、上
記Ｎ+ 拡散領域１２の、上記絶縁膜４６の薄膜化部分４
６ｂと接する部分にＰ型反転層１２ａが形成されるよう
にしている。なおここで４６ａは上記絶縁膜４６のＰ型
拡散領域１３と接する部分、４６ｃは上記絶縁膜４６
の、Ｐ型拡散領域１１ａと接する部分であり、その他の
部分は図１６に示した従来のサイリスタ素子２０２と同
一構成である。Embodiment 4 FIG. FIG. 9 is a view for explaining a semiconductor device according to a fourth embodiment of the present invention, and shows a cross-sectional structure of a thyristor element. In the figure, reference numeral 104 denotes a thyristor element of the present embodiment. In this element 104, the gate insulating film 46 has a structure in which a portion 46b in contact with the N + diffusion region 12 is thinner than other portions 46a and 46c, When a reverse bias is applied to the electrode 15, the thinned portion 4 of the insulating film 46 of the N + diffusion region 12 is formed.
The P-type inversion layer 12a is formed in a portion in contact with 6b. Here, 46a is a portion of the insulating film 46 in contact with the P-type diffusion region 13, and 46c is a portion of the insulating film 46.
Are in contact with the P-type diffusion region 11a, and the other portions have the same configuration as the conventional thyristor element 202 shown in FIG.
【００６４】次に動作について説明する。オフ時の動作
において、この構造特有の効果が認められる。即ち、オ
ン状態においてゲート電極１５に負の電圧を印加して電
子電流を遮断すると、サイリスタ領域に残っていた電子
キャリアはターンオフの初期に正孔キャリアと再結合し
て消滅する。この時余剰の正孔キャリアはＰ型拡散領域
１１ａに注入され、Ｐ型拡散領域１１ｂを通って、カソ
ード電極１７へ吸収されるが、Ｎ型領域１２の絶縁膜４
６ｂ近傍の部分にはＰ型反転層１２ａが生じ、Ｐ型半導
体領域１３とＰ型領域１１ａが短絡されることとなり、
これにより正孔キャリアの一部がこの経路を通ってカソ
ード電極１７へ吸収される。この結果全体として電流経
路が短縮され、スイッチング時間が短縮される。Next, the operation will be described. The effect peculiar to this structure is recognized in the off-state operation. That is, when a negative voltage is applied to the gate electrode 15 in the ON state to cut off the electron current, the electron carriers remaining in the thyristor region recombine with the hole carriers in the early stage of turn-off and disappear. At this time, excess hole carriers are injected into the P-type diffusion region 11a, and are absorbed by the cathode electrode 17 through the P-type diffusion region 11b.
6b, a P-type inversion layer 12a is formed in the vicinity, and the P-type semiconductor region 13 and the P-type region 11a are short-circuited.
Thereby, a part of the hole carriers is absorbed by the cathode electrode 17 through this path. As a result, the current path is shortened as a whole, and the switching time is shortened.
【００６５】このように本実施例では、トレンチゲート
型ＥＳＴのゲート絶縁膜の一部を薄膜化し、ゲート電極
に逆バイアスを印加した時に上記ゲート絶縁膜の一部に
近接する半導体領域に反転層が形成されるようにしたの
で、ターンオフ時に上記反転層により、正孔電流を引き
抜くためのバイパス経路が形成され、ターンオフ時間の
短縮を図ることができるという効果がある。As described above, in this embodiment, a part of the gate insulating film of the trench gate type EST is thinned, and when a reverse bias is applied to the gate electrode, the inversion layer is formed in the semiconductor region adjacent to the part of the gate insulating film. Is formed, a bypass path for extracting a hole current is formed by the inversion layer at the time of turn-off, and there is an effect that the turn-off time can be shortened.
【００６６】なお、上記第１〜第４の実施例で示したよ
うにトレンチゲート絶縁膜の一部を薄膜化することによ
って耐圧の向上，ターンオフ時間の短縮等を図ったもの
を示したが、一方でこのゲート絶縁膜の薄膜化に伴い問
題点も発生する。As described in the first to fourth embodiments, the breakdown voltage is improved, the turn-off time is shortened by reducing a part of the trench gate insulating film. On the other hand, a problem arises with the thinning of the gate insulating film.
【００６７】すなわち、ゲート絶縁膜の薄膜化に伴って
ゲート容量が増大することとなり、このゲート容量の増
加によるスイッチング時間の遅れやミラー効果が生ずる
という問題があり、上記ミラー効果により、ターンオフ
時に電流の減少変化がスムーズに行われず、電流値が一
定レベルを保持し減少しない期間が生じてしまう。That is, as the gate insulating film becomes thinner, the gate capacitance increases, and there is a problem that the switching time is delayed and the Miller effect occurs due to the increase in the gate capacitance. Is not smoothly changed, and a period occurs in which the current value is maintained at a constant level and does not decrease.
【００６８】図１０(a) は第１あるいは第２の実施例の
構造を用いて、オフ（ターンオフ）時にゲート容量とし
て寄与する成分を説明するための図である。ここで全ゲ
ート容量をＣg とすると、 １／Ｃg ＝１／Ｃox＋１／Ｃs ＝１／（Ｃoxa ＋Ｃoxb ＋Ｃoxc ）＋１／Ｃs で表わされる。ここで、Ｃs は空乏層（Depletion laye
r)中の容量、Ｃoxは絶縁膜中の総容量である。FIG. 10A is a diagram for explaining a component that contributes as a gate capacitance at the time of off (turn off) using the structure of the first or second embodiment. Here, assuming that the total gate capacitance is Cg, it is expressed by 1 / Cg = 1 / Cox + 1 / Cs = 1 / (Coxa + Coxb + Coxc) + 1 / Cs. Here, Cs is the depletion layer (Depletion laye
The capacitance in r), Cox, is the total capacitance in the insulating film.
【００６９】また、図１０(b) はオフ時の電流・電圧波
形を示しており、この図において、オフ時間ｔf は次式
によって表わされる。 ｔf ＝Ｒg ×Ｃg ×ｌn （Ｉl ／（ｇｍ・Ｖt ）＋１） Ｒg ：ゲート抵抗(Gate Resistance) ｇｍ：相互コンダクタンス（ｄＩd ／ｄＶg ） Ｉl ：負荷電流（Load current） Ｖt ：しきい値電圧（Threshold Voltage) 上式から明らかなように、Ｃg の増加によってｔf は直
接影響を受けて増加する。従って、第１〜第４の実施例
では、オフ（ターンオフ）スイッチングに悪影響が及ば
ないようにするには、Ｃg の増加を抑える必要がある。[0069] Further, FIG. 10 (b) shows the current and voltage waveforms at the time of off, in this figure, off-time t f is represented by the following equation. t f = Rg × Cg × ln (Il / (gm · Vt) +1) Rg: gate resistance (Gate Resistance) gm: transconductance (dId / dVg) Il: load current (Load current) Vt: threshold voltage ( Threshold Voltage) As is apparent from the above equation, tf is directly affected by the increase in Cg and increases. Therefore, in the first to fourth embodiments, it is necessary to suppress an increase in Cg so as not to adversely affect off (turn-off) switching.
【００７０】実施例５．図１１は本発明の第５の実施例
による半導体装置を説明するための図であり、図におい
て、１０５は本実施例のＵ−ＭＯＳＦＥＴで、ここでは
上記第２の実施例のＵ−ＭＯＳＦＥＴの構造において、
第１ゲート絶縁膜６ａの側壁部分６ａ1の薄膜化による
ゲート容量の増大分が相殺されるよう、第１ゲート絶縁
膜の底面部分６ａ2 及び第２ゲート絶縁膜６ｂの膜厚を
増大し、かつこの膜厚増大によるしきい値電圧の変動が
相殺されるよう、上記第２ゲート絶縁膜６ｂの、ウェル
領域と接する部分にイオンを注入して固定電荷を形成し
ている。Embodiment 5 FIG. FIG. 11 is a view for explaining a semiconductor device according to a fifth embodiment of the present invention. In the figure, reference numeral 105 denotes a U-MOSFET of the present embodiment. In structure
The thickness of the bottom portion 6a2 of the first gate insulating film and the thickness of the second gate insulating film 6b are increased so that the increase in gate capacitance due to the thinning of the side wall portion 6a1 of the first gate insulating film 6a is offset. Ions are implanted into a portion of the second gate insulating film 6b in contact with the well region to form fixed charges so that a change in threshold voltage due to an increase in film thickness is offset.
【００７１】つまり、Ｎ- ドリフト層２に接するトレン
チゲート絶縁膜の側壁部６ａ1 を薄膜化すると、この部
分での容量成分Ｃoxb は増加する。この増加分を相殺す
べく、第１ゲート絶縁膜の底面部分６ａ2 及び第２ゲー
ト絶縁膜６ｂの膜厚を厚くしてこれらの部分での容量成
分Ｃoxc ，Ｃoxa を低下させているが、第２ゲート絶縁
膜６ｂの厚膜化によってしきい値電圧が増加してしま
う。このためしきい値電圧を最適化するために、例えば
プロトン等の軽イオン４０を表面側より、飛程を上記第
２ゲート絶縁膜のウェル領域と接する部分内に収まるよ
うに照射して、同膜中に選択的に正の固定電荷を導入し
ている。なお、このイオン照射はゲート電極５に正の電
圧を印加しながら行うと、より少ない照射量で同様の効
果が得られ、Ｐウェル領域３に与える損傷を最低限に抑
えることができる。That is, when the side wall 6a1 of the trench gate insulating film in contact with the N - drift layer 2 is made thinner, the capacitance component Coxb at this portion increases. To offset this increase, the thicknesses of the bottom surface portion 6a2 of the first gate insulating film and the second gate insulating film 6b are increased to reduce the capacitance components Coxc and Coxa in these portions. The threshold voltage is increased by increasing the thickness of the gate insulating film 6b. Therefore, in order to optimize the threshold voltage, for example, light ions 40 such as protons are irradiated from the surface side so that the range falls within a portion in contact with the well region of the second gate insulating film. Positive fixed charges are selectively introduced into the film. If this ion irradiation is performed while applying a positive voltage to the gate electrode 5, a similar effect can be obtained with a smaller irradiation amount, and damage to the P-well region 3 can be minimized.
【００７２】なお、上記第１〜第３及び第５の実施例で
は、トレンチ型パワーデバイスとして、Ｕ−ＭＯＳＦＥ
Ｔを例に挙げて説明したが、これは、上記Ｕ−ＭＯＳＦ
ＥＴの構造において、Ｎ+ 半導体基板をＰ+ 半導体基板
に置き換えた素子構造のＩＧＢＴでもよく、この場合も
上記各実施例と同様の効果が得られる。In the first to third and fifth embodiments, the U-MOSFE is used as a trench power device.
T has been described as an example, this is because the above-mentioned U-MOSF
In the ET structure, an IGBT having an element structure in which an N + semiconductor substrate is replaced with a P + semiconductor substrate may be used. In this case, the same effects as those of the above embodiments can be obtained.
【００７３】この実施例では、第１ゲート絶縁膜の底面
部分６ａ2 及び第２ゲート絶縁膜６ｂの膜厚を増大した
ので、第１ゲート絶縁膜６ａの側壁部分６ａ1 の薄膜化
によるゲート容量の増大分が抑制されることとなり、ま
た上記第２ゲート絶縁膜６ｂの、ウェル領域と接する部
分にイオンを注入して固定電荷を形成したので、上記膜
厚増大によるしきい値電圧の変動が抑制されることとな
る。これによりしきい値電圧の最適化を図りつつ、上記
オフ時間を短縮することができる。In this embodiment, since the bottom portion 6a2 of the first gate insulating film and the thickness of the second gate insulating film 6b are increased, the gate capacitance is increased by reducing the thickness of the side wall portion 6a1 of the first gate insulating film 6a. In addition, since fixed charges are formed by implanting ions into a portion of the second gate insulating film 6b that is in contact with the well region, the fluctuation of the threshold voltage due to the increase in the film thickness is suppressed. The Rukoto. This makes it possible to shorten the off-time while optimizing the threshold voltage.
【００７４】実施例６．図１２は本発明の第６の実施例
による半導体装置を説明するための図であり、図におい
て、１０６は本実施例のＥＳＴサイリスタ素子で、これ
は、上記第４実施例のＥＳＴサイリスタにおいて、上記
ゲート絶縁膜４６の、Ｎ型領域１２と接する部分４６ｂ
の薄膜化によるゲート電極の容量増大分が相殺されるよ
う、上記絶縁膜４６の、Ｐ型領域１１ａ及びＰウェル領
域１３と接する部分４６ｃ，４６ａの膜厚を増大し、か
つこの膜厚増大によるしきい値電圧の変動が相殺される
よう、絶縁膜４６のチャネル対応部分４６ａにイオンを
注入して固定電荷を形成したものである。この場合第５
の実施例と同様、しきい値電圧の最適化を図りつつ、タ
ーンオフ時間を短縮することができる。Embodiment 6 FIG. FIG. 12 is a view for explaining a semiconductor device according to a sixth embodiment of the present invention. In the figure, reference numeral 106 denotes an EST thyristor element of the present embodiment, which is an EST thyristor of the fourth embodiment. Portion 46b of gate insulating film 46 in contact with N-type region 12
The thickness of the portions 46c and 46a of the insulating film 46 that are in contact with the P-type region 11a and the P-well region 13 is increased so that the increase in the capacitance of the gate electrode due to the reduction in the thickness of the gate electrode is offset. The fixed charges are formed by implanting ions into a portion 46a corresponding to the channel of the insulating film 46 so as to cancel the fluctuation of the threshold voltage. In this case the fifth
As in the embodiment, the turn-off time can be reduced while optimizing the threshold voltage.
【００７５】[0075]
【発明の効果】この発明（請求項１，２，３）に係る半
導体装置によれば、制御電極と第１導電型の半導体層と
の間に介在する第１の絶縁膜の所定部分の膜厚を、制御
電極と第２導電型の、チャネルが形成される領域との間
に介在する第２の絶縁膜の膜厚より薄くし、上記制御電
極に逆バイアスを印加した時、上記第１導電型の半導体
層の、制御電極に近接する部分に第２導電型の反転が形
成されるようにしたので、逆バイアス印加時には、上記
第１の絶縁膜の、制御電極に接する部分が第２導電型の
反転領域で覆われることとなり、これにより高耐圧化を
図ることができる効果がある。According to the semiconductor device according to the embodiments of the Invention This invention (claim 1, 2, 3), a control electrode and the semiconductor layer of the first conductivity type
Controlling the thickness of a predetermined portion of the first insulating film interposed therebetween.
Between the electrode and the region of the second conductivity type where the channel is formed
When a reverse bias is applied to the control electrode, the second conductivity type is inverted in a portion of the semiconductor layer of the first conductivity type close to the control electrode when a reverse bias is applied to the control electrode. As a result, when a reverse bias is applied, a portion of the first insulating film that is in contact with the control electrode is covered with the inversion region of the second conductivity type, thereby increasing the breakdown voltage. effective.
【００７６】この発明（請求項４，６）によれば、上記
第２導電型のウエル領域を、その上面側の両端部間の距
離がその底面側の両端部間の距離より小さくなるようそ
の側面が傾斜した断面形状とし、上記制御電極を、その
上面側の両端部間の距離がその底面側の両端部間の距離
より大きくなるようその側面が傾斜して、上記ウエル領
域の側面と一定間隔を隔てて対向する断面形状としたの
で、上記ウェル領域形成後、制御電極を形成する前に全
面に絶縁膜を形成すると、該絶縁膜の上記ウェル領域上
の部分が斜めに傾斜して配置されることとなり、その後
基板表面側に表面に対して垂直な方向から酸素イオンを
注入し熱処理を行うことにより、上記絶縁膜のウェル領
域上の部分を、従来のプロセスフローを大幅に変更する
ことなく簡単に厚膜化することができる効果がある。According to the present invention (claims 4 and 6), the well region of the second conductivity type is provided with a distance between both ends on the upper surface side.
Away is a cross-sectional shape that its <br/> side of inclined to be smaller than the distance between the ends of its bottom side, the control electrode, the
The distance between both ends on the top side is the distance between both ends on the bottom side
Since the side surface is inclined so as to be larger and has a cross-sectional shape facing the side surface of the well region at a constant interval, an insulating film is formed over the entire surface after the well region is formed and before the control electrode is formed. The portion of the insulating film above the well region is disposed obliquely and thereafter, oxygen ions are implanted into the substrate surface side from a direction perpendicular to the surface and heat treatment is performed. The effect is that the thickness of the portion on the well region can be easily increased without significantly changing the conventional process flow.
【００７７】この発明（請求項５，７）によれば、上記
第２の絶縁膜の膜厚を、上記第１の絶縁膜の薄膜化によ
る制御電極の容量増大分が相殺されるよう増大し、かつ
この膜厚の増大によるしきい値電圧の変動が相殺される
よう、上記第２の絶縁膜の、ウェル領域と接する部分に
イオンを注入して固定電荷を形成したので、ゲート絶縁
膜の膜厚に関してトレードオフの関係にある、しきい値
電圧の増大とスイッチング速度の低下とをともに抑えつ
つ、高耐圧化を図ることができる。 [0077] According to the invention this (claim 5,7), increases so that the thickness of the second insulating film, the capacitance increment of the first control electrode by thinning the insulating film is offset In addition, ions are implanted into a portion of the second insulating film which is in contact with the well region to form fixed charges so that a change in threshold voltage due to the increase in the film thickness is offset. a thickness in a trade-off relationship with respect to, while both suppressing and lowering of increasing the switching speed of the threshold voltage, Ru can achieve high breakdown voltage.
【００７８】この発明（請求項８）に係る半導体装置に
よれば、サイリスタ構造を第１〜第４半導体層により構
成するとともに、上記サイリスタ構造に電流を供給する
経路を第５及び第６半導体層により構成し、第４半導体
層と制御電極との間に介在する絶縁膜を、チャネルが形
成される第５半導体層と制御電極との間に介在する絶縁
膜より薄くし、上記制御電極に逆バイアスを印加した
時、上記第１導電型の第４半導体層の、制御電極に近接
する部分に第２導電型の反転層が形成されるようにした
ので、ターンオフ時には、第３半導体層から第４半導体
層の反転層を介して第５半導体層へ到る、ホールを引き
抜くためのバイパス経路が形成されることとなり、つま
りターンオフ時の電流経路が短縮されることとなり、こ
れにより高速化を図ることができる効果がある。According to the semiconductor device of the present invention (claim 8) , the thyristor structure is constituted by the first to fourth semiconductor layers, and the paths for supplying current to the thyristor structure are provided by the fifth and sixth semiconductor layers. And the insulating film interposed between the fourth semiconductor layer and the control electrode is made thinner than the insulating film interposed between the fifth semiconductor layer in which the channel is formed and the control electrode, and is opposite to the control electrode. When a bias is applied, an inversion layer of the second conductivity type is formed in a portion of the fourth semiconductor layer of the first conductivity type close to the control electrode. Holes are drawn to the fifth semiconductor layer through the inversion layer of the four semiconductor layers.
A bypass path for disconnection is formed, that is, a current path at the time of turn-off is shortened, which has the effect of increasing the speed.
【００７９】この発明（請求項９）によれば、上記第４
半導体層と接する絶縁膜の薄膜化による制御電極の容量
増大分が相殺されるよう、上記第３，第５，第６半導体
層と接する絶縁膜の厚膜を増大し、かつこの膜厚の増大
によるしきい値電圧の変動が相殺されるよう、上記第５
半導体層と接する絶縁膜にイオンを注入して固定電荷を
形成したので、しきい値電圧の増大を招くことなく上記
ターンオフ時間の短縮を図ることができる。 [0079] According to the invention this (claim 9), the fourth
The thickness of the insulating film in contact with the third, fifth, and sixth semiconductor layers is increased so that the increase in the capacity of the control electrode due to the thinning of the insulating film in contact with the semiconductor layer is offset, and the increase in the thickness is increased. In order to cancel the fluctuation of the threshold voltage due to
Since the formation of the fixed charges by injecting ions into the insulating film in contact with the semiconductor layer, Ru can be shortened the turn-off time without increasing the threshold voltage.
【図１】本発明の第１の実施例による半導体装置として
Ｕ−ＭＯＳＦＥＴを示す断面図である。FIG. 1 is a sectional view showing a U-MOSFET as a semiconductor device according to a first embodiment of the present invention.
【図２】上記Ｕ−ＭＯＳＦＥＴのオフ状態においてゲー
ト電極を負にバイアスした時の様子を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a state where a gate electrode is negatively biased in an off state of the U-MOSFET.
【図３】上記Ｕ−ＭＯＳＦＥＴのオン状態においてゲー
ト電極を正にバイアスした時の様子を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a state where a gate electrode is positively biased in an ON state of the U-MOSFET.
【図４】本発明の第２の実施例による半導体装置として
Ｕ−ＭＯＳＦＥＴを示す断面図である。FIG. 4 is a sectional view showing a U-MOSFET as a semiconductor device according to a second embodiment of the present invention.
【図５】上記Ｕ−ＭＯＳＦＥＴのオフ状態においてゲー
ト電極を負にバイアスした時の様子を示す断面図であ
る。FIG. 5 is a cross-sectional view showing a state where a gate electrode is negatively biased in the off state of the U-MOSFET.
【図６】上記Ｕ−ＭＯＳＦＥＴのオン状態においてゲー
ト電極を正にバイアスした時の様子を示す断面図であ
る。FIG. 6 is a cross-sectional view showing a state where a gate electrode is positively biased in the ON state of the U-MOSFET.
【図７】本発明の第３の実施例による半導体装置として
Ｕ−ＭＯＳＦＥＴを示す断面図である。FIG. 7 is a sectional view showing a U-MOSFET as a semiconductor device according to a third embodiment of the present invention.
【図８】上記第３実施例装置の製造フローを示す断面図
である。FIG. 8 is a sectional view showing a manufacturing flow of the device of the third embodiment.
【図９】本発明の第４の実施例による半導体装置として
サイリスタを示す断面図である。FIG. 9 is a sectional view showing a thyristor as a semiconductor device according to a fourth embodiment of the present invention.
【図１０】ゲート容量及びターンオフ時の電流−電圧特
性を示す図である。FIG. 10 is a diagram showing gate capacitance and current-voltage characteristics at turn-off.
【図１１】本発明の第５の実施例による半導体装置とし
てＵ−ＭＯＳＦＥＴを示す断面図である。FIG. 11 is a sectional view showing a U-MOSFET as a semiconductor device according to a fifth embodiment of the present invention.
【図１２】本発明の第６の実施例による半導体装置とし
てサイリスタを示す断面図である。FIG. 12 is a sectional view showing a thyristor as a semiconductor device according to a sixth embodiment of the present invention.
【図１３】従来のパワーデバイスとしてＵ−ＭＯＳＦＥ
Ｔの構造を示す図である。FIG. 13 shows U-MOSFE as a conventional power device.
FIG. 3 is a diagram showing the structure of T.
【図１４】上記ＭＯＳＦＥＴの構造におけるシュミレー
ションによる電界集中の様子を示す図である。FIG. 14 is a diagram showing a state of electric field concentration by simulation in the structure of the MOSFET.
【図１５】上記Ｕ−ＭＯＳＦＥＴにおける耐圧低下に対
する対策を説明するための図である。FIG. 15 is a diagram for explaining a countermeasure against a decrease in withstand voltage in the U-MOSFET.
【図１６】従来のサイリスタの構造の一例を示す断面図
である。FIG. 16 is a sectional view showing an example of the structure of a conventional thyristor.
【図１７】上記サイリスタの動作を説明するための断面
図である。FIG. 17 is a cross-sectional view for explaining the operation of the thyristor.
【図１８】従来のパワーデバイスとしてＤ−ＭＯＳＦＥ
Ｔの構造を示す断面図である。FIG. 18 shows a D-MOSFE as a conventional power device.
It is sectional drawing which shows the structure of T.
１，１０ Ｐ型半導体基板 ２，２０ Ｎ- エピタキシャル層 ２ａ Ｎ--拡散領域 ３ Ｐウェル領域 ４ Ｎ+ 拡散領域 ５，１５ ゲート電極 ６ａ 第１ゲート絶縁膜 ６ａ1 第１ゲート絶縁膜側面部 ６ａ2 第１ゲート絶縁膜底面部 ６ｂ 第２ゲート絶縁膜 ７ ソース電極 ８ ドレイン電極 ９ Ｐ+ フローティング領域 １１ａ，１３ Ｐ型半導体領域 １１ｂ Ｐ+ 型半導体領域 １２，１４ Ｎ+ 型半導体領域 １２ａ チャネル領域 １６ａ 絶縁膜 １７ コレクタ電極 １８ アノード電極 ４６ ゲート絶縁膜 ４６ａ ゲート絶縁膜厚膜部分 ４６ｂ ゲート絶縁膜薄膜部 ４６ｃ ゲート絶縁膜底面部 １０１〜１０３，１０５ 第１〜第３及び第５の実施例
によるＵ−ＭＯＳＦＥＴ素子 １０４，１０６ 第４及び第６の実施例によるＥＳＴ素
子1,10 P-type semiconductor substrate 2,20 N − epitaxial layer 2a N − diffusion region 3 P well region 4 N + diffusion region 5,15 Gate electrode 6a First gate insulating film 6a1 First gate insulating film side surface 6a2 1 bottom surface of gate insulating film 6b second gate insulating film 7 source electrode 8 drain electrode 9 P + floating region 11a, 13 P type semiconductor region 11b P + type semiconductor region 12, 14 N + type semiconductor region 12a Channel region 16a Insulating film Reference Signs List 17 collector electrode 18 anode electrode 46 gate insulating film 46a gate insulating film portion 46b gate insulating thin film portion 46c gate insulating film bottom portion 101-103,105 U-MOSFET device according to first to third and fifth embodiments 104, 106 EST device according to fourth and sixth embodiments
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 29/78 ６５５Ａ ──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H01L 29/78 655A
Claims (9)
導体層と、 該半導体層の突出部の表面上に形成された第２導電型の
ウェル領域と、 該第２導電型のウエル領域の側面、及び上記半導体層の
突出部の側面に近接するよう形成された制御電極と、 該制御電極と上記半導体層との間に形成された第１の絶
縁膜と、 上記制御電極と上記ウエル領域との間に形成された第２
の絶縁膜と、 該ウエル領域表面部の周辺部分に形成された第１導電型
の半導体領域と、 上記半導体層表面側に該第１導電型の半導体領域と電気
的につながるよう形成された第１の主電極と、 上記半導体層裏面側にこの半導体層と電気的につながる
よう形成された第２の主電極とを備え、 上記第１の絶縁膜の少なくとも一部をその基準膜厚に対
して薄膜化して、該第１の絶縁膜を、その膜厚が第２の
絶縁膜の膜厚より薄い薄膜部を有する構造とし、 上記制御電極に所定のオン電位の順バイアスを印加した
時、上記第２導電型のウエル領域の、該制御電極と近接
する部分にチャネルが形成され、上記制御電極に所定の
オフ電位の逆バイアスを印加した時、上記第１導電型の
半導体層における、上記第１の絶縁膜の薄膜部を介して
該制御電極に近接する領域が、第２導電型領域に反転す
るよう構成したことを特徴とする半導体装置。1. A first conductivity type semiconductor layer portion of the surface protrudes, and a second conductivity type well region made form on the surface of the protruding portion of the semiconductor layer, the second conductivity type well Side surface of the region , and the semiconductor layer
A control electrode formed to be close to the side surface of the protruding portion; a first insulating film formed between the control electrode and the semiconductor layer; and a control electrode formed between the control electrode and the well region Second
An insulating film, a first conductive type semiconductor region formed on a peripheral portion of the well region surface portion, and a first conductive type semiconductor region formed on the semiconductor layer surface side so as to be electrically connected to the first conductive type semiconductor region. A first main electrode, and a second main electrode formed on the back side of the semiconductor layer so as to be electrically connected to the semiconductor layer. At least a part of the first insulating film is formed with respect to its reference film thickness. When the first insulating film has a thin film portion whose thickness is smaller than the thickness of the second insulating film, when a forward bias of a predetermined ON potential is applied to the control electrode, A channel is formed in a portion of the well region of the second conductivity type adjacent to the control electrode, and when a reverse bias of a predetermined off-potential is applied to the control electrode, the channel in the semiconductor layer of the first conductivity type is To the control electrode via the thin film portion of the first insulating film Region contacting the semiconductor device being characterized in that configured to inverted second conductivity type region.
て上記制御電極の底面に近接する部分は、その他の部分
に比べて不純物濃度が低くなっており、 上記逆バイアスの印加時、上記半導体層の、上記制御電
極に隣接する部分には、第２導電型の反転領域が上記第
１の絶縁膜の表面を全て覆うよう形成されるようになっ
ていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a portion of the first conductivity type semiconductor layer which is close to a bottom surface of the control electrode via the first insulating film is compared with other portions. The impurity concentration is low, and when the reverse bias is applied, a second conductivity type inversion region covers the entire surface of the first insulating film in a portion of the semiconductor layer adjacent to the control electrode. A semiconductor device characterized by being formed.
て上記制御電極の底面及びその底面側端のコーナ部に近
接する部分には、第２導電型の半導体領域が形成されて
おり、 上記第１の絶縁膜の上記制御電極の側面と接する部分が
上記薄膜部となっており、 上記第１の絶縁膜の上記制御電極の底面と接する部分
は、上記薄膜部に比べて厚くなっており、 上記逆バイアスの印加時、上記半導体層の、第１の絶縁
膜に近接する第１導電型領域が第２導電型に反転して、
上記第２導電型のウエル領域と上記第２導電型の半導体
領域とが上記第２導電型反転領域により短絡されるよう
になっていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a portion of said first conductivity type semiconductor layer which is adjacent to a bottom portion of said control electrode and a corner portion at a bottom side end thereof via said first insulating film. A semiconductor region of the second conductivity type is formed, a portion of the first insulating film which is in contact with the side surface of the control electrode is the thin film portion, and the control electrode of the first insulating film is formed. The portion in contact with the bottom surface of the semiconductor layer is thicker than the thin film portion. When the reverse bias is applied, the first conductivity type region of the semiconductor layer adjacent to the first insulating film is inverted to the second conductivity type. do it,
A semiconductor device, wherein the second conductivity type well region and the second conductivity type semiconductor region are short-circuited by the second conductivity type inversion region.
の距離がその底面側の両端部間の距離より小さくなるよ
うその側面が傾斜した断面形状となっており、 上記制御電極は、その上面側の両端部間の距離がその底
面側の両端部間の距離より大きくなるようその側面が傾
斜して、上記ウエル領域の側面と一定間隔を隔てて対向
する断面形状となっており、 上記ウエル領域と上記制御電極との間には上記第２の絶
縁膜が介在していることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein said second conductivity type well region is located between both ends on the upper surface side.
Is smaller than the distance between the two ends on the bottom side.
Cormorant has a sectional shape that the side surface is inclined, the control electrode, the distance between the ends of the upper surface side thereof a bottom
The side surface is inclined so as to be larger than the distance between both end portions on the surface side, and has a cross-sectional shape facing the side surface of the well region at a fixed interval, between the well region and the control electrode. Is a semiconductor device having the second insulating film interposed therebetween.
導体装置において、 上記第２の絶縁膜は、その基準膜厚に対してその膜厚を
増大し、かつその第２導電型のウェル領域と接する部分
にイオンを注入して固定電荷を形成した構造としたもの
であり、 上記第２の絶縁膜の基準膜厚に対する膜厚増大による制
御電極の容量の基準値に対する減少分は、上記第１の絶
縁膜の基準膜厚に対する薄膜化による制御電極の容量の
基準値に対する増大分と等しく、 かつ上記第２の絶縁膜の基準膜厚に対する膜厚増大によ
るしきい値電圧の基準値に対する増大分は、上記第２の
絶縁膜での固定電荷の形成によるしきい値電圧の基準値
に対する減少分と等しくなっていることを特徴とする半
導体装置。5. The semiconductor device according to claim 1, wherein said second insulating film has a thickness that is greater than a reference thickness thereof and has a second conductivity type well. A fixed charge is formed by injecting ions into a portion in contact with the region. A decrease in the capacitance of the control electrode with respect to a reference value due to an increase in the film thickness with respect to the reference film thickness of the second insulating film is as described above. It is equal to the increase of the control electrode capacitance with respect to the reference value due to the thinning of the first insulating film with respect to the reference thickness, and the threshold voltage with respect to the reference value of the second insulating film is increased with respect to the reference thickness. A semiconductor device characterized in that the increase is equal to the decrease of the threshold voltage with respect to a reference value due to the formation of fixed charges in the second insulating film.
法において、 第１導電型の第１半導体層上に第２導電型の第２半導体
層を形成し、該第２半導体層内に第１導電型の第３半導
体層を選択的に形成する工程と、 上記第１ないし第３半導体層を選択的に除去して、上記
第２及び第３半導体層を貫通する断面逆台形形状の第１
の溝を形成するとともに、断面台形形状の第２導電型の
ウェル領域及び上記第１導電型の半導体領域を形成する
工程と、 上記第１の溝の底面部分を選択的に除去して、上記第１
半導体層の表面部分に断面長方形形状の第２の溝を形成
する工程と、 上記第１及び第２の溝の内壁面上に絶縁膜を所定の膜厚
でもって形成し、その後全面に酸素イオンビームを照射
する工程と、 熱処理により、上記第１の溝内壁面上及び第２の溝底面
上の絶縁膜を、第２の溝側壁面上の絶縁膜より厚くする
工程と、 その後制御電極を上記第１及び第２の溝内に埋め込み、
上記ウェル領域上に上記第１導電型の半導体領域と電気
的につながるよう第１の主電極を、上記第１半導体層の
裏面側にこれと電気的につながるよう第２の主電極を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。6. The method for manufacturing a semiconductor device according to claim 4, wherein a second semiconductor layer of a second conductivity type is formed on the first semiconductor layer of the first conductivity type, and a second semiconductor layer is formed in the second semiconductor layer. Selectively forming a third semiconductor layer of one conductivity type; and selectively removing the first to third semiconductor layers to form an inverted trapezoidal cross-section through the second and third semiconductor layers. 1
To form a groove in the steps of forming a second conductivity type well region and the semiconductor region of the first conductivity type of the cross-sectional surface trapezoidal, by selectively removing the bottom portion of the first groove, The first
Forming a second groove having a rectangular cross section in the surface portion of the semiconductor layer; forming an insulating film with a predetermined thickness on the inner wall surfaces of the first and second grooves; A step of irradiating a beam; a step of making the insulating film on the inner wall surface of the first groove and the bottom surface of the second groove thicker than the insulating film on the side wall surface of the second groove by heat treatment; Embedded in the first and second grooves,
A first main electrode is formed on the well region so as to be electrically connected to the semiconductor region of the first conductivity type, and a second main electrode is formed on the back side of the first semiconductor layer so as to be electrically connected thereto. And a method of manufacturing a semiconductor device.
おいて、 上記制御電極の形成後、主電極を形成する前に、軽イオ
ンをその飛程距離が上記ウェル領域内に収まるよう１０
10〜１０13個／cm2 の照射量で第１半導体層の第１主面
側から照射する工程と、その後低温シンターを３００〜
４００°温度で１〜５時間行う工程とを追加して、上記
絶縁膜の、上記第２導電型のウェル領域と接する部分に
固定電荷を形成し、 上記絶縁膜の、第１の溝内壁面上及び第２の溝底面上の
部分の厚膜化によるしきい値電圧の基準値に対する増大
分と、上記絶縁膜の、上記第２導電型のウェル領域と接
する部分での固定電荷の形成によるしきい値電圧の基準
値に対する減少分とを等しくしたことを特徴とする半導
体装置。7. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the control electrode and before forming the main electrode, light ions are applied so that the range of the light ions falls within the well region.
A step of irradiating from the first main surface side of the first semiconductor layer with an irradiation amount of 10 to 10 13 / cm 2 , and then performing a low-temperature sintering for 300 to
Adding a step of performing at a temperature of 400 ° C. for 1 to 5 hours to form a fixed charge in a portion of the insulating film in contact with the well region of the second conductivity type; The increase in the threshold voltage with respect to the reference value due to the increase in thickness of the upper and second trench bottom portions and the formation of fixed charges in the portion of the insulating film in contact with the second conductivity type well region A semiconductor device characterized in that a decrease in threshold voltage with respect to a reference value is made equal.
に第２の導電型の第２半導体層及び第１導電型の第３半
導体層を順次形成し、該第３半導体層上に選択的に第２
導電型の第４半導体層を、該第４半導体層上に第１導電
型の第５半導体層を形成し、該第５半導体層の上部の周
辺部分に選択的に第２導電型の第６半導体層を形成して
なる半導体層構造を有するとともに、 上記第４及び第５の半導体層の側面に近接するよう形成
された制御電極と、 該制御電極と上記第４及び第５の半導体層の間に形成さ
れた絶縁膜と、 上記第５及び第６の半導体層上に跨がって形成された第
１の主電極と、 上記第１半導体層の第２主面上に形成された第２の主電
極とを備え、 上記絶縁膜は、上記第４半導体層と接する部分の膜厚
を、基準膜厚であるその他の部分の膜厚に比べて薄くし
た構造とし、 上記制御電極に所定のオン電位の順バイアスを印加した
時、上記第５半導体層の、上記絶縁膜近傍部分にチャネ
ルが形成され、上記制御電極に所定のオフ電位の逆バイ
アスを印加した時、上記第１導電型の第４半導体層の、
該絶縁膜近傍部分が第２導電型領域に反転するよう構成
したものであることを特徴とする半導体装置。8. A second semiconductor layer of the second conductivity type and a third semiconductor layer of the first conductivity type are sequentially formed on the first main surface of the first semiconductor layer of the first conductivity type, and Selectively second on layer
A fourth conductive semiconductor layer is formed by forming a fifth semiconductor layer of the first conductive type on the fourth semiconductor layer, and selectively forming a sixth semiconductor layer of the second conductive type on a peripheral portion above the fifth semiconductor layer. A control electrode formed to have a semiconductor layer structure formed by forming a semiconductor layer, and formed so as to be close to side surfaces of the fourth and fifth semiconductor layers; and a control electrode formed by the control electrode and the fourth and fifth semiconductor layers. An insulating film formed therebetween, a first main electrode formed over the fifth and sixth semiconductor layers, and a first main electrode formed on a second main surface of the first semiconductor layer. The insulating film has a structure in which the film thickness of a portion in contact with the fourth semiconductor layer is smaller than the film thickness of the other portion which is a reference film thickness. When a forward bias of ON potential is applied, a channel is formed in a portion of the fifth semiconductor layer near the insulating film. , When applying a reverse bias of a predetermined OFF potential to the control electrode of the fourth semiconductor layer of the first conductivity type,
A semiconductor device, wherein a portion near the insulating film is configured to be inverted to a second conductivity type region.
接する部分の膜厚を、その基準膜厚であるその他の部分
の膜厚に対して増大し、かつその上記第５半導体層と接
する部分にイオンを注入して固定電荷を形成した構造と
し、 上記絶縁膜の第４半導体層と接する部分の、基準膜厚に
対する薄膜化による制御電極の容量の基準値に対する増
大分は、その第３，第５及び第６半導体層と接する部分
の、基準膜厚に対する膜厚増大による制御電極の容量の
基準値に対する減少分と等しく、 かつ上記絶縁膜の基準膜厚に対する膜厚増大によるしき
い値電圧の基準値に対する増大分は、該絶縁膜での固定
電荷の形成によるしきい値の基準値に対する減少分と等
しくなっていることを特徴とする半導体装置。9. The semiconductor device according to claim 8, wherein said insulating film has a film thickness of a portion in contact with said third, fifth and sixth semiconductor layers, and a film of another portion which is a reference film thickness. A structure in which fixed charges are formed by injecting ions into a portion in contact with the fifth semiconductor layer, the thickness of the insulating film being in contact with the fourth semiconductor layer being reduced with respect to a reference film thickness; The increase in the capacitance of the control electrode with respect to the reference value is equal to the decrease in the capacitance of the control electrode with respect to the reference value due to the increase in the film thickness with respect to the reference film thickness in the portion in contact with the third, fifth, and sixth semiconductor layers. The increase in the threshold voltage with respect to the reference value due to the increase in the thickness of the insulating film with respect to the reference thickness is equal to the decrease in the threshold value with respect to the reference value due to the formation of fixed charges in the insulating film. Characterized by semiconductive Body device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191578A JP2983110B2 (en) | 1992-06-24 | 1992-06-24 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191578A JP2983110B2 (en) | 1992-06-24 | 1992-06-24 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0613621A JPH0613621A (en) | 1994-01-21 |
| JP2983110B2 true JP2983110B2 (en) | 1999-11-29 |
Family
ID=16276991
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4191578A Expired - Lifetime JP2983110B2 (en) | 1992-06-24 | 1992-06-24 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2983110B2 (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
| JP3850054B2 (en) | 1995-07-19 | 2006-11-29 | 三菱電機株式会社 | Semiconductor device |
| US6693310B1 (en) | 1995-07-19 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| KR100452312B1 (en) * | 1997-05-13 | 2005-07-05 | 삼성전자주식회사 | Memory device using GTO and its manufacturing method |
| CN1139134C (en) | 1998-01-22 | 2004-02-18 | 三菱电机株式会社 | Insulating gate type bipolar semiconductor device |
| US6777745B2 (en) * | 2001-06-14 | 2004-08-17 | General Semiconductor, Inc. | Symmetric trench MOSFET device and method of making same |
| US6784488B2 (en) * | 2001-11-16 | 2004-08-31 | Koninklijke Philips Electronics N.V. | Trench-gate semiconductor devices and the manufacture thereof |
| WO2005036650A2 (en) | 2003-10-08 | 2005-04-21 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| JP2006303287A (en) * | 2005-04-22 | 2006-11-02 | Toshiba Corp | Power semiconductor apparatus |
| JP4867597B2 (en) * | 2006-11-15 | 2012-02-01 | 三菱電機株式会社 | Manufacturing method of semiconductor device having trench structure |
| JP2008135458A (en) | 2006-11-27 | 2008-06-12 | Elpida Memory Inc | Semiconductor device and its fabrication process |
| JP4450241B2 (en) | 2007-03-20 | 2010-04-14 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
| JP2009135360A (en) * | 2007-12-03 | 2009-06-18 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP5969771B2 (en) | 2011-05-16 | 2016-08-17 | ルネサスエレクトロニクス株式会社 | IE type trench gate IGBT |
| JP6715567B2 (en) * | 2014-12-16 | 2020-07-01 | 富士電機株式会社 | Semiconductor device |
| CN106663692B (en) | 2015-02-03 | 2020-03-06 | 富士电机株式会社 | Semiconductor device and method for manufacturing the same |
| CN206194745U (en) * | 2016-07-22 | 2017-05-24 | 三垦电气株式会社 | Semiconductor device |
| JP6237845B1 (en) * | 2016-08-24 | 2017-11-29 | 富士電機株式会社 | Vertical MOSFET and manufacturing method of vertical MOSFET |
| JP6885414B2 (en) * | 2019-03-11 | 2021-06-16 | 富士電機株式会社 | Semiconductor device |
| JP7339908B2 (en) * | 2020-03-19 | 2023-09-06 | 株式会社東芝 | Semiconductor device and its control method |
-
1992
- 1992-06-24 JP JP4191578A patent/JP2983110B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0613621A (en) | 1994-01-21 |
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