JPH11195770A - Nonvolatile semiconductor memory device and data erasing method for nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease dissipation current by setting an erasing voltage from a voltage step-up circuit at the low voltage and to achieve miniaturization by providing a voltage applying means, which generates a second voltage from a first voltage from an erasing-gate decoder and applies the voltage on the erasing decoder. SOLUTION: For wiring data into a cell, a selecting signal for selecting an applicable cell row is outputted from a word line WL of a word decoder 2 and given to a control gate CG of the cell. An desired bit line BL is selected, and the data are written into a floating gate FG via a drain D of the intended cell. On the other hand, for reading the data of the cell, the selecting signal for selecting the applicable cell row is outputted from the word line WL of the word decoder WL and given to the control gate CG of the cell. Thereafter, the data of the erasing gate EG are read out via the source S of the cell, which is connected to the intended bit line BL. For erasing the cell data, the voltage is outputted to the erasing line from the decoder 3, and the FG data of all the cells are erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device having an erase gate for erasing data, and a data erasing method therefor.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device is a flash memory, and includes a cell array 1 for storing data, a word decoder 2 for selecting a cell array 1 in a row direction, and an erase gate decoder 3 for erasing data of each cell in the cell array. And a booster circuit 4 for supplying a voltage of 20 V to the erase gate decoder 3 to erase data in the cells.

In FIG. 7, when writing data to a cell, first, a selection signal for selecting a corresponding cell row is output from a word line WL of a word decoder 2 to control a cell control gate (control gate; hereinafter, CG). ), A desired bit line BL is selected, and data is written from a drain D side of a desired cell to a floating gate (floating gate; hereinafter, FG) via the bit line BL. On the other hand, when reading cell data, the word decoder 2
A selection signal for selecting a corresponding cell row is output from the word line WL and applied to the CG of the cell, and then a desired bit line BL is selected and a source of a desired cell connected to the bit line BL is selected. The data of the FG is read via S.

Next, when erasing the data in the cell, a voltage of 20 V is output from the erase gate decoder 3 to the erase line EL. Then, the data of all the cells connected to the erase line EL by the erase gate (hereinafter, EG) is erased. That is, when a high voltage of 20 V is applied to the erase line EL, the EG of the cell connected to the erase line EL also becomes 20 V. Then, the electrons of the FG 13 of the corresponding cell are moved to the EG 16 side, as shown in FIG.
As shown by the arrow, the cell is pulled out by the FN tunnel phenomenon, and as a result, the data of the corresponding cell is erased. In addition,
8, reference numeral 10 denotes a P-SUB (P-type semiconductor substrate);
11 is an insulating film made of SiO2, 12 and 14 are insulating films,
Reference numeral 15 denotes each CG.

[0005]

When erasing data from a cell as described above, a high voltage of about 20 V is required. However, in the conventional device, since the erase voltage is generated by the booster circuit, the power consumption of the booster circuit increases, and a control circuit such as an erase gate decoder for supplying the high erase voltage to the cell has a high breakdown voltage structure. Therefore, there is a problem that miniaturization of the device becomes difficult. Accordingly, an object of the present invention is to reduce the current consumption of the device by reducing the erase voltage from the booster circuit, and to miniaturize the device.

[0006]

In order to solve such a problem, the present invention provides a CG (control gate) connected to a word line and an FG (floating gate) to which data is written.
A cell array including a plurality of cells each having an EG (erase gate) for erasing FG data based on application of a first voltage; a word decoder for selecting a word line; and an erase gate decoder for selecting EG. A non-volatile semiconductor memory device having voltage application means for generating a first voltage and applying the second voltage to the EG when a second voltage lower than the first voltage is output from the erase gate decoder to the EG of the cell. It is a thing. In addition, when the second voltage is applied to the EG, the voltage application unit applies a predetermined voltage to the CG from the word decoder via the word line and a voltage holding unit that holds the second voltage to the EG. And a voltage adding means for adding a voltage based on the capacitance between the CG and the EG to the second voltage of the EG and applying the added voltage as the first voltage. Further, the capacity between EG and FG is sufficiently smaller than the capacity between EG and CG. A first step of applying a second voltage lower than the first voltage from the erase gate decoder to the EG of the cell, and a second step of applying the second voltage to the EG and then bringing the EG into a floating state And a predetermined voltage is applied to the CG from the word decoder via the word line to change the voltage due to the capacitive coupling between the CG and the EG to E.
A third voltage to be added to the second voltage of G and applied as the first voltage
And a data erasing method having the following steps.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the present invention. In this figure, the nonvolatile semiconductor memory device has a drain D, a source S,
CG (control gate; control gate), FG (floating gate; floating gate), EG (erase gate)
, A word decoder 2 connected to the CG of each cell of the cell array 1 via a word line WL to select each column row, and connected to an EG of each cell via an erase line EL An erase gate decoder 3 for erasing data from each cell and an erase circuit 5 for applying an erase voltage to the erase gate decoder.

In FIG. 3, when data is written to a cell, first, a selection signal for selecting a corresponding cell row is output from the word line WL of the word decoder 2 and the CG of the cell is output.
, A desired bit line BL is selected, and data is written to FG via a drain D of a desired cell connected to the bit line BL. On the other hand, when reading data from a cell, a selection signal for selecting a corresponding cell row is output from the word line WL of the word decoder 2 and applied to the CG of the cell, and then a desired bit line BL is selected. The data of FG is read through the source S of the desired cell connected to the bit line BL. Next, when erasing the data of the cell, a voltage of 12 V is output from the erase gate decoder 3 to the erase line EL. Then, the data of the FG of all the cells connected to the erase line EL by the EG is erased.

That is, when erasing the data in the cell, as shown in the timing chart of FIG. 4, first, a voltage of 12 V is output from the erase gate decoder 3 to the erase line EL at a point in time (FIG. 4B). The voltage of the EG is set to 12 V (FIG. 4
(C)). Next, at the time, the output of the erase gate decoder 3 is opened (OPEN) to be in a floating state (FIG. 4).
(B)) Then, a 12 V voltage is output from the word decoder 2 to the corresponding word line WL, and the CG voltage is set to 12 V (FIG. 4).
(A)). Then, the voltage of the EG becomes 20 V, the electrons of the FG are pulled out to the EG side by a tunnel phenomenon, and the data of the FG is erased.

FIG. 5 is a block diagram showing a specific configuration of an erasing circuit for erasing data of a cell.
It comprises a word decoder driver 21 which is an output stage of the word decoder 2, an erase gate driver 31 which is an output stage of the erase gate decoder 3, and a transistor TR. FIG. 6 is a timing chart showing the operation of the erase circuit shown in FIG. The operation at the time of data erasure of a cell will be described more specifically with reference to FIGS.

When erasing cell data, first, FIG.
When the erase signal ADG shown in (a) goes to the “H” level at the time and is given to the erase gate driver 31, the erase gate driver 31 outputs the voltage VP1 to EG, and as shown in FIG. Is VP1.

Next, when the erase signal ADG is set to the "L" level and the address selection signal ADCG given to the word decoder driver 21 shown in FIG.
2 is output, and the voltage of the CG connected to this is
It becomes VP2 as shown in (e). Here, the erase signal A
Since the output of the erase gate decoder driver 31 is in a floating state even when DEG is set to the “L” level, the voltage of EG is held by the capacitor C1. Also, E
A coupling capacitance C3 exists between G and CG,
When the voltage of the CG becomes VP2, as shown in FIG. 6D, a high voltage obtained by adding a voltage based on the coupling capacitance C3 to the held voltage VP1 is applied to the EG. .

That is, when the output voltages VP1 and VP2 of the erase gate driver 31 and the word decoder driver 21 are respectively set to 12V as shown in FIG. 3, the EG is coupled to the voltage 12V output from the erase gate driver 31. A voltage of 8 V by the capacitor C3 is added, and a total of 20
A high voltage of V is applied. As a result, the voltage between the EG and the FG becomes high, electrons in the FG are pulled out to the FG side by a tunnel phenomenon, and data is erased.

Next, when an "H" level discharge signal DIS is output to the transistor TR to turn on the transistor TR at the time shown in FIG. 6C, the electric charge stored in the capacitor C1 and the electric charge stored in the coupling capacitor C1 are stored. The charge is discharged via the transistor TR. Subsequently, the signal ADCG to the word decoder driver 21 is set to “L” level at a point in time, and then the discharge signal DI
S is set to “L” to turn off the transistor TR.

As described above, when erasing data from a cell, first, the EG is supplied with the erasing voltage VP1 and is held.
By applying the gate voltage VP2 to the CG, a voltage based on the coupling capacitance between the EG and the CG is added to the holding voltage of the EG, and the EG voltage is set to a high voltage at which data can be erased. As a result, a booster circuit that generates a high voltage is not required, so that the current consumption of the device can be reduced and the device can be miniaturized.

FIG. 1 is a sectional view showing the structure of a main part of a cell. In FIG. 1, the cell comprises a P-SUB (P-type semiconductor substrate) 10, an insulating film 11 made of SiO2, a gate insulating film 12, a FG 13, an insulating film 14, a CG 15, and an EG 16, and is manufactured by the following steps. You.

That is, first, the insulating film 11 is formed on the P-SUB 10.
Is formed, the portion of the insulating film 11 on which the FG 13 is formed is removed by etching, and the etched P-SUB is removed.
A gate insulating film 12 is formed on 10. Then, the insulating film 1
1 and the gate insulating film 12 are formed with polysilicon to be FG13.
A film is formed to a thickness of 230 ° (angstrom), and then polysilicon to be CG15 is formed. Thereafter, these films are subjected to ordinary photolithography to form FGs 131, 132, insulating films 141, 142, CG 15 in FIG.
The other portions are etched away except for the portions 1 and 152. Thereafter, an insulating film having a thickness of 200 to 230 ° is formed on the exposed surfaces of the polysilicon surfaces of FG13 and CG15, and then polysilicon which becomes EG16 is formed. Is formed by etching away.

FIG. 2A is an equivalent circuit diagram of each gate of the cell shown in FIG. 1, where VEG is the voltage of EG16 and VCG is CG.
A voltage of 15 and VFG indicate a voltage of FG13, respectively. CEC is the capacitance of the insulating film between EG16 and CG15, CEF is the capacitance of the insulating film between EG16 and FG13, CCF
Is the capacitance of the insulating film between CG15 and FG13, and CFS is FG1
3 shows the capacitance of the insulating film between P-SUB 10 and P-SUB 10, respectively. Note that QEG is the charge amount of EG16, and QFG is FG13
Is the amount of charge of

Here, an erasing voltage is applied to the EG 16 to
In order to extract the electrons of G13 to the EG16 side, EG1
EG16 and FG13 for the capacitance CEC between
It is necessary to make the capacitance CEF between them sufficiently small such that CEC≫CEF (1). That is, in FIG. 2B, if the thickness of the insulating film 14 is fixed, the length (L1 + L2) of the insulating film 142 between the CG 15 and the EG 16 is smaller than that of the FG 13
It is necessary to make the length L3 of the insulating film 142 between the gate electrode EG16 and EG16 sufficiently short. As a result, when the erasing voltage is applied to the EG 16, only the electrons e of the FG 13 are extracted to the FG 16 side, the data of the FG 13 is erased, and the electrons of the CG 15 are not extracted.

Further, in order to efficiently extract the electrons e of the FG 13 to the FG 16 side, the CG 15 and the FG 1
The capacitance CEF between the EG 16 and the FG 13 needs to be sufficiently smaller than the capacitance CCF between the FG 16 and the capacitance CFS between the FG 13 and the P-SUB 10 so that CCF≫CEF (2) and CFS≫CEF (3).

That is, in FIG. 2B, CG 15 and F
For the length L4 of the insulating film 141 between G13, FG13
It is necessary to make the length L3 of the insulating film 142 between the gate electrode EG16 and EG16 sufficiently short. In addition, the length L3 of the insulating film 142 between the FG 13 and the EG 16 needs to be sufficiently shorter than the length L5 of the insulating film 12 between the FG 13 and the P-SUB 10. With such a configuration, the data of the FG 13 can be accurately erased.

By defining the above conditional expressions (1) to (3), the voltage of EG16 shown in FIG. 2A can be expressed as VEG = QEG / CEC + VCG (4). Here, in equation (4),
It is preferable to increase QEG / CEC. In this case, since QEG is constant, the capacitance CEC between EG16 and CG15 is reduced.

The voltage V of the FG 13 shown in FIG.
FG can be expressed as VFG = QFG / (CCF + CFS) + VCG.CCF / (CCF + CFS) (5) Here, in the equation (5), since QFG is constant, it is preferable to reduce CCF / (CCF + CFS) in order to lower the voltage VFG of the FG13. Therefore, FG13 and PFG shown in FIG. -S
It is preferable to make the length L4 of the insulating film 141 between the CG 15 and the FG 13 shorter than the length L5 of the insulating film 12 between the UBs 10.

[0024]

As described above, according to the present invention, the CG (control gate) connected to the word line, the FG (floating gate) to which data is written, and the FG based on the application of the first voltage. In a nonvolatile semiconductor memory device including a cell array including a plurality of cells each having an EG (erase gate) for erasing data, a word decoder for selecting a word line, and an erase gate decoder for selecting an EG, From the second voltage lower than the first voltage
Is output to the EG of the cell, the first voltage is generated and applied to the EG. Therefore, the output voltage of the booster circuit provided in the device and providing the erase voltage to the erase gate decoder is determined by The voltage can be reduced, so that the current consumption of the device can be reduced and the device can be miniaturized. Further, a voltage application unit for applying the first voltage to the EG, a voltage holding unit for holding the second voltage on the EG when the second voltage is applied to the EG, and a word decoder via the word line. When a predetermined voltage is applied to the CG, a voltage based on the capacitance between the CG and the EG is added to the second voltage of the EG and the voltage is added as a first voltage. With such a configuration, a high voltage can be applied to the EG. Further, the capacity between EG and FG is set to EG
Since the capacity between the data and the CG is sufficiently smaller, the data of the FG can be surely erased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a main part cross-section of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a gate in a memory cell constituting the device (FIG. 2A) and a diagram for explaining a magnitude relationship between capacitances between gates (FIG. 2B).

FIG. 3 is a block diagram showing a configuration of the device.

FIG. 4 is a timing chart showing a data erasing operation of the device.

FIG. 5 is a block diagram showing a main configuration of the above device.

FIG. 6 is a time chart illustrating operation timings of respective units of the data erasing circuit illustrated in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional device.

FIG. 8 is a diagram showing a cross section of a main part of a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Cell array, 2 ... Word decoder, 3 ... Erase gate decoder, 5 ... Booster circuit, 10 ... P-SUB (P-type semiconductor substrate), 11, 12, 14 ... Insulating film, 13 ... Floating gate (Floating gate; FG) ), 15: control gate (control gate; CG), 16: erase gate (E
G), WL: word line, BL: bit line.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (4)

[Claims] 1. A plurality of cells each having a control gate connected to a word line, a floating gate to which data is written, and an erase gate for erasing data of the floating gate based on application of a first voltage. In a nonvolatile semiconductor memory device having a cell array, a word decoder for selecting the word line, and an erase gate decoder for selecting the erase gate, a second voltage lower than the first voltage is applied from the erase gate decoder to the second gate. When output to the erase gate of the cell, the first
A non-volatile semiconductor memory device, comprising: a voltage applying means for generating a voltage and applying the generated voltage to an erase gate. 2. The device according to claim 1, wherein the voltage application unit comprises: a voltage holding unit that holds a second voltage at the erase gate when a second voltage is applied to the erase gate; and a word line from the word decoder. When a predetermined voltage is applied to the control gate via the control gate, a voltage based on the capacitance between the control gate and the erase gate is added to the second voltage of the erase gate, and the voltage adding means is applied as the first voltage. A nonvolatile semiconductor memory device, comprising: 3. The nonvolatile semiconductor memory device according to claim 1, wherein the capacitance between the erase gate and the floating gate is sufficiently smaller than the capacitance between the erase gate and the control gate. 4. A plurality of cells each having a control gate connected to a word line, a floating gate to which data is written, and an erase gate for erasing data of the floating gate based on application of a first voltage. In a nonvolatile semiconductor memory device having a cell array, a word decoder for selecting the word line, and an erase gate decoder for selecting the erase gate, a second voltage lower than the first voltage is supplied from the erase gate decoder to the second voltage. A first step of applying a second voltage to the erase gate of the cell, a second step of applying the second voltage to the erase gate, and then bringing the erase gate into a floating state; A predetermined voltage is applied to add a voltage due to capacitive coupling between the control gate and the erase gate to a second voltage of the erase gate. First
And a third step of applying the data as a voltage of the non-volatile semiconductor memory device.