JP2850655B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device (flash E ² PROM) which can be electrically written and erased collectively.

[0002]

^2. Description of the Related Art Conventionally, this type of flash E ² PROM
As a typical example, for example, the Journal of Solid State Circuit (Journal of Solid State Circuit)
Solid State Circuit), twelfth
3, No. 5, October 1988, p. 1157. The operation of the memory cell is described in the 1988 IEE / International Reliability Physics Symposium (1988 IEEE / Inte
rnftional Reliability phy
sics Symposium), page 158. This prior art will be described below.

FIG. 3A is a sectional view of a single memory cell. The memory cell includes a drain region 52 and a source region 53 formed on the surface of a P-type silicon substrate 51.
A floating gate electrode 55 provided on a channel region between the drain and the source via a tunnel insulating film 54;
It comprises a control gate electrode 57 provided thereon with an insulating film 56 interposed.

Next, the operation will be described. To write data, the source region 53 is grounded as shown in FIG.
A high voltage (V) is applied to the control gate electrode 57 and the drain region 52.
g and Vd) are applied to inject electrons generated by impact ionization near the drain region into the floating gate electrode. Figure 3 shows how to erase data.
As shown in (C), the control gate electrode 57 is grounded, the drain region 52 is opened or grounded, and the source region 53 is opened.
Is applied by applying a high voltage Vpp to the floating gate electrode 56 and tunneling the electrons from the floating gate electrode 56 to the source region 53.

As shown in FIG. 4, a plurality of such memory cells MC are arranged in a matrix to form a memory cell array. A plurality of word lines 101 are formed by commonly connecting control gates of memory cells in the same row, and a plurality of bit lines 102 are formed by commonly connecting drain regions of memory cells in the same column. A plurality of source lines 103 are formed by connecting the sources of the cells in common.

The word lines are connected to a row selection circuit 105, and the bit lines are connected to a column selection circuit 104.

The source lines are commonly connected, and are connected via a switching circuit 106 to the ground terminal when reading and writing of the memory cell, and to the erase voltage generating circuit 110 when erasing the memory cell. Further, a read control circuit 108 for performing read control of the memory cell and a write control circuit 109 for performing write control of the memory cell are provided. Read control circuit 108, write control circuit 10
9. The output of the erase control circuit 107 is connected to the row selection circuit 106 and the column selection circuit 104.

Next, the operation will be described. At the time of writing to the memory cell, the source line 103 is connected to the ground terminal via the switching circuit 106 to operate the write control circuit 109, and the column selection circuit 104 and the row selection circuit 105 control one bit line and one word. The line is set to a high potential and writing is performed on one memory cell MC. At the time of reading, as in the case of writing, the source line 103 is connected to the ground terminal, the read control circuit 108 is operated, and the column selection circuit 104 and the row selection circuit 105 apply one bit line and one word line to a predetermined voltage. (About 5 V) to read one memory cell. At the time of erasing the memory cell, the source line 103 is connected to the erasing voltage generating circuit 110 via the switching circuit 106, and the erasing control circuit 10
7, the source line is set to a high potential (about 15 V), all word lines are set to the ground potential, all bit lines are opened, and all memory cells are erased.

FIG. 5 shows a conventional erase voltage generating circuit.
It is composed of an N-channel enhancement type transistor Q2. The drain electrode is connected to the high voltage power supply terminal 1, the gate electrode is connected to the erase control terminal 2, and the source electrode is connected to the switching circuit 106.
Connected to. At the time of the erasing operation, a signal is input to the erasing control terminal 2 during the erasing time te to turn on Q2,
During the period te, the source line 103 of the memory cell array is
A high voltage (Vpp = 15V) is applied via the switching circuit 106. The erasing time te is appropriately set so that over-erasing (excessive erasing) of the cell does not occur. This is because if overerasing occurs, correct data cannot be read. About this, FIG. 6, FIG.
This will be described with reference to FIG.

FIG. 6 is a graph showing the relationship between the threshold voltage _VTM of a memory cell and the erasing time. As a result, when the erase time te exceeds a certain value t ₀ , in the initial state, the threshold voltage of the written memory cell becomes a negative value, for example, about 5 V. In other words, a so-called depletion state occurs in which the gate is turned on even when the gate is grounded. This is over-erasing (excessive erasing). Here, FIG.
It is assumed that the memory cell H has been overerased in the above. Then, for example, when data is written to the memory cell I and then this data is read, no current flows between the drain and the source in the selected cell I. However, in the non-selected cell H, the drain
Since a current flows between the sources, a current also flows to the bit line at the left end of the drawing, and the memory cell I which is an off bit is detected as an on bit. In the conventional erase control circuit, the erase time t is set so that the cell is not over-erased.
e is set to a certain value.

[0011]

In the conventional nonvolatile semiconductor memory device described above, when the gate length of a memory cell is made thicker or thinner due to manufacturing variations, overerasing or insufficient erasing of the memory cell occurs. There is a drawback that is easy to occur. Figure 7 shows the data obtained by our company. This shows the memory cell gate length dependence of the memory cell threshold voltage after erasing for te time. The longer the gate length, the lower the threshold voltage after erasing,
Eventually, the threshold voltage becomes negative, that is, an over-erase state occurs. In addition, as the gate length becomes shorter, the threshold voltage after erasure becomes higher, and the erasure becomes insufficient. In other words, when the erase time te and the control voltage are constant, the gate length of the memory cell varies, resulting in overerasing and insufficient erasing. The reason can be understood from the model shown in FIG. Here, L is the gate length, C1 is the capacitance between the substrate and the floating gate electrode, C2 is the capacitance between the floating gate electrode and the control gate electrode, and C3 is the capacitance between the drain / source and the floating gate electrode. In the state shown in FIG.
When applied to, the difference between the source potential and the floating gate potential is
[1−C3 / (C1 + C2 + 2C3)] Vs. Since C1 and C2 increase as L increases, the potential difference also increases, indicating that the erasing speed increases.

As described above, in the conventional nonvolatile semiconductor memory device, it is difficult to set an appropriate erasing time in consideration of variations in the memory cell gate length.

[0013]

SUMMARY OF THE INVENTION A nonvolatile semiconductor device according to the present invention
The storage device controls a memory cell having a control gate electrode connected to a word line, a drain region connected to a bit line, a source region connected to a source line and a floating gate electrode, and an erase operation of the memory cell. An erasing control circuit, an erasing voltage generating circuit for generating a predetermined erasing voltage in response to an erasing mode signal from the erasing control circuit, and switching a voltage supplied to the source line in response to the erasing mode signal to the erasing voltage. A non-volatile semiconductor memory device having a switching circuit, wherein the erasing voltage generating circuit has a resistor element having one end connected to a high voltage terminal, and a drain region connected to the other end of the resistor element, and has the same type as the memory cell. A reference transistor whose gate length is substantially the same as the gate length of the memory cell; and the reference transistor And a connected inverting amplifier to the input end of the connection point between the drain region and the other end of the resistive element
It is configured.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a circuit block diagram of an erase voltage generating circuit according to a first embodiment of the present invention. FIG.
In (A), one end of a resistance element R is connected to a high-voltage power supply terminal 1.
(For example, 12.5 V), and the other end is connected to the connection point A. The drain region of the reference transistor Q1 having the same structure as the memory cell is connected to a connection point A.
The gate electrode is connected to the erase control terminal 2 and the source region is connected to the installation end. The input terminal of the inverting amplifier 5 is connected to the connection point A, and the output terminal is connected to the switching circuit 106.
This switching circuit is connected to the source line of the memory cell (1 in FIG. 4).
03) is connected to the connection point B during the erase operation, and to the ground terminal otherwise. Here, the gate length of the reference transistor Q1 and the gate length of the memory cell are defined by the same lithography and etching process, and are regarded as substantially the same. The inverting amplifier 5 includes the operational amplifier 4 and
A resistance element R2 provided between the input terminal 6 and the output terminal 7
And a resistance element R1 connected between the connection point A and the input terminal 6 of the operational amplifier 4. A high voltage Vpp (for example, 12.5 V) is applied to the reference voltage terminal 3. At this time, the output voltage Vout is

[0016]

[Table 1]

It can be seen that the higher the input voltage Vin, the lower the voltage, and the lower the Vin, the higher the input voltage.

In the erase operation, the erase control circuit 10 shown in FIG.
7, a signal is sent to the column selection circuit 104 to open all bit lines, a signal is sent to the row selection circuit 105 to set all word lines to the ground potential, and a signal is sent to the switching circuit 106 to erase the source line 103. The high voltage Vp is connected to the high voltage power supply terminal 1 of the erase voltage generation circuit 110A.
Apply p. At this time, a constant voltage, for example, 5 V is applied to the erase control terminal 2. Then, Q1 is turned on, and a constant current I flows between the drain and source of Q1 and R. The voltage Vin at the connection point A is given by Vpp-RI. The voltage Vout at the connection point B is given by Vpp + RI. This voltage is supplied to the source region of the memory cell via the switching circuit 106.

Here, consider a case where the gate length of the memory cell is made thicker due to manufacturing variations. Since the gate length of the memory cell and the gate length of Q1 are determined by the same lithography and etching process, the gate length of Q1 is similarly increased. Therefore, the ON current I of Q1 decreases, and the voltage at point B also decreases. Conversely, when the gate length of the memory cell is made smaller, the ON current I of Q1 increases, and the voltage at point B also increases.

That is, the gate length of Q1 and the voltage at point B (erasing voltage) have the relationship shown in FIG. As a result, the erasing speed of the memory cell is kept almost constant. In this manner, a change in the erase speed due to a variation in the gate length of the memory cell can be corrected by changing the applied voltage accordingly.
This is the point of the present invention. FIG. 1C shows the relationship between the threshold voltage after erasing a memory cell and the gate length of the memory cell.

According to the present invention, even if the gate length of the memory cell varies, the threshold value of the erased memory cell can be kept substantially constant.

FIG. 2A is a circuit block diagram for explaining a second embodiment of the present invention. In this example,
The transistor Q1A has a control gate electrode 57 and a gate electrode in which the floating gate electrode 55 is short-circuited via the connection hole 59 as shown in FIG. As a result, it is possible to eliminate a factor that changes the ON current of Q1A other than the gate length, for example, the influence of the variation in the thickness of the insulating film 56 between the floating gate and the control gate. Thus, it is possible to more accurately supply an erasing voltage corresponding to the erasing voltage.

[0023]

As described above, according to the present invention, the erase voltage generating circuit is provided with a reference transistor of the same type as the memory cell whose gate length is defined by the same lithography and etching process as the gate length of the memory cell. By supplying an erase voltage corresponding to the ON current value of the reference transistor to the source region of the memory cell during the erase operation, the gate length of the memory cell becomes thicker or thinner due to manufacturing variations, resulting in overerasing or erasing. When the shortage is likely to occur, the erase voltage is changed in accordance with this, so that overerasing and insufficient erasure can be prevented. That is, according to the present invention, the allowable manufacturing range of the gate length of the memory cell is expanded, and a margin for setting the erasing time in consideration of the case where the gate length varies is not required. Therefore, a non-volatile semiconductor device having a higher yield than before can be obtained, and the reliability of the erasing operation can be improved. According to our study, the resistance value of the resistance element R in FIG. 1 is 10 to 50 kΩ, the channel width of Q1 is 5 to 10 times that of the memory cell, and R1, R
When 2 was set to 1 to 10 kΩ, the allowable manufacturing range of the gate length of the memory cell could be extended by about 50% as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram for explaining a first embodiment of the present invention (FIG. 1A), and shows a relationship between a voltage at a point B in FIG. 1A and a gate length of a reference transistor Q1. FIG. 1B is a graph showing the relationship between the threshold voltage after erasing the memory cell and the gate length of the memory cell (FIG. 1C).

FIG. 2 is a circuit block diagram (FIG. 2 (A)) for explaining a second embodiment of the present invention, and a cross-sectional view (FIG. 2 (B)) showing a reference transistor Q1A in FIG. 2 (A). is there.

FIG. 3 is a cross-sectional view of a memory cell for explaining a conventional technique (FIG. 3A), a schematic cross-sectional view for explaining a writing operation (FIG. 3B), and an erasing operation; FIG. 3C is a schematic sectional view of FIG.

FIG. 4 is a circuit block diagram showing an outline of a flash E ² PROM.

FIG. 5 is a circuit block diagram showing a conventional conventional power consumption generating circuit.

FIG. 6 is a graph showing a relationship between an erasing time te and a threshold voltage of a memory cell after erasing;

FIG. 7 is a graph showing a relationship between a gate length of a memory cell and a threshold voltage of the memory cell after erasing;

FIG. 8 is a schematic sectional view for explaining consumption speed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High voltage power supply terminal 2 Erase control terminal 3 Reference power supply terminal 4 Operational amplifier 5 Inverting amplifier 6 Input terminal 7 Output terminal 51 P-type silicon substrate 52 Drain region 53 Source region 54 Tunnel insulating film 55 Floating gate electrode 56 Insulating film 57 Control gate Electrode 58 Field oxide film 59 Connection hole 101 Word line 102 Bit line 103 Source line 104 Column select circuit 105 Row select circuit 106 Switching circuit 107 Erase control circuit 108 Read control circuit 109 Write control circuit 110 Erase voltage generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-326981 (JP, A) JP-A-6-236693 (JP, A) JP-A-5-81883 (JP, A) JP-A-5-21883 325573 (JP, A) JP-A-5-135595 (JP, A) JP-A-4-6698 (JP, A) JP-A-3-12898 (JP, A) JP-A-2-126498 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] A control gate electrode connected to a word line;
A memory cell having a drain region connected to a bit line, a source region connected to a source line, and a floating gate electrode; an erase control circuit for controlling an erase operation of the memory cell; and an erase mode signal from the erase control circuit A non-volatile semiconductor memory device, comprising: an erasing voltage generating circuit receiving the erasing mode signal to generate a predetermined erasing voltage; and a switching circuit receiving the erasing mode signal to switch a voltage supplied to the source line to the erasing voltage. A voltage generating circuit has a resistance element having one end connected to a high-voltage terminal and a drain region connected to the other end of the resistance element, and has the same type as the memory cell and a gate length substantially equal to the gate length of the memory cell. And a connection point between the drain region of the reference transistor and the other end of the resistance element. The nonvolatile semiconductor memory device, characterized in that it comprises an inverting amplifier connected to the force terminal. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the reference transistor has a gate electrode in which a control gate electrode and a floating gate electrode of a transistor of the same type as the memory cell are commonly connected.