JPH11135622A - Semiconductor device, liquid crystal display device, projection type liquid crystal display device and manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, the manufacture and a liquid crystal display device, etc., for planarizing an inter-layer insulation film so as to eliminate the need of a CMP processing, at the same time improving crack resistance, improving the efficiency of a reflection electrode and the reliability of multilayered metal wiring and improving the yield. SOLUTION: This semiconductor device is provided with an inter-layer insulation film in a structure, for which insulation films and inorganic SOG films 7 and 9 are formed for plural layers on the metal wiring in inter-layer insulation films 6, 8 and 10 of the semiconductor device. Also, in the formation method of the inter-layer insulation films 6, 8 and 10 of the semiconductor device, a process for forming the insulation film on the metal wiring, and the process for forming the inorganic SOG film on it are performed repeatedly, the inter- layer insulation film composed of the plural layer structure of the insulation films and the inorganic SOG films is formed, and the semiconductor device is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, a liquid crystal display device using the semiconductor device, and a projection type liquid crystal display device, and more particularly, to a method of forming an interlayer insulating film of a liquid crystal display device using a semiconductor element. It relates to a forming method.

[0002]

2. Description of the Related Art Conventionally, the flatness of the surface of an interlayer insulating film of a semiconductor element used in a liquid crystal display device has been poor.

FIG. 8 shows a cross-sectional structure of an interlayer insulating film formed by using the conventional technique.

In FIG. 8, 1 is a semiconductor substrate, and 2 is an LO
A COS insulating film, 3 is a gate electrode, 4 is a BPSG film, 5 is a metal electrode wiring, 6 is a first interlayer insulating film, 7 is an SOG, 8 is a second interlayer insulating film, 9 is a recess, and 10 is a step.

In a general process of a conventional MOS transistor, a well region is formed in a semiconductor substrate 1 and Si is formed.
An N film or the like is deposited, a part of the SiN film is removed by patterning, and a LOCOS insulating film 2 is formed by a thermal oxidation method or the like. Next, a gate oxide film is formed by forming a thermal oxide film by a thermal oxidation method or the like, poly-Si or the like is deposited by an LP-CVD method or the like, impurities are introduced, the resistance of the poly-Si is reduced, and a photolithography process is performed. Then, patterning and etching are performed to form the gate electrode 3. Thereafter, a high concentration impurity is introduced into the well region by an ion implantation method by a self-alignment method, and a heat treatment is applied to form a source region and a drain region. Next, an insulating film is deposited by a CVD method or the like,
Reflow by heat treatment. Next, a contact hole is formed by patterning and etching in a photolithography process, a metal film is deposited by a PVD method, and a metal electrode wiring 5 is formed by patterning and etching again. After that, the first interlayer insulating film 6 is deposited by various CVD methods or the like,
After applying the SOG film 7 by a spin coating method and applying heat treatment,
The second interlayer insulating layer 8 is deposited by various CVD methods or the like. Thereafter, a through hole is formed, a metal film serving as a multilayer wiring and a reflective electrode is deposited, and patterning and etching are repeated to form a multilayer wiring and a reflective electrode.

[0006]

However, in the method of forming an interlayer insulating film according to the above-mentioned conventional example, P
Since the (phosphorus) -containing SOG film is used, an etch-back step is required so as not to corrode the metal wiring. When the etch back process is performed, the SO at the portion where the metal wiring contacts
Although G is removed and corrosion does not occur, there is a problem that the step coverage is reduced, the flatness of the interlayer insulating film is deteriorated, and the multilayer metal wiring is easily broken.

Further, the SOG film has a disadvantage that it cannot be formed thick because the internal stress of the SOG film itself is large, and an organic SOG film exists to make up for it. However, since an organic component is contained, an etch-back step is still required. Yes, there are many concerns about the reliability of metal wiring.

Further, the P (phosphorus) -containing SOG cannot be formed thick because of its own stress, but the liquid pool of the SOG increases when the distance between the metal wirings becomes narrow. In particular, when the layout is long metal wirings and the distance between the wirings is narrow, cracks often occur, which causes a very large leak between the metal wirings or a reduction in the yield.

[Object of the Invention] An object of the first invention of the present application is to flatten the surface of an interlayer insulating film.

A second object of the present invention is to planarize the surface of an interlayer insulating film so that CMP processing is not required.

Another object of the third invention of the present application is to improve the crack resistance while flattening the interlayer insulating film so that CMP treatment is not required.

A fourth object of the present invention is to flatten an interlayer insulating film so as not to require a CMP process, and at the same time to improve crack resistance, to improve the efficiency of a reflective electrode and the reliability of a multilayer metal wiring, This is to improve the yield.

[0013]

According to the present invention, there is provided a semiconductor device having a structure in which an insulating film and an inorganic SOG film are formed on a metal wiring in a plurality of layers. A semiconductor device characterized by having an interlayer insulating film.

Further, a method of manufacturing a semiconductor device according to the present invention
In the method for forming an interlayer insulating film of a semiconductor device, a step of forming an insulating film on a metal wiring and a step of forming an inorganic SOG film thereon are repeatedly performed to form the insulating film and the inorganic SOG.
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film having a multilayer structure of a G film.

Further, the step of forming the inorganic SOG film includes the step of forming the inorganic SOG film, the step of irradiating the inorganic SOG film with UV light or O ₂ plasma, and the step of forming the inorganic SOG film again. And a method for manufacturing a semiconductor device.

In the method for forming an interlayer insulating film of a semiconductor device, a first insulating film is formed on a metal wiring, a first inorganic SOG film is formed thereon, and then a second inorganic SOG film is further formed thereon. A method of manufacturing a semiconductor device, comprising forming an insulating film, forming a second inorganic SOG film thereon, and further forming an interlayer insulating film on which a third insulating film is formed.

Further, in the method for forming an interlayer insulating layer of a semiconductor device, a first insulating film is formed on a metal wiring, a first inorganic SOG film is formed thereon, and UV light is irradiated thereon, and the first inorganic SOG film is irradiated again. A second inorganic SOG film, a second insulating film is formed thereon, and a third inorganic SOG film is further formed thereon,
Thereafter, an interlayer insulating film in which a third insulating film is formed is also formed.

Further, in the method for forming an interlayer insulating film of a semiconductor device, a first insulating film is formed on a metal wiring, a first inorganic SOG film is formed thereon, and after irradiation with O ₂ plasma, A second inorganic SOG film is formed again, and a second inorganic SOG film is formed thereon.
And a third inorganic SOG film is further formed thereon, and then an interlayer insulating film is further formed on which the third insulating film is formed.

The film stress of the insulating film above, below, or both of the inorganic SOG film and the inorganic SOG film is the same as that of the inorganic SOG film.
The present invention also provides a method for manufacturing a semiconductor device, which has a stress in a direction opposite to the film stress of the OG film.

The UV light is irradiated in an atmosphere containing an O ₂ component, and its wavelength is 172 nm, 185 nm.
m, or 254 nm.

A step of forming a contact opening;
And forming a wiring portion, wherein the contact opening diameter is 0.6 to 1.2 μm, and the wiring interval is 0.5 to
A method for manufacturing a semiconductor device, wherein the thickness is 1.5 μm.

Further, a liquid crystal display device according to the present invention is a liquid crystal display device comprising the above semiconductor device and a liquid crystal layer.

A projection type liquid crystal display device according to the present invention is a projection type liquid crystal display device using the above liquid crystal display device.

In the above projection type liquid crystal display device,
It has at least three liquid crystal panels for three colors, separates blue light with a high reflection mirror and a blue reflection dichroic mirror, and further separates red and green with a red reflection dichroic mirror and a green / blue reflection dichroic mirror. The projection type liquid crystal display device is characterized in that each liquid crystal panel is separately projected.

[Operation] The first invention according to the present application is characterized in that an inorganic SOG film is formed in a multilayer structure as an interlayer insulating film.

Further, the second invention according to the present application is to form an inorganic SOG film in a multi-layer structure on an interlayer insulating film, irradiate UV light or O ₂ plasma having a specific wavelength, and then re-use the inorganic SOG film.
A film is formed, an insulating film is deposited thereon, an inorganic SOG film is formed again, and the insulating film is further deposited to improve the flatness of the interlayer insulating film to a level that does not require a CMP process. And

According to the third invention of the present application, a contact hole having a contact opening diameter of 0.6 to 1.2 μm is formed, and a metal electrode wiring having a wiring interval of 0.5 to 1.5 μm is formed. Then, after forming one layer of the inorganic SOG film on a part of the interlayer insulating film, UV rays having wavelengths of 172 nm, 185 nm, and 254 nm are irradiated to cut hydrogen groups on the surface of the inorganic SOG film to improve wettability. Then, an inorganic SOG film is formed again, an insulating film is deposited thereon, an inorganic SOG film is formed again, and the insulating film is further deposited so that the interlayer insulating film becomes flat to a level that does not require CMP treatment. It is characterized by remarkable improvement.

[0028]

【Example】

(First Embodiment) FIG. 1 is a drawing which best illustrates the features of the first embodiment of the present invention. FIG. 1 shows a method of forming an interlayer insulating film in a semiconductor device using the present invention, and shows a contact hole. FIG. 4 is a cross-sectional view of a process flow showing embedding.

In FIG. 1, 1 is a semiconductor substrate, 2 is a LO
COS insulating layer, 3 a gate electrode, 4 a BPSG film, 5 a metal wiring electrode, 6 a first interlayer insulating film, 7 a first inorganic SO
G film, 8 is a second interlayer insulating film, 9 is a second inorganic SOG film, 1
0 is a third interlayer insulating film.

A first embodiment of the present invention will be described with reference to FIG.

First, a method for forming a MOS transistor in a semiconductor substrate will be described below. Impurity concentration 1E14 ~
A thermal oxide film (pad oxide film) is formed on the semiconductor substrate 1 of 1E15 cm ^-3 by a thermal oxidation method, and a SiN film is deposited thereon by an LP-CVD method. In this embodiment, the thermal oxide film is
An Angstrom, 2000 Angstrom SiN film is deposited.

Next, a part of the SiN film is removed by patterning and etching in a photolithography process, P (phosphorus) is implanted by an ion implantation method, and subsequently heat treatment is applied to form a well region. In this embodiment, the concentration of the impurity region formed by ion implantation is 1E15 to 1E.
P is injected into 1.8E12cm- ^{2 so} as to be 17cm- ³ ,
The heat treatment is performed at 1000 ° C. for 60 minutes in an N ₂ / O ₂ atmosphere. Further, in this embodiment, after the SiN film is entirely removed, B (boron) is ion-implanted and then heat treatment is applied to form well regions having different conductivity.
The impurity concentration is formed to the same extent as the well region.

Next, a SiN film is deposited again by the LP-CVD method, patterned by a photolithography process, a part of the SiN film is removed, and a thermal oxide film is formed by a thermal oxidation method. In this embodiment, the SiN film thickness is 1
The thickness is 500 angstroms and the thermal oxide film thickness is 8000 angstroms. Subsequently, the SiN film is entirely removed and L
An OCOS insulating film 2 is formed (FIG. 1A).

Next, a gate oxide film is formed by a thermal oxidation method,
An impurity for adjusting the threshold value is introduced by an ion implantation method. In this embodiment, the thickness of the gate oxide film is 850 Å, and the impurity is B (boron) of 4E11 cm ⁻² , 40 Ke.
Under the condition of V, it is implanted below the gate oxide film.

Next, polycrystalline Si is deposited on the gate oxide film by the LP-CVD method, impurities are implanted into the entire surface, heat treatment is performed, and then a gate electrode 3 is formed by a patterning method (FIG. 1). (A)).

In this embodiment, P (phosphorus) is deposited at 1.5E16c after polycrystalline Si is deposited at 4400 angstroms.
The gate electrode 3 is formed by implanting at m ⁻² and 70 KeV, heat-treating at 950 ° C. for 30 minutes in an N ₂ atmosphere, and then patterning and etching.

Here, the gate electrode 3 may have a combination structure of a refractory metal such as W and Co and polycrystalline Si. Further, in this embodiment, in order to improve the breakdown voltage of the gate oxide film, a 350 Å thermal oxide film is formed on the gate electrode 3 by a thermal oxidation method.

Next, a resist is opened around the gate electrode 3 by a resist patterning method, and impurities are implanted. Here, impurities having a conductivity opposite to that of the well region are implanted and heat treatment is performed. In this embodiment, the well region is P-type and P (phosphorus) is 1 to 8E after heat treatment.
It is formed to have a surface concentration of 17 cm ^-3 . This region serves as an electric field relaxation layer and improves the breakdown voltage of the MOS transistor. Further, in this embodiment, B (boron) is ion-implanted into the N-type well region, and heat treatment is performed so that the surface concentration becomes 1E16 to 1E17 cm ^-3 .
An electric field relaxation layer is formed.

Next, an opening is made in the resist around the gate electrode 3 by a resist patterning method, an N-type impurity is introduced into the P-type well region, and after the resist is removed, patterning is performed again. A resist around the gate electrode on the N-type well region is opened, and a P-type impurity is introduced into the N-type well region. In this embodiment, the N-type impurity is P (phosphorus) of 5E15 cm ⁻² and 95 Ke.
Injected under the condition of V, 3E15 cm a P-type impurity BF ₂
^-2 , implantation at 100 KeV. After removing the resist, heat treatment is applied in an N ₂ atmosphere at 1000 ° C. for 10 minutes to diffuse the impurities, thereby forming source and drain regions in the P-type and N-type well regions.

In this embodiment, the source and drain regions are offset by resist patterning. The offset amount is preferably 0.5 to 2.0 μm. As a method of providing an offset, side spacers may be provided on both sides of the gate electrode, and high concentration impurities may be introduced.

Next, an insulating film is deposited by the CVD method. In this embodiment, the BPSG film 4 is deposited by the normal pressure TEOS CVD method. However, the BPSG film 4 may be deposited by another CVD method or a combination of a plurality of insulating films (FIG. 1B). Subsequently, a heat treatment is applied in a N ₂ atmosphere at 1000 ° C. for 5 minutes.
The BPSG film 4 is reflowed.

Next, patterning and etching are performed in a photolithography process to open contact holes on the source and drain regions.
A metal film for wiring and electrodes is deposited by the VD method. In this embodiment, a barrier metal made of Ti and TiN is deposited, and after heat treatment is applied, Al-Si and TiN are successively formed. However, Al-Si-Cu, Al-Cu, Al-C
It is also possible to use a material such as u-Ti.

Next, a metal wiring electrode wiring 5 is formed in a photolithography process (FIG. 1C). In this embodiment, the wiring interval is 1 μm, but may be 0.5 to 5 μm.

Next, a first interlayer insulating film 6 is deposited by P-CVD. In this embodiment, a P-SiO film is deposited to a thickness of 1000 angstroms by the P-CVD method.
An N, P-SiON, or P-TEOS insulating film is also possible.

Next, the first inorganic SOG film 7 is formed by spin coating.
Is applied. In this embodiment, the inorganic SOG film is formed by applying 2200 Å (FIG. 1D).

Thereafter, a heat treatment is applied at 400 ° C. for 30 minutes, and then a second interlayer insulating film 8 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
000 angstroms deposited, but P-Si
N, P-SiON, a combination of multiple insulating films and P-
An insulating film formed by the TEOS method is also possible.

Next, the second inorganic SOG is again formed by the spin coating method.
The film 9 is applied. In this embodiment, the inorganic SOG film is 220
It is formed by applying 0 angstrom. Then 4
Heat treatment is performed at 00 ° C. for 30 minutes, and then the third interlayer insulating film 10 is deposited by the P-CVD method. In this embodiment, P
-An SiO film is deposited at 2000 Å.

The present invention is characterized in that a recess formed when the gate electrode 3 and the metal wiring electrode 6 are brought into contact with each other is filled with an insulating film / an inorganic SOG film / an insulating film / an inorganic SOG film.

[0049] In the present invention, the first inorganic SOG film uses a P-SiO film to the insulating film between the second inorganic SOG film, as the film forming conditions, 450 ° C., SiH ₄ and N
It is deposited using ₂ O so that the film stress is in the compression direction.

Since the inorganic SOG film has a film stress in the tensile direction, the P-SiO film located between the inorganic SOG films is formed for the purpose of relaxing the stress of the inorganic SOG film.

The strength and direction of the stress of the P-SiO film can be changed by changing the thickness of the inorganic SOG film for filling the contact holes and between the wirings. Can be changed. Further, in the present invention, the relationship between the amount of the above-mentioned concave portion generated due to the size of the contact hole and the film thickness of the first and second inorganic SOG films for filling the concave portion is shown in FIG.
The thickness of the inorganic SOG film is between 1500 and 4000 angstroms, which is effective for improving the flatness of the interlayer insulating film.
In this embodiment, the inorganic SOG film is formed with a thickness of 2200 angstroms, but the contact opening diameter is 0.5-1.
4 μm is effective for embedding the concave portion. In particular, when the contact opening diameter is 0.6 to 1.2 μm, the concave amount is 0.1 μm.
m or less, and the flatness is greatly improved.

Thereafter, in a photolithography process, through holes required for conduction with the first metal wiring are opened in the interlayer insulating film by dry etching, and then metal for multilayer wiring is deposited by PVD. A multilayer metal wiring is formed by patterning and etching, or a reflective electrode is formed by performing a CMP process after using an Al reflow method (FIG. 7).

A liquid crystal panel is formed by sandwiching a liquid crystal 65 between the active matrix substrate formed as described above and a counter substrate 63 provided with a transparent electrode 64 (FIG. 7). As the liquid crystal material, a polymer network liquid crystal PNLC is used.
Etc. may be used.

The technical effect of this embodiment is that the interlayer insulating film becomes very flat to the extent that the CMP operation in the interlayer insulating film forming step becomes unnecessary, so that a highly reliable multilayer metal wiring can be formed, It is possible to form reflective electrodes with high reflectivity,
Further, a semiconductor device with a high degree of integration and a display device with a high pixel density can be formed, so that performance and yield can be improved.

(Second Embodiment) FIG. 2 is a drawing showing the features of a second embodiment of the present invention. FIG. 2 shows a method of forming an interlayer insulating film in a semiconductor device according to the present invention. It is sectional drawing of the process flow showing a recessed part embedding.

In FIG. 2, 1 is a semiconductor substrate and 2 is a LO
COS insulating layer, 3 is a BPSG film, 4 is a metal wiring electrode, 5
Is a first interlayer insulating film, 6 is a first inorganic SOG film, 7 is a second interlayer insulating film, 8 is a second inorganic SOG film, and 9 is a third interlayer insulating film.

A second embodiment of the present invention will be described with reference to FIG.

First, a method for forming a MOS transistor in a semiconductor substrate will be described below. Impurity concentration 1E14 ~
A thermal oxide film (pad oxide film) is formed on the semiconductor substrate 1 of 1E15 cm ^-3 by a thermal oxidation method, and a SiN film is deposited thereon by an LP-CVD method. In this embodiment, the thermal oxide film is
An Angstrom, 2000 Angstrom SiN film is deposited.

Next, a part of the SiN film is removed by patterning and etching in a photolithography process, P (phosphorus) is implanted by an ion implantation method, and subsequently heat treatment is applied to form a well region. In this embodiment, the concentration of the impurity region formed by ion implantation is 1E15 to 1E.
P is injected into 1.8E12cm- ^{2 so} as to be 17cm- ³ ,
The heat treatment is performed at 1000 ° C. for 60 minutes in an N ₂ / O ₂ atmosphere.

Further, in this embodiment, after the SiN film is entirely removed, B (boron) is ion-implanted and then heat treatment is applied to form well regions having different conductivity. It is formed to the same extent as the well region.

Next, a SiN film is deposited again by the LP-CVD method, patterned by a photolithography process, a part of the SiN film is removed, and a thermal oxide film is formed by a thermal oxidation method. In this embodiment, the SiN film thickness is 1
The thickness is 500 angstroms and the thermal oxide film thickness is 8000 angstroms. Subsequently, the SiN film is entirely removed and L
An OCOS insulating film 2 is formed (FIG. 2A).

Next, a gate oxide film is formed by a thermal oxidation method.
An impurity for adjusting the threshold value is introduced by an ion implantation method. In this embodiment, the thickness of the gate oxide film is 850 Å, and the impurity is B (boron) of 4E11 cm ⁻² , 40 Ke.
Under the condition of V, it is implanted below the gate oxide film.

Next, polycrystalline Si is deposited on the gate oxide film by the LP-CVD method, impurities are implanted into the entire surface, heat treatment is performed, and a gate electrode is formed by a patterning method.

In this embodiment, P (phosphorus) is deposited at 1.5E16c after depositing 4400 Å of polycrystalline Si.
Implantation is performed at m ⁻² , 70 KeV, and heat treatment is performed at 950 ° C. for 30 minutes in an N ₂ atmosphere, followed by patterning and etching to form a gate electrode.

Here, the gate electrode may have a combination structure of a refractory metal such as W and Co and polycrystalline Si. Further, in this embodiment, in order to improve the breakdown voltage of the gate oxide film, a 350 Å thermal oxide film is formed on the gate electrode by a thermal oxidation method.

Next, an opening is made in the resist around the gate electrode 3 by a resist patterning method, and impurities are implanted. Here, impurities having a conductivity opposite to that of the well region are implanted and heat treatment is performed. In this embodiment, the well region is P-type and P (phosphorus) is 1 to 8E after heat treatment.
It is formed to have a surface concentration of 17 cm ^-3 . This region serves as an electric field relaxation layer and improves the breakdown voltage of the MOS transistor. Further, in this embodiment, B (boron) is ion-implanted into the N-type well region, and heat treatment is performed so that the surface concentration becomes 1E16 to 1E17 cm ^-3 .
An electric field relaxation layer is formed.

Next, an opening is made in the resist around the gate electrode 3 by a resist patterning method, an N-type impurity is introduced into the P-type well region, and after removing the resist, patterning is performed again. A resist around the gate electrode on the N-type well region is opened, and a P-type impurity is introduced into the N-type well region. In this embodiment, the N-type impurity is P (phosphorus) of 5E15 cm ⁻² and 95 Ke.
Injected under the condition of V, 3E15 cm a P-type impurity BF ₂
^-2 , implantation at 100 KeV. After removing the resist, heat treatment is applied in an N ₂ atmosphere at 1000 ° C. for 10 minutes to diffuse the impurities, thereby forming source and drain regions in the P-type and N-type well regions.

In this embodiment, the source and drain regions are offset by resist patterning. The offset amount is preferably 0.5 to 2.0 μm. As a method of providing an offset, side spacers may be provided on both sides of the gate electrode, and high concentration impurities may be introduced.

Next, an insulating film is deposited by the CVD method. In this embodiment, the BPSG film 4 is deposited by the normal pressure TEOS CVD method. However, the BPSG film 4 may be deposited by another CVD method or a combination of a plurality of insulating films (FIG. 2B). Subsequently, a heat treatment is applied in a N ₂ atmosphere at 1000 ° C. for 5 minutes.
The BPSG film 3 is reflowed.

Next, patterning and etching are performed in a photolithography step to open contact holes on the source and drain regions.
A metal film for wiring and electrodes is deposited by the VD method. In this embodiment, a barrier metal made of Ti and TiN is deposited, and after heat treatment is applied, Al-Si and TiN are successively formed. However, Al-Si-Cu, Al-Cu, Al-C
It is also possible to use a material such as u-Ti.

Next, a metal wiring electrode wiring 4 is formed in a photolithography process (FIG. 2C). In this embodiment, the wiring interval is 1 μm, but may be 0.5 to 5 μm.

Next, a first interlayer insulating film 5 is deposited by P-CVD. In this embodiment, a P-SiO film is deposited to a thickness of 1000 angstroms by the P-CVD method.
An N, P-SiON, or P-TEOS insulating film is also possible.

Next, the first inorganic SOG film 6 is formed by spin coating.
Is applied. In this embodiment, the inorganic SOG film is formed by applying 2200 Å (FIG. 2D).

Thereafter, a heat treatment is applied at 400 ° C. for 30 minutes, and then a second interlayer insulating film 7 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
000 angstroms deposited, but P-Si
N, P-SiON, a combination of multiple insulating films and P-
An insulating film formed by the TEOS method is also possible.

Next, the second inorganic SOG is again applied by the spin coating method.
The film 8 is applied. In this embodiment, the inorganic SOG is 2200
It is formed by Angstrom coating. Then 40
Heat treatment is performed at 0 ° C. for 30 minutes, and then a third interlayer insulating film 9 is deposited by a P-CVD method. In this embodiment, P-S
An iO film is deposited at 2000 Å.

According to the present invention, the recess formed between the metal electrode wirings 4 is formed as an insulating film / inorganic SOG film / insulating film / inorganic S
It is characterized by being embedded with an OG film.

Further, in the present invention, a P-SiO film is used as an insulating film between the first inorganic SOG film and the second inorganic SOG film, and the film forming conditions are 450 ° C., SiH ₄ and N 2.
It is deposited using ₂ O so that the film stress is in the compression direction.

Since the inorganic SOG film has a film stress in the tensile direction, the P-SiO film located between the inorganic SOG films is formed for the purpose of relaxing the stress of the inorganic SOG film.

The film quality of the P-SiO film can be changed in the intensity and direction of the stress by changing the film thickness of the inorganic SOG film for filling the contact holes and between the wirings. Can be changed. The amount of the concave portion generated due to the difference in the wiring interval, and first and second inorganic SOGs for embedding the concave portion.
FIG. 5 shows the relationship between the film thicknesses.

The thickness of the inorganic SOG film is 1500 to 4000
This is effective for improving the flatness of the interlayer insulating film between the wirings during angstrom. In this embodiment, the inorganic SOG film thickness is 2
Although it is formed at 200 Å, it is effective to fill the recess when the wiring interval is 0.5 to 2.0 μm. In particular, when the wiring interval is 0.5 to 1.5 μm, the recess amount is 0. It is suppressed to 2 μm or less, and the flatness is greatly improved.

Thereafter, in a photolithography process, through holes required for conduction with the first metal wiring are opened in the interlayer insulating film by dry etching, and then metal for multilayer wiring is deposited by PVD. A multilayer metal wiring is formed by patterning and etching, or a reflective electrode is formed by performing a CMP process after using an Al reflow method (FIG. 7).

A liquid crystal panel is formed by sandwiching a liquid crystal 65 between the active matrix substrate formed as described above and a counter substrate 63 provided with a transparent electrode 64 (FIG. 7). As the liquid crystal material, a polymer network liquid crystal PNLC is used.
Etc. may be used.

The technical effect of this embodiment is that the interlayer insulating film becomes very flat to the extent that the CMP operation in the interlayer insulating film forming step becomes unnecessary, and therefore, the formation of a highly reliable multilayer metal wiring, It is possible to form reflective electrodes with high reflectivity,
Further, a semiconductor device with a high degree of integration and a display device with a high pixel density can be formed, so that performance and yield can be improved.

(Third Embodiment) FIG. 3 is a drawing which best illustrates the features of the third embodiment of the present invention. FIG. 3 shows a method of forming an interlayer insulating film in a semiconductor device using the present invention. FIG. 7 is a cross-sectional view of a process flow showing embedding of a part.

In FIG. 3, 1 is a semiconductor substrate and 2 is a LO
COS insulating layer, 3 a gate electrode, 4 a BPSG film, 5 a metal wiring electrode, 6 a first interlayer insulating film, 7 a first inorganic SO
G film, 50 is UV light, 9 is a second inorganic SOG film, 10 is a second interlayer insulating film, 11 is a third inorganic SOG film, and 12 is a third interlayer insulating film.

A third embodiment of the present invention will be described with reference to FIG.

First, a method for forming a MOS transistor in a semiconductor substrate will be described below. Impurity concentration 1E14 ~
A thermal oxide film (pad oxide film) is formed on the semiconductor substrate 1 of 1E15 cm ^-3 by a thermal oxidation method, and a SiN film is deposited thereon by an LP-CVD method. In this embodiment, the thermal oxide film is
An Angstrom, 2000 Angstrom SiN film is deposited.

Next, part of the SiN film is removed by patterning and etching in a photolithography step, P (phosphorus) is implanted by an ion implantation method, and subsequently heat treatment is applied to form a well region. In this embodiment, the concentration of the impurity region formed by ion implantation is 1E15 to 1E.
P is injected into 1.8E12cm- ^{2 so} as to be 17cm- ³ ,
The heat treatment is performed at 1000 ° C. for 60 minutes in an N ₂ / O ₂ atmosphere.

Further, in this embodiment, after the SiN film is entirely removed, B (boron) is ion-implanted and then heat treatment is applied to form well regions having different conductivity. It is formed to the same extent as the well region.

Next, a SiN film is deposited again by the LP-CVD method, patterned by a photolithography process, a part of the SiN film is removed, and a thermal oxide film is formed by a thermal oxidation method. In this embodiment, the SiN film thickness is 1
The thickness is 500 angstroms and the thermal oxide film thickness is 8000 angstroms. Subsequently, the SiN film is entirely removed and L
An OCOS insulating film 2 is formed (FIG. 3A).

Next, a gate oxide film is formed by a thermal oxidation method.
An impurity for adjusting the threshold value is introduced by an ion implantation method. In this embodiment, the thickness of the gate oxide film is 850 Å, and the impurity is B (boron) of 4E11 cm ⁻² , 40 Ke.
Under the condition of V, it is implanted below the gate oxide film.

Next, polycrystalline Si is deposited on the gate oxide film by the LP-CVD method, impurities are implanted into the entire surface, heat treatment is performed, and then a gate electrode 3 is formed by a patterning method (FIG. 3). (A)).

In this embodiment, P (phosphorus) is deposited to 1.5E16c after depositing 4400 Å of polycrystalline Si.
Implantation is performed at m ⁻² and 70 KeV, and heat treatment is performed at 950 ° C. for 30 minutes in an N ₂ atmosphere, followed by patterning, etching, and etching to form a gate electrode 3.

Here, the gate electrode 3 may have a combination structure of a refractory metal such as W and Co and polycrystalline Si. Further, in this embodiment, in order to improve the breakdown voltage of the gate oxide film, a 350 Å thermal oxide film is formed on the gate electrode 3 by a thermal oxidation method.

Next, an opening is formed in the resist around the gate electrode 3 by a resist patterning method, and impurities are implanted. Here, impurities having a conductivity opposite to that of the well region are implanted and heat treatment is performed. In this embodiment, the well is P-type and P (phosphorus) is 1-8E17 after heat treatment.
It is formed to have a surface concentration of cm ^-3 . This region serves as an electric field relaxation layer and improves the breakdown voltage of the MOS transistor. Further, in this embodiment, B (boron) ions are implanted into the N-type well region, and
A heat treatment is performed so as to be E16 to 1E17 cm ^-3 to form an electric field relaxation layer.

Next, an opening is made in the resist around the gate electrode 3 by a resist patterning method, an N-type impurity is introduced into the P-type well region, and after the resist is removed, patterning is performed again. A resist around the gate electrode on the N-type well region is opened, and a P-type impurity is introduced into the N-type well region. In this embodiment, the N-type impurity is P (phosphorus) of 5E15 cm ⁻² and 95 Ke.
Injected under the condition of V, 3E15 cm a P-type impurity BF ₂
^-2 , implantation at 100 KeV. After removing the resist, heat treatment is applied in an N ₂ atmosphere at 1000 ° C. for 10 minutes to diffuse the impurities, thereby forming source and drain regions in the P-type and N-type well regions.

In this embodiment, the source and drain regions are offset by resist patterning. The offset amount is preferably 0.5 to 2.0 μm. As a method of providing an offset, side spacers may be provided on both sides of the gate electrode, and high concentration impurities may be introduced.

Next, an insulating film is deposited by the CVD method. In this embodiment, the BPSG film 4 is deposited by the normal pressure TEOS CVD method. However, an insulating film formed by another CVD method or a combination of a plurality of insulating films may be deposited (FIG. 3A). Subsequently, a heat treatment is applied in a N ₂ atmosphere at 1000 ° C. for 5 minutes.
The BPSG film 4 is reflowed.

Next, patterning and etching are performed in a photolithography step to open contact holes on the source and drain regions.
A metal film for wiring and electrodes is deposited by the VD method. In this embodiment, a barrier metal made of Ti and TiN is deposited, and after heat treatment is applied, Al-Si and TiN are successively formed. However, Al-Si-Cu, Al-Cu, Al-C
It is also possible to use a material such as u-Ti.

Next, a metal wiring electrode wiring 5 is formed by a photolithography process (FIG. 3A). In this embodiment, the wiring interval is 1 μm, but may be 0.5 to 5 μm.

Next, a first interlayer insulating film 6 is deposited by P-CVD. In this embodiment, a P-SiO film is deposited to a thickness of 1000 angstroms by the P-CVD method.
An N, P-SiON, or P-TEOS insulating film is also possible.

Next, the first inorganic SOG film 7 is formed by spin coating.
Is applied. In this embodiment, the inorganic SOG film is formed by applying 2200 angstroms. 172
Irradiation with UV light 50 having a wavelength of nm
The second inorganic SOG film 9 is formed by applying a film of 2200 Å. Here, instead of the 172 nm wavelength UV light, 185 nm and 254 nm wavelength UV light, O
Irradiation with _two plasmas has the same effect on the surface modification of the SOG film.

Thereafter, a heat treatment is applied at 400 ° C. for 30 minutes, and subsequently, a second interlayer insulating film 10 is deposited by the P-CVD method. In this embodiment, a P-SiO film is deposited by 2,000 angstroms by the P-CVD method.
N, P-SiON, a combination of multiple insulating films and P-
An insulating film formed by the TEOS method is also possible.

Next, the third inorganic SOG is again applied by the spin coating method.
The film 11 is applied. In this embodiment, the inorganic SOG film is
It is formed by applying 00 angstrom. afterwards,
A heat treatment is performed at 400 ° C. for 30 minutes, and then the third interlayer insulating film 12 is deposited by the P-CVD method. In this embodiment,
A P-SiO film is deposited at 2000 angstroms.

In the present invention, the recess formed when the gate electrode 3 and the metal wiring electrode 6 are brought into contact with each other is filled with an insulating film / inorganic SOG film / insulating film / inorganic SOG film, and the surface of the interlayer insulating film requires CMP. The feature is that the flatness is remarkably enhanced to a level that does not.

Further, in the present invention, a P-SiO film is used as an insulating film between the first inorganic SOG film and the second inorganic SOG film, and the film forming conditions are 450 ° C., SiH ₄ and N 2.
It is deposited using ₂ O so that the film stress is in the compression direction.

Since the inorganic SOG film has a film stress in the tensile direction, the P-SiO film located between the inorganic SOG films is formed for the purpose of relaxing the stress of the inorganic SOG film.

The quality and the direction of the stress of the P-SiO film can be changed by changing the film thickness of the inorganic SOG film for filling the contact holes and between the wirings. Can be changed. FIGS. 6A, 6B, 6C, and 6C show the relationship between the amount of the concave portion generated at the step portion and the film thickness of the first, second, and third inorganic SOGs for embedding the concave portion. Shown in

The thickness of the inorganic SOG film is 1500 to 4000
This is effective for improving the flatness of the interlayer insulating film during angstrom. In this embodiment, the inorganic SOG film is formed with a thickness of 2200 angstroms. However, when the contact opening diameter is in the range of 0.5 to 1.6 μm, it is effective in filling the concave portion. When the thickness is .about.1.2 .mu.m, the concave amount is scarcely recognized, and is completely improved to a region very close to flattening (FIG. 6A).

The amount of recess due to the wiring interval is also 0.5 to 3 μm.
m, and especially between 0.5 and 2 μm, it is also improved to a region very close to complete flattening (FIG. 6).
(B)).

Further, the first from the surface of the semiconductor substrate 1
In order to eliminate the concave amount of both the contact hole and the wiring interval formed by the step amount up to the interlayer insulating film 7, the step amount is 0.5 to
At 2.0 μm, there is a remarkable effect, and when it is between 0.5 and 1.5 μm, it is possible to increase even to complete flattening (FIG. 6).
(C)).

Thereafter, in a photolithography process, through holes required for conduction with the first metal wiring are opened in the interlayer insulating film by dry etching, and a metal for multilayer wiring is deposited by PVD. A multilayer metal wiring is formed by patterning and etching, or a reflective electrode is formed by performing a CMP process after using an Al reflow method (FIG. 7).

A liquid crystal panel is formed by sandwiching a liquid crystal 65 between the active matrix substrate formed as described above and a counter substrate 63 provided with a transparent electrode 64 (FIG. 7). As the liquid crystal material, a polymer network liquid crystal PNLC is used.
Etc. may be used.

The technical effect of this embodiment is that the interlayer insulating film becomes very flat to the extent that the CMP work in the interlayer insulating film forming step becomes unnecessary, so that a highly reliable multilayer metal wiring can be formed, It is possible to form reflective electrodes with high reflectivity,
Further, a semiconductor device with a high degree of integration and a display device with a high pixel density can be formed, so that performance and yield can be improved.

(Embodiment A) Hereinafter, embodiments of the present invention will be described with reference to a plurality of liquid crystal panels, but the present invention is not limited to each embodiment. It goes without saying that the effect is increased by combining the mutual forms of technology. Although the structure of the liquid crystal panel is described using a semiconductor substrate, the structure is not limited to the semiconductor substrate, and the structure described below may be formed on a normal transparent substrate. . The liquid crystal panels described below are all of a MOSFET type or a TFT type, but may be of a two-terminal type such as a diode type. In addition, the liquid crystal panel described below can be used as a display device for home televisions, projectors, head mounted displays, 3D video game machines, laptop computers, electronic organizers, video conferencing systems, car navigation systems, airplane panels, etc. It is valid.

FIG. 9 shows a cross section of the liquid crystal panel of this embodiment. In the figure, reference numeral 301 denotes a semiconductor substrate;
2 ′ are p-type and n-type wells, 303 and 30 respectively
3 'and 303 "are source regions of the transistor, 304 is a gate region, and 305, 305' and 305" are drain regions.

As shown in FIG. 9, since a high voltage of 20 to 35 V is applied to the transistor in the display region, the source and drain layers are not formed in a self-aligned manner with respect to the gate 304, and the transistor is offset. , a source region 303 therebetween ', the drain region 305' as shown in a low concentration in the p-well n ^- layer of low concentration in the n-well p ^- layer is provided. By the way, the offset amount is 0.5-2.0μ
m is preferred. On the other hand, a part of the peripheral circuit is shown in FIG.
Although not shown as 0, in some peripheral circuits, source and drain layers are formed in a self-aligned manner at the gate.

Here, the offset of the source and the drain has been described. However, it is effective to change not only the presence or absence of the offset but also the offset amount according to the withstand voltage and to optimize the gate length. This is because a part of the peripheral circuit is a logic circuit, and this part is generally 1.5 to 5V.
Since the system drive is sufficient, the self-aligned structure is provided to reduce the size of the transistor and improve the driving force of the transistor. The substrate 1 is made of a p-type semiconductor, the substrate has a minimum potential (usually a ground potential), and the n-type well has a voltage applied to the pixel, that is, 20 in the case of a display region.
A logic drive voltage of 1.5 to 5 V is applied to the logic portion of the peripheral circuit. With this structure, it is possible to configure an optimum device according to each voltage, and it is possible to realize not only a reduction in chip size but also a high pixel display by improving a driving speed.

In FIG. 9, reference numeral 306 denotes a field oxide film; 310, a source electrode connected to a data line;
11 is a drain electrode connected to the pixel electrode, 312 is a pixel electrode also serving as a reflecting mirror, 307 is a light shielding layer covering a display area and a peripheral area, and is suitably made of Ti, TiN, W, Mo or the like.
As shown in FIG. 9, the light-shielding layer 307 is covered in the display region except for a connection portion between the pixel electrode 312 and the drain electrode 311. In the region where the wiring capacitance is heavy, the light-shielding layer 307 is excluded, and in the portion where the light-shielding layer 307 is exposed to high-speed signals, illumination light is mixed in. The device is designed so that it can be transferred. 308 is a light shielding layer 30
7, a flattening process is performed on the P-SiO layer 318 by SOG on the P-SiO layer 318, and the P-SiO layer 318 is further covered with the P-SiO layer 308 to secure the stability of the insulating layer 308. .

A method for forming an interlayer insulating film when the present invention is used for the insulating film 308 in FIG. 9 will be described with reference to FIG. After forming the metal wiring, the first interlayer insulating film 6 is deposited by P-CVD. In this embodiment, the first interlayer insulating film 6 is formed by P-CVD.
Although an SiO film is deposited at a thickness of 1000 °, P-SiN,
An insulating film of the P-SiON or P-TEOS method is also possible.

Next, the first inorganic SOG film 7 is formed by spin coating.
Is applied. In this embodiment, the inorganic SOG film is formed by applying 2200 ° (FIG. 1D).

Thereafter, a heat treatment is applied at 400 ° C. for 30 minutes, and then a second interlayer insulating film 8 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
P-SiN, P-SiO
N and a combination of a plurality of insulating films or an insulating film formed by a P-TEOS method is also possible.

Next, the second inorganic SOG is again formed by the spin coating method.
The film 9 is applied. In this embodiment, the inorganic SOG film is 220
It is formed by applying 0 °. Thereafter, a heat treatment is performed at 400 ° C. for 30 minutes, and then the third interlayer insulating film 10 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
000Å deposited.

The present invention is characterized in that a recess formed when the gate electrode 3 is brought into contact with the metal wiring electrode 6 is filled with an insulating film / an inorganic SOG film / an insulating film / an inorganic SOG film. FIG. 4 shows the relationship between the amount of the above-mentioned concave portion generated depending on the size of the contact hole and the thickness of the first and second inorganic SOG films for filling the concave portion. The thickness of the inorganic SOG film is 150
When the thickness is in the range of 0 to 4000 °, it is effective for improving the flatness of the interlayer insulating film. In this embodiment, the thickness of the inorganic SOG film is 2200
The contact opening diameter is 0.5 to 1.4.
When the contact opening diameter is 0.6 to 1.2 μm, the concave amount is 0.1 μm.
m or less, and the flatness is greatly improved.

In FIG. 9, reference numeral 309 denotes an insulating layer provided between the reflective electrode 312 and the light shielding layer 307.
09 serves as a charge holding capacity of the reflection electrode 312. In order to form a large capacity, in addition to SiO ₂ , a high dielectric constant P-SiN, Ta ₂ O ₅ , or a laminated film with SiO ₂ is effective. By providing the light-shielding layer 307 on a flat metal such as Ti, TiN, Mo, or W, a film thickness of about 500 to 5000 Å is preferable.

Further, 314 is a liquid crystal material, 315 is a common transparent electrode, 316 is a counter substrate, 317 and 317 'are high concentration impurity regions, 319 is a display region, and 320 is an antireflection film.

As shown in FIG. 9, the high-concentration impurity layers 317 and 317 'having the same polarity as the wells 302 and 302' formed below the transistor are formed in the periphery and the contents of the wells 302 and 302 '. Even when a high-amplitude signal is applied to the source, the well potential is fixed at a desired potential in the low-resistance layer, so that stable and high-quality image display can be realized. Further, the high-concentration impurity layers 317 and 317 'are provided between the n-type well 302' and the p-type well 302 via a field oxide film. Channel stop layer is unnecessary.

These high-concentration impurity layers 317 and 317 '
Can be performed simultaneously in the source and drain layer formation process, so the number of masks and man-hours in the fabrication process are reduced,
Cost reduction was achieved.

Reference numeral 313 denotes an antireflection film provided between the common transparent electrode 315 and the counter substrate 316. The antireflection film is configured to reduce the interface reflectance in consideration of the refractive index of the liquid crystal at the interface. Is done. In that case, an insulating film smaller than the refractive index of the counter substrate 316 and the transmission electrode 315 is preferable.

Next, a plan view of this embodiment is shown in FIG. In the figure, reference numeral 321 denotes a horizontal shift register, 322
Is a vertical shift register, 323 is an n-channel MOSF
ET, 324 is a p-channel MOSFET, 325 is a storage capacitor, 326 is a liquid crystal layer, 327 is a signal transfer switch,
328 is a reset switch, 329 is a reset pulse input terminal, 330 is a reset power supply terminal, and 331 is a video signal input terminal. The semiconductor substrate 301 is p-type in FIG. 9, but may be n-type.

The well region 302 ′ is
And the opposite conductivity type. Therefore, in FIG. 9, the well region 302 is p-type. p-type well region 302
It is preferable that impurities are implanted into the n-type well region 302 ′ at a higher concentration than the semiconductor substrate 301.
The impurity concentration of the semiconductor substrate 301 is 10 ¹⁴ to 10 ¹⁵ (cm
^{In the case of -3} ), the impurity concentration of the well region 302 is 10 ¹⁵ to
10 ¹⁷ (cm ⁻³ ) is desirable.

The source electrode 310 is connected to a data line to which a display signal is sent, and the drain electrode 311 is connected to the pixel electrode 3.
12 is connected. These electrodes 310 and 311 usually have Al, AlSi, AlSiCu, AlGeCu, Al
Cu wiring is used. If a via metal layer made of Ti and TiN is used for the contact surface between the lower part of these electrodes 310 and 311 and the semiconductor, the contact can be stably realized. Also, the contact resistance can be reduced. The pixel electrode 312 has a flat surface and is desirably a high-reflection material. Al, AlSi, AlSiCu, AlGeCu, A
It is possible to use materials such as Cr, Au, and Ag other than 1C. Further, in order to improve flatness, the pixel electrode 3
12 surface is subjected to chemical mechanical polishing (CM
P) method.

The holding capacitor 325 is a capacitor for holding a signal between the pixel electrode 312 and the common transparent electrode 315. A substrate potential is applied to the well region 302. In the present embodiment, the transmission gate configuration of each row is
The first row from the top is the n-channel MOSFET 323
The order of the adjacent rows is changed so that the lower row is the p-channel MOSFET 324 and the lower row is the p-channel MOSFET 324, and the lower row is the n-channel MOSFET 323. As described above, not only the power supply line is brought into contact with the periphery of the display area in the stripe well, but also a thin power supply line is provided in the display area to make contact.

At this time, the stabilization of the well resistance is key. Therefore, in the case of a p-type substrate, a configuration is adopted in which the contact area or the number of contacts inside the display region of the n-well is increased compared to the contact of the p-well. Since the p-well has a constant potential in the p-type substrate, the substrate plays a role as a low-resistance body. Therefore, the influence of the swing due to the input and output of the signal to the source and drain of the n-well having the island shape tends to be large, but this can be prevented by increasing the contact from the upper wiring layer. As a result, stable and high-quality display can be realized.

A video signal (a video signal, a pulse-modulated digital signal, etc.) is input from a video signal input terminal 331, and opens and closes a signal transfer switch 327 in response to a pulse from the horizontal shift register 321. Output. From the vertical shift register 322, a high pulse is applied to the gate of the n-channel MOSFET 323 and a low pulse is applied to the gate of the p-channel MOSFET in the selected row.

As described above, the switch of the pixel portion is constituted by a single-crystal CMOS transmission gate, and the signal written to the pixel electrode has the advantage that the signal of the source can be fully written without depending on the threshold value of the MOSFET. Have.

Further, since the switch is composed of a single crystal transistor, there is no unstable behavior at the crystal grain boundary of the polysilicon-TFT, and high-speed driving with high reliability and no variation can be realized.

Next, the configuration of the panel peripheral circuit will be described with reference to FIG.
1 will be described. In FIG. 11, 337 is a display area of a liquid crystal element, 332 is a level shifter circuit, 333 is a video signal sampling switch, 334 is a horizontal shift register, 335 is a video signal input terminal, and 336 is a vertical shift register.

With the above-described configuration, a logic circuit such as a shift register for both H and V is connected to the video signal input terminal 3
Since an amplitude of about 35 to 25 V and 30 V is supplied,
It can be driven at an extremely low value of about 1.5 to 5 V, and high speed and low voltage consumption can be achieved. Here, the horizontal and vertical SR are
The scanning direction can be bi-directionally controlled by a selection switch, so it is possible to respond to changes in the arrangement of optical systems, etc. without changing the panel, and the same panel can be used for different series of products, reducing cost. There are merits that can be achieved. In FIG. 11, the video signal sampling switch is
Although a one-transistor one-transistor configuration has been described, it is needless to say that the input video lines can all be written to signal lines by using a CMOS transmission gate configuration.

Further, when the CMOS transmission gate structure is used, there is a problem that a video signal is fluctuated due to a difference in the area between the NMOS gate and the PMOS gate and the overlap capacitance between the gate and the saw drain. This can be prevented by connecting the source and the drain of the MOSFET having a gate amount of about 1/2 of the gate amount of the MOSFET of the sampling switch of each polarity to the signal line, respectively, and applying a reverse phase pulse, thereby preventing the swing. A very good video signal was written to the signal line. As a result, higher-quality display is possible.

Next, the direction in which the video signal and the sampling pulse are accurately synchronized will be described with reference to FIG. For this purpose, it is necessary to change the delay amount of the sampling pulse. 342 is a pulse delay inverter, 343 is a switch for selecting which delay inverter to select, 344 is an output whose delay amount is controlled, 345 is a capacity (outB is a reverse phase output, o
ut is an in-phase output). 346 is a protection circuit.

From SEL1 (SEL1B) to SEL3 (S
EL3B) can select how many passes through the delay inverter 342.

Since this synchronizing circuit is built in the panel, the delay amount of the pulse from the outside of the panel becomes
R. G. FIG. In the case of the B3 plate panel, even if the symmetry is lost due to the jig or the like, the symmetry can be adjusted by the selection switch. G. FIG. B
A good display image with no displacement due to the high pulse phase range was obtained. Needless to say, it is also effective to incorporate a temperature measuring diode inside the panel and to correct the temperature by referring to the delay amount from a table based on the output of the diode.

Next, the relationship with the liquid crystal material will be described.
Although FIG. 9 shows a flat counter substrate structure, the common electrode substrate 316 is formed with irregularities in order to prevent interfacial reflection of the common transparent electrode 315, and the common transparent electrode 315 is formed on the surface thereof.
Is provided. On the opposite side of the common electrode substrate 316, an antireflection film 320 is provided. In order to form these concavities and convexities, a method in which sandblasting is performed using abrasive grains having a small particle size is also effective for increasing the contrast.

As the liquid crystal material, a polymer network liquid crystal PNLC was used. However, PDLC or the like may be used as the polymer network liquid crystal. The polymer network liquid crystal PNLC is produced by a polymerization phase separation method. A solution is prepared from the liquid crystal and a polymerizable monomer or oligomer, and the solution is injected into a cell by a usual method. Then, the liquid crystal and the polymer are phase-separated by UV polymerization, thereby forming a polymer in the liquid crystal in a network. PNLC has many liquid crystals (70-9)
0 wt%).

In PNLC, the anisotropy of the refractive index (Δ
When a nematic liquid crystal having a high n) is used, light scattering is not strong. When a nematic liquid crystal having a large dielectric anisotropy (Δε) is used, driving can be performed at a low voltage. The size of the polymer network, that is, the center-to-center distance of the mesh is 1 to 1.5.
(Μm), the light scattering is strong enough to obtain high contrast.

Next, the relationship between the seal structure and the panel structure will be described with reference to FIG. In FIG.
351 is a seal portion, 352 is an electrode pad, and 353 is a clock buffer circuit. An amplifier unit (not shown) is used as an output amplifier at the time of panel electrical inspection.
In addition, there is an Ag paste portion (not shown) for taking the potential of the counter substrate, 356 is a display portion using a liquid crystal element, and 357 is a peripheral circuit portion such as a horizontal / vertical shift register (SR). The seal portion 351 indicates a contact area of a bonding material or an adhesive for bonding a pixel electrode 312 provided on the semiconductor substrate 301 around the display portion 356 to a glass substrate provided with the common electrode 315. After bonding by the unit 351, liquid crystal is sealed in the display unit 356 and the shift register unit 357.

As shown in FIG. 13, in this embodiment, circuits are provided both inside and outside the seal so that the total chip size is reduced. In this embodiment,
Pad drawers are concentrated on one side of the panel, but both sides on the long side can be taken out from multiple sides instead of one side, which is effective when handling high-speed clocks. .

Further, since the panel of this embodiment uses a semiconductor substrate such as a Si substrate, strong light is irradiated as in a projector, and light is applied to the side wall of the substrate.
The substrate potential may fluctuate, causing a malfunction of the panel. Therefore, the side wall of the panel and the peripheral circuit portion of the display area on the top surface of the panel are a substrate holder capable of shielding light, and the back surface of the Si substrate has a high thermal conductivity through an adhesive having a high thermal conductivity. It has a holder structure in which metals such as Cu are connected.

Next, a description will be given of a reflective electrode structure and a manufacturing method thereof, which are the points of the present embodiment. The completely flat reflective electrode structure of the present embodiment is different from the usual method of patterning and polishing a metal, in which a groove is etched in advance at an electrode pattern, and a metal film is formed there. This is a novel method of removing the metal on the region where the electrode pattern is not formed by polishing and flattening the metal on the electrode pattern. Moreover, the width of the wiring is much wider than the region other than the wiring, and the common problem of the conventional etching apparatus causes the following problem, and the structure of the present embodiment cannot be manufactured.

When the etching is performed, the polymer is deposited during the etching, and the patterning cannot be performed. Then, the conditions were changed in the oxide film type etching (CF ₄ / CHF ₃ type). (FIG. 14) total pressure (conventional)
At 1.7 torr (a), (this time) at 1.0 torr (b).

When the deposition gas CHF ₃ is exposed under the conditions shown in FIG.
Although it decreases, the difference in dimensions (loading effect) between the pattern close to the resist and the pattern far from it becomes extremely large, indicating that the pattern cannot be used.

In FIG. 14B, in order to suppress the loading effect, the pressure is gradually lowered, and when the pressure becomes 1 torr or less, the loading effect is considerably suppressed and the CHF
_By setting ₃ to zero, it was found that etching using only CF ₄ was effective.

Further, the pixel electrode region has almost no resist, and the peripheral portion is covered with the resist.
It was found that it was difficult to form the structure, and it was found that it was effective to provide a free electrode equivalent to the pixel electrode and its shape up to the periphery of the display area.

With this structure, there is no step between the conventional display portion and the peripheral portion or the seal portion, the gap accuracy is increased, the in-plane uniform pressure is increased, and unevenness during injection is reduced. Thus, an effect that high-quality image quality can be obtained with good yield was obtained.

Next, an optical system incorporating the reflection type liquid crystal panel of this embodiment will be described with reference to FIG. In FIG. 15, reference numeral 371 denotes a light source such as a halogen lamp;
Reference numeral 2 denotes a condenser lens for narrowing down a light source image, 373 and 375 denote flat convex Fresnel lenses, and 374 denotes a color separation optical element that separates light into R, G, and B, and a dichroic mirror, a diffraction grating, or the like is effective.

A mirror 376 guides each light separated into R, G, and B lights to the R, G, and B panels, and a mirror 377 illuminates a condensed beam to a reflective liquid crystal panel with parallel lights. The field lens 378 has an aperture at the position of the reflective liquid crystal element 379 described above. Reference numeral 380 denotes a projection lens that expands by combining a plurality of lenses.
Reference numeral 1 denotes a screen, which can normally provide a clear, high-contrast, bright image if it is composed of a Fresnel lens that converts projection light into parallel light and a lenticular lens that displays a wide viewing angle vertically and horizontally. . Although only one color panel is described in the configuration of FIG. 15, the space between the color separation optical element 374 and the squeezing portion 379 is separated into three colors, respectively, and a three-panel panel is arranged. Further, it is needless to say that not only three plates but also a single plate configuration is possible by providing a microlens array on the surface of the reflective liquid crystal device panel and irradiating different incident lights to different pixel regions. A voltage is applied to the liquid crystal layer of the liquid crystal element, and the light that has been specularly reflected at each pixel is transmitted through the squeezed portion 379 and projected on the screen.

On the other hand, when the voltage is not applied and the liquid crystal layer is a scatterer, the light incident on the reflection type liquid crystal element is scattered isotropically, and the angle 379 in which the aperture of the aperture shown in FIG. Except for the scattered light inside, there is no need for the projection lens. Thereby, black is displayed. As can be seen from the above optical system, no polarizing plate is required, and the entire surface of the pixel electrode enters the projection lens with a high reflectance of the signal light, so that a display 2-3 times brighter than in the past can be realized. As described in the above embodiment, anti-reflection measures are taken on the surface and the interface of the counter substrate, the noise light component is extremely small, and high contrast display can be realized. In addition, since the panel size can be reduced, all optical elements (lenses, mirrors etc.) are reduced in size, and low cost and light weight are achieved.

The color non-uniformity, luminance non-uniformity, and fluctuation of the light source can be reduced by inserting an integrator (fly-eye lens type rod type) between the light source and the optical system to thereby obtain the color non-uniformity, luminance non-uniformity on the screen. Could be solved.

A peripheral electric circuit other than the liquid crystal panel will be described with reference to FIG. In the figure, reference numeral 385 denotes a power supply, which is mainly divided into a lamp power supply and a system power supply for driving a panel and a signal processing circuit. Reference numeral 386 denotes a plug, and 387 denotes a lamp temperature detector. When there is an abnormality in the lamp temperature, the control board 388 controls the lamp to stop. This is controlled not only by the lamp but also by the 389 filter safety switch. For example, if a high-temperature lamp house box is to be opened, safety measures are taken to prevent the box from burning. Reference numeral 390 denotes a speaker, and 391 denotes an audio board. A processor for 3D sound, surround sound, or the like can be incorporated as required. Reference numeral 392 denotes an expansion board 1, which is an external device 396 for an S terminal for video signals, composite video and audio for video signals, and the like.
, A selection switch 395 for selecting which signal to select, and a tuner 394. A signal is sent to the extension board 2 via the decoder 393. On the other hand, the expansion board 2 mainly has a Dsub15 pin terminal for video from another system or a computer, and receives an A / D signal via a switch 450 for switching to a video signal from the decoder 393.
The signal is converted into a digital signal by the converter 451.

Reference numeral 453 denotes a main board mainly comprising a memory such as a video RAM and a CPU. The NTSC signal that has been A / D converted by the A / D converter 451 is temporarily stored in a memory and assigned to a high pixel count.
Signal processing such as interpolation of intermittent signals of empty elements that do not match the number of liquid crystal elements, and signal processing such as gamma conversion edge gradation and brightness adjustment bias adjustment suitable for liquid crystal display elements are performed. If a VGA signal is received instead of an NTSC signal, for example, a computer signal is also subjected to a resolution conversion process for a high-resolution XGA panel. The main board 453 also performs processing such as combining a computer signal with NTSC signals of a plurality of image data as well as one image data. The output of the main board 453 is subjected to serial / parallel conversion, and is supplied to the head board 454 in a form that is not easily affected by noise. The head board 454 performs parallel / serial conversion again, performs D / A conversion, and divides the data according to the number of video lines on the panel.
A signal is written to the liquid crystal panels 455, 456, and 457 of B, G, and R colors. Reference numeral 452 denotes a remote control operation panel, and a computer screen can be easily operated with the same feeling as a TV. In addition, each of the liquid crystal panels 455, 456, and 457 has the same liquid crystal device configuration including a color filter of each color.

(Embodiment B) FIG. 17 is a configuration diagram of an optical system of a front and rear projection type liquid crystal display device using the liquid crystal display device of the present invention. FIG. 17 (a) showing the top view thereof,
FIG. 17B showing a front view, and FIG. 17C showing a side view.
Consists of In the figure, reference numeral 1301 denotes a projection lens for projecting onto a screen; 1302, a liquid crystal panel with microlenses; 1303, a polarizing beam splitter (PB).
S), 1340 are R (red light) reflecting dichroic mirrors, 1341 is B / G (blue & green light) reflecting dichroic mirrors, 1342 is B (blue light) reflecting dichroic mirrors, 1343 is a high reflecting mirror that reflects all color light ,
1350 is a Fresnel lens, 1351 is a convex lens, 13
Reference numeral 06 denotes a rod-type integrator, 1307 denotes an elliptical reflector, 1308 denotes an arc lamp such as a metal halide or UHP. Here, the R (red light) reflecting dichroic mirror 1340, the B / G (blue & green light) reflecting dichroic mirror 1341, and the B (blue light) reflecting dichroic mirror 1342 have spectral reflection characteristics as shown in FIG. doing. These dichroic mirrors are arranged three-dimensionally together with the high-reflection mirror 1343 as shown in the perspective view of FIG. 19, and separate white illumination light into RGB as described later.
Each primary color light illuminates the liquid crystal panel 1302 from three-dimensionally different directions.

Here, a description will be given according to the progress of the light beam. First, the light beam emitted from the lamp 1308 of the light source is white light, and is condensed by the elliptical reflector 1307 at the entrance of the integrator 1306 in front of the light. As the reflection proceeds, the spatial intensity distribution of the light beam is made uniform. The light beam emitted from the integrator 1306 is the convex lens 1
351 and the Fresnel lens 1350 are converted into a parallel light flux in the x-axis direction (reference to the front view in FIG. 17B), and first reach the B-reflecting dichroic 19-ick mirror 1342. This B reflection dichroic mirror 1342 reflects only the B light (blue light), and is in the z-axis direction, that is, the lower side (FIG. 17).
(Refer to the front view of (b)), the light is directed toward the R reflection dichroic mirror 1340 at a predetermined angle with respect to the z axis. On the other hand, the color light (R / G light) other than the B light passes through the B reflection dichroic mirror 1342, is reflected by the high reflection mirror 1343 at right angles in the z-axis direction (downward), and also travels toward the R reflection dichroic mirror 1340. . Here, both the B-reflection dichroic mirror 1342 and the high-reflection mirror 1343 convert the light flux (x-axis direction) from the integrator 1306 into the z-axis direction (lower side) based on the front view of FIG. The high-reflection mirror 1343 has an inclination of exactly 45 ° with respect to the xy plane about the y-axis direction as a rotation axis. On the other hand, the B reflection dichroic mirror 1342 also has x
The angle is set to be shallower than 45 ° with respect to the −y plane. Accordingly, the R / G light reflected by the high reflection mirror 1343 is reflected at a right angle in the z-axis direction, while
The B light reflected by the B reflection dichroic mirror 1342 travels downward at a predetermined angle (tilt in the xz plane) with respect to the z axis. Here, the liquid crystal panel 13 of B light and R / G light
In order to match the illumination range on the liquid crystal panel 1302, the shift amount and the tilt amount of the high-reflection mirror 1343 and the B-reflection dichroic mirror 1342 are selected so that the principal rays of each color light intersect on the liquid crystal panel 1302.

Next, as described above, the downward direction (z-axis direction)
The R / G / B light directed to is directed to the R reflection dichroic mirror 1340 and the B / G reflection dichroic mirror 1341, which are the B reflection dichroic mirror 134.
2 and the lower side of the high reflection mirror 1343,
The G reflection dichroic mirror 1341 is disposed at an angle of 45 ° with respect to the x-z plane with the x axis as the rotation axis, and the R reflection dichroic mirror 1340 is also positioned with respect to the xz plane with the x axis direction as the rotation axis. The angle is set shallower than 45 °. Therefore, of the R / G / B light incident on these, first, the B / G light is converted to the R reflection dichroic mirror 13.
40, the B / G reflecting dichroic mirror 13
41, the beam is reflected at right angles in the y-axis + direction,
After being polarized through 3, the liquid crystal panel 1302 arranged horizontally on the xz plane is illuminated.

Among them, the B light is as described above (FIG. 17).
17 (a) and FIG. 17 (b)), since the light is traveling at a predetermined angle (tilt in the xz plane) with respect to the x-axis, the light is reflected by the B / G reflection dichroic mirror 1341 and then moved to the y-axis. The liquid crystal panel 13 maintains a predetermined angle (tilt in the xy plane) with respect to the liquid crystal panel 13 as an incident angle (in the xy plane direction).
Illuminate 02.

The G light is reflected at right angles by the B / G reflection dichroic mirror 1341, travels in the positive y-axis direction, is polarized through the PBS 1303,
That is, the liquid crystal panel 1302 is illuminated vertically. Also, as described above, the R light is reflected in the y-axis + direction by the R reflection dichroic mirror 1340 by the R reflection dichroic mirror 1340 disposed in front of the B / G reflection dichroic mirror 1341 as described above. )
As shown in (side view), a predetermined angle (y
(−z-plane tilt), advance in the y-axis + direction, and
After being polarized through the liquid crystal panel 1302, the liquid crystal panel 1302 is illuminated with an angle with respect to the y-axis as an incident angle (y-z plane direction). Further, similarly to the above, the liquid crystal panel 1 of each color of RGB is used.
In order to make the illumination ranges on 302 the same, the shift amount and the tilt amount of the B / G reflection dichroic mirror 1341 and the R reflection dichroic mirror 1340 are selected so that the principal rays of each color light intersect on the liquid crystal panel 1302. . Further, as shown in FIG. 18A, the cut wavelength of the B reflection dichroic mirror 1341 is 480 nm,
As shown in FIG. 18B, the cut wavelength of the B / G reflection dichroic mirror 1341 is 570 nm.
As shown in (c), the R reflection dichroic mirror 13
Since the cut wavelength of 40 is 600 nm, unnecessary orange light passes through the B / G reflection dichroic mirror 1341 and is discarded. Thereby, an optimal color balance can be obtained.

As will be described later, the liquid crystal panel 1302
The RGB light is reflected and polarization-modulated by the PBS 1303.
The light flux reflected on the PBS surface 1303a of the PBS 1303 in the + x-axis direction becomes image light, and the projection lens 13
01 is enlarged and projected on a screen (not shown). By the way, each RG that illuminates the liquid crystal panel 1302
Since the B light has a different incident angle, each of the RGB light reflected from the B light has a different emission angle.
As 301, a lens having a lens diameter and an opening large enough to capture all of them is used. However, the inclination of the light beam incident on the projection lens 1301 is made parallel by each color light passing twice through the micro lens, and the inclination of the light incident on the liquid crystal panel 1302 is maintained. However, as shown in FIG. 29, in the transmission type of the conventional example, the light beam emitted from the liquid crystal panel spreads larger due to the condensing action of the microlens, so the projection lens for capturing this light beam is even larger. The numerical aperture is determined,
It was an expensive lens. However, in this example, since the spread of the light beam from the liquid crystal panel 2 is relatively small in this manner, a sufficiently bright projection image can be obtained on a screen even with a projection lens having a smaller numerical aperture, and a less expensive projection lens can be obtained. Can be used. Further, an example of a stripe type display method in which the same colors are arranged in the vertical direction shown in FIG. 30 can be used in the present embodiment, but is not preferable in the case of a liquid crystal panel using a microlens as described later. .

Next, the liquid crystal panel 13 of the present invention used here
02 will be described. FIG. 20 shows the liquid crystal panel 1302.
20 (corresponding to the yz plane in FIG. 19).
In the figure, 1321 is a microlens substrate, 1322
Is a micro lens, 1323 is a sheet glass, 1324
Denotes a transparent counter electrode, 1325 denotes a liquid crystal layer, 1326 denotes a pixel electrode, 1327 denotes an active matrix drive circuit unit,
328 is a silicon semiconductor substrate. Reference numeral 1252 denotes a peripheral seal portion. Here, in the present embodiment, R,
G and B pixels are integrated into one panel, and the size of one pixel is reduced. Therefore, it is important to increase the aperture ratio, and the reflective electrode must be present in the range of the collected light. The micro lens 1322
The pixel electrode 1 is formed on the surface of a glass substrate (alkali glass) 1321 by a so-called ion exchange method.
A two-dimensional array structure is formed at a pitch twice the pitch of 326.

The liquid crystal layer 1325 employs a so-called ECB mode nematic liquid crystal such as DAP or HAN adapted to a reflection type, and a predetermined alignment is maintained by an alignment layer (not shown). Since the voltage value is lower than in the other embodiments and the accuracy of the potential of the pixel electrode 1326 becomes more important, the circuit and configuration of the present invention are effective, and the number of pixels in a single plate is large, and thus the video line , The reduction of the coupling capacity of the other embodiments is very effective. The pixel electrode 1326 is made of Al and also serves as a reflecting mirror, and is subjected to a so-called CMP process in a final step after patterning in order to improve surface properties and improve reflectivity (details will be described later).

Active matrix drive circuit section 132
Reference numeral 7 denotes a semiconductor circuit provided on a so-called silicon semiconductor substrate 1328. A method of forming an interlayer insulating film when the present invention is used in forming an interlayer insulating film in the semiconductor circuit will be described with reference to FIG. . After forming the metal wiring, a first interlayer insulating film 6 is deposited by P-CVD. In this embodiment, a P-SiO film is deposited at a thickness of 1000 ° by P-CVD, but P-SiN, P- SiON, P-TE
An insulating film formed by the OS method can be used.

Next, the first inorganic SOG film 7 is formed by spin coating.
Is applied. In this embodiment, the inorganic SOG film is formed by applying 2200 ° (FIG. 1D).

Thereafter, a heat treatment is applied at 400 ° C. for 30 minutes, and subsequently, a second interlayer insulating film 8 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
P-SiN, P-SiO
N and a combination of a plurality of insulating films or an insulating film formed by a P-TEOS method is also possible.

Next, the second inorganic SOG is again formed by the spin coating method.
The film 9 is applied. In this embodiment, the inorganic SOG film is 220
It is formed by applying 0 °. Thereafter, a heat treatment is performed at 400 ° C. for 30 minutes, and then the third interlayer insulating film 10 is deposited by the P-CVD method. In this embodiment, the P-SiO film is
000Å deposited.

The present invention is characterized in that a recess formed when the gate electrode 3 is brought into contact with the metal wiring electrode 6 is filled with an insulating film / an inorganic SOG film / an insulating film / an inorganic SOG film. FIG. 4 shows the relationship between the amount of the above-mentioned concave portion generated depending on the size of the contact hole and the thickness of the first and second inorganic SOG films for filling the concave portion. The thickness of the inorganic SOG film is 150
When the thickness is in the range of 0 to 4000 °, it is effective for improving the flatness of the interlayer insulating film. In this embodiment, the thickness of the inorganic SOG film is 2200
The contact opening diameter is 0.5 to 1.4.
When the contact opening diameter is 0.6 to 1.2 μm, the concave amount is 0.1 μm.
m or less, and the flatness is greatly improved.

The semiconductor circuit is connected to the pixel electrode 1326
Are driven by an active matrix, and a gate line driver (vertical register and the like) and a signal line driver (horizontal register and the like) (not shown) are provided in the periphery of the circuit matrix (details will be described later). The peripheral driver and the active matrix drive circuit are configured to write the RGB primary color video signals to predetermined RGB pixels, and the pixel electrodes 132
Reference numeral 6 denotes a primary color video signal which does not have a color filter, but is distinguished as each RGB pixel by a primary color video signal written by the active matrix driving circuit.
A GB pixel array is formed.

Here, looking at the G light illuminating the liquid crystal panel 1302, the G light is P
The liquid crystal panel 13 after being polarized by the BS 1303
02 perpendicularly. An arrow G (in / out) in the drawing shows an example of a ray incident on one micro lens 1322a. As shown in the figure, the G light beam is collected by the micro lens 1322, and illuminates the G pixel electrode 1326g. Then, the light is reflected by the pixel electrode 1326g made of Al, and is emitted to the outside of the panel again through the same micro lens 1322a. When the G light (polarized light) reciprocates through the liquid crystal layer 1325 in this manner, the G light (polarized light) is modulated by the operation of the liquid crystal due to the electric field formed between the pixel electrode 1326g and the counter electrode 1324 by a signal voltage applied to the pixel electrode 1326g. Exit the liquid crystal panel,
It returns to PBS1303.

Here, the PBS surface 1 depends on the degree of modulation.
The amount of light reflected at 303a and traveling toward the projection lens 1301 changes, and so-called gray-scale gradation display of each pixel is performed. On the other hand, as described above, the cross section (y-
For R light incident from an oblique direction in the (z plane),
When attention is paid to, for example, an R ray incident on the microlens 1322b after being polarized by the PBS 1303, as shown by an arrow R (in) in the figure, the light is condensed by the microlens 1322b and is located on the left side immediately below. The R pixel electrode 1326r at the shifted position is illuminated. Then, the reflected light is reflected by the pixel electrode 1326r, and as shown in FIG.
322a and exits out of the panel (R (ou
t)).

At this time, the R light (polarized light) is also applied to the opposite electrode 13 by the signal voltage applied to the pixel electrode 1326r.
The liquid crystal panel is modulated by the operation of the liquid crystal by an electric field corresponding to an image signal formed between the liquid crystal panel 24 and the liquid crystal panel, and is emitted from the liquid crystal panel.
It returns to PBS1303. In the subsequent process, the image light is projected from the projection lens 1301 in exactly the same manner as in the case of the G light described above. By the way, in the depiction of FIG. 20, the G light and the R light on the pixel electrode 1326g and the pixel electrode 1326r partially overlap each other and interfere with each other. This is schematically represented by the thickness of the liquid crystal layer. Is actually exaggerated, and the thickness of the liquid crystal layer is actually 1 to 5 μm.
This is very thin compared to 50-100 μm of the sheet glass 1323, and such interference does not occur regardless of the pixel size.

Next, FIG. 21 is a view for explaining the principle of color separation / color synthesis in this example. Here, FIG. 21 (a) is a schematic top view of the liquid crystal panel 1302, and FIGS. 21 (b) and 21 (c) are AA ′ (x
3 is a schematic cross-sectional view of FIG. Here, the micro lens 1322 is formed as shown in FIG.
As shown by the one-dot chain line, one for each half of two adjacent two-color pixels centering on the G light. Among them, FIG. 21C corresponds to FIG. 20 showing the yz cross section, and shows how the G light and the R light incident on each micro lens 1322 enter and exit. As can be seen from this, each G pixel electrode is disposed directly below the center of each microlens, and each R pixel electrode is disposed directly below the boundary between microlenses. Therefore, the angle of incidence of the R light is
is preferably set to be equal to the ratio of the pixel pitch (B & R pixel) to the distance between the microlens and the pixel electrode. On the other hand, FIG. 21B shows x-rays of the liquid crystal panel 1302.
This corresponds to the y section. In this xy cross section, the B pixel electrodes and the G pixel electrodes are alternately arranged in the same manner as in FIG. 21C, and each G pixel electrode is arranged immediately below the center of each microlens. The pixel electrodes are arranged immediately below the boundaries between the microlenses.

As described above, the B light illuminating the liquid crystal panel is incident on the oblique direction of the cross section (xy plane) in FIG. 17 after being polarized by the PBS 1303 as described above. In exactly the same manner, the B ray incident from each microlens 1322 is reflected by the B pixel electrode 1326b as shown in the figure, and exits from the microlens 1322 adjacent to the incident microlens 1322 in the x direction. The modulation by the liquid crystal on the B pixel electrode 1326b and the projection of the B emission light from the liquid crystal panel are the same as the above-described G light and R light.

Each B pixel electrode 1326b is disposed immediately below the boundary between the microlenses, and the incident angle of B light to the liquid crystal panel is the same as that of R light.
It is preferable to set nθ to be equal to the ratio between the pixel pitch (G & B pixel) and the distance between the microlens and the pixel electrode. By the way, in the liquid crystal panel of this example, as described above, the arrangement of each RGB pixel is RGRGRG in the z direction.
Are arranged in the x-direction, and FIG. 21 (a) shows a planar arrangement thereof. As described above, each pixel size is about half of the microlens in both the vertical and horizontal directions, and the pixel pitch is half of that of the microlens in both the x and z directions. Also,
The G pixel is also located directly below the center of the microlens in plan view, the R pixel is located between the G pixels in the z direction and at the microlens boundary, and the B pixel is located between the G pixels in the x direction and at the microlens boundary. I have. Further, the shape of one microlens unit is rectangular (double the size of a pixel).

FIG. 22 is a partially enlarged top view of the present liquid crystal panel. Here, a broken-line grid 1329 in the figure indicates a group of RGB pixels constituting one picture element. That is, when each of the RGB pixels is driven by the active matrix driving circuit unit 1327 in FIG. 20, the RGB pixel units indicated by the broken-line grid 1329 correspond to the R pixels corresponding to the same pixel position.
It is driven by a GB video signal. Here, the R pixel electrode 132
Focusing on one pixel composed of 6r, G pixel electrode 1326g, and B pixel electrode 1326b, first, R pixel electrode 1
326r is the micro lens 1 as indicated by the arrow r1.
As described above, the illumination light is illuminated with the R light obliquely incident from 322b, and the R reflected light is emitted through the microlens 1322a as indicated by an arrow r-2. B pixel electrode 132
6b denotes a micro lens 132 as indicated by an arrow b1.
As described above, the illumination light is illuminated with the B light obliquely incident from 2c, and the B reflected light is also emitted through the micro lens 1322a as shown by the arrow b2. Further, the G pixel electrode 1326g is illuminated with the G light incident vertically (in the direction toward the back of the paper) from the micro lens 1322a as described above, as indicated by the front rear arrow g12, and the G reflected light is the same micro lens 1322a. Vertically (in the direction coming out of the page).

As described above, in the present liquid crystal panel, 1
Regarding the RGB pixel units constituting one picture element, although the incident illumination position of each primary color illumination light is different, their emission is the same micro lens (1322 in this case).
a). This is also true for all other picture elements (RGB pixel units).

Therefore, as shown in FIG. 23, all the light emitted from the present liquid crystal panel is transmitted to the PBS 1303 and the projection lens 13.
When the image is projected onto the screen 1309 through the optical system 01, the position of the micro lens 1322 in the liquid crystal panel 1302 is optically adjusted so that the image is projected on the screen 1309, and the projected image becomes a micro lens lattice as shown in FIG. Each of the picture elements has a mixed state of the light emitted from the RGB pixel units constituting each picture element, that is, a picture element in a mixed color state of the same pixel. In addition, it is possible to display high quality and good color images without the so-called RGB mosaic as in the related art.

Next, as shown in FIG. 20, the active matrix drive circuit 1327 is connected to each pixel electrode 1326.
In FIG. 20, the RGB pixels constituting the picture element are simply drawn side by side on the circuit cross-sectional view of FIG. 20, but the drain of each pixel FET has a two-dimensional structure as shown in FIG. To each of the RGB pixel electrodes 1326 in a specific arrangement.

FIG. 24 is an overall block diagram of a drive circuit system of the projection type liquid crystal display device. Here, reference numeral 1310 denotes a panel driver which inverts the polarity of an RGB video signal and forms a liquid crystal drive signal obtained by a predetermined voltage amplification.
Various timing signals are formed. An interface 1312 decodes various video and control transmission signals into standard video signals and the like. Reference numeral 1311 denotes a decoder which decodes and converts a standard video signal from the interface 1312 into an RGB primary color video signal and a synchronization signal, that is, an image signal corresponding to the liquid crystal panel 1302. Reference numeral 1314 denotes a ballast for driving and lighting an arc lamp 1308 in the elliptical reflector 1307. 1
A power supply circuit 315 supplies power to each circuit block. Reference numeral 1313 denotes a controller including an operation unit (not shown), which comprehensively controls the respective circuit blocks. As described above, in the present projection type liquid crystal display device, the drive circuit system is very common as a single-panel type projector. It is possible to display a color image with a natural texture.

FIG. 26 is a partially enlarged top view of another embodiment of the liquid crystal panel of this embodiment. Here, the B pixel electrode 132 is located just below the center of the micro lens 1322.
6b, and G pixels 1326g in the left-right direction.
Are alternately arranged in the vertical direction so that the R pixels 1326r are alternately arranged in the vertical direction. Even with this arrangement,
By making the B light vertically incident and the R / G light obliquely incident (different directions at the same angle) so that the reflected light from the RGB pixel unit constituting the picture element is emitted from one common microlens, Exactly the same effect can be obtained. Further, R is located just below the center of the micro lens 1322.
Arrange the pixels and set the other color pixels in the
G and B pixels may be arranged alternately with respect to the pixels.

(Embodiment C) FIG. 27 shows another embodiment of the liquid crystal panel according to the present invention. The figure shows the liquid crystal panel 1
FIG. 320 is a partially enlarged cross-sectional view of 320. The difference from the other embodiments is as follows. First, a sheet glass 1323 is used as a facing glass substrate, and the microlenses 1220 are formed on the sheet glass 1323 by a so-called reflow method using a thermoplastic resin. I have. further,
A spacer pillar 1251 is formed in a non-pixel portion by photolithography of a photosensitive resin. The liquid crystal panel 132
FIG. 28 (a) shows a partial top view of the portion No. 0. As can be seen from this figure, the spacer pillars 1251 are formed in the non-pixel area at the corners of the microlenses 1220 at a predetermined pixel pitch. FIG. 28B is a sectional view taken along the line AA ′ passing through the spacer pillar 1251. The formation density of the spacer pillars 1251 is preferably provided in a matrix at a pitch of 10 to 100 pixels, so that both the flatness of the sheet glass 1323 and the liquid crystal injection property, which are inconsistent with the number of spacer pillars, are satisfied. Must be set. Further, in the present embodiment, the light shielding layer 1221 made of a metal film pattern is provided to prevent the leakage light from entering from each microlens boundary. As a result, a decrease in the saturation of the projected image (due to the mixing of the primary color image light) and a decrease in the contrast due to the leak light are prevented. Therefore, by using the present liquid crystal panel 1320 to configure a projection display device including the liquid crystal panel as in the present embodiment,
Further, sharp and good image quality can be obtained.

[0189]

As described above, according to the present invention, an insulating film between inorganic SOGs using an inorganic SOG film in a multilayer structure is formed by forming an interlayer insulating film in a direction to relieve the internal stress of the inorganic SOG. As a result, it is possible to form a highly reliable metal wiring and an interlayer insulating film with high flatness that do not require an etch-back process.

Further, according to the present invention, the contact opening diameter is 0.6 to 1.2 μm and the wiring interval is 0.5 to 1.5 μm.
In the case of μm, by forming an interlayer insulating film using an inorganic SOG film in a multilayer structure, flatness can be significantly improved without using a CMP process in an interlayer insulating film forming step.

Further, according to the present invention, the diameter of the contact hole is formed in the range of 0.5 to 1.2 μm, and the wiring interval is set in the range of 0.5 to 1.2 μm.
2 μm, an insulating film is formed thereon, and inorganic SO
By forming a G film and irradiating UV light or O ₂ plasma having a wavelength of 172 nm, 185 nm, or 254 nm, the surface of the inorganic SOG film is modified, the wettability is improved, and the inorganic SOG film is formed again. After that, an insulating film is deposited,
By forming an inorganic SOG film once more and depositing an insulating film thereon, it is possible to achieve almost flattening without using a CMP process in the interlayer insulating film forming process, thereby improving crack resistance. At the same time, it is possible to form a high-density and highly reliable multilayer metal wiring and a reflective electrode having a high reflectivity, thereby improving the performance and yield of a semiconductor device and a display device.

[Brief description of the drawings]

FIG. 1 is a drawing showing a method of filling a concave portion of a contact hole on an interlayer insulating film according to a first embodiment of the present invention.

FIG. 2 is a view showing a method of filling a concave portion between wirings on an interlayer insulating film according to a second embodiment of the present invention.

FIG. 3 is a view illustrating a method of embedding a step portion on an interlayer insulating film according to a third embodiment of the present invention.

FIG. 4 is a graph showing technical verification of the embedding property of a recess on a contact hole using the first embodiment of the present invention.

FIG. 5 is a graph showing technical verification of the embedment of recesses between wirings using the second embodiment of the present invention.

FIG. 6 (a) is a graph showing a technical verification of the embedding property of a concave portion on a contact hole using a third embodiment of the present invention. (B) is a graph showing technical verification of the embedding property of a recess between wirings using the third example of the present invention. (C) Using the third embodiment of the present invention,
9 is a graph showing a technical verification of the embedding property of a step portion on an interlayer insulating film.

FIG. 7 is a sectional view of a liquid crystal display device formed by using the present invention.

FIG. 8 is a diagram illustrating a conventional example.

FIG. 9 is a cross-sectional view of a liquid crystal device manufactured by CMP according to the present invention.

FIG. 10 is a schematic circuit diagram of a liquid crystal device according to the present invention.

FIG. 11 is a block diagram of a liquid crystal device according to the present invention.

FIG. 12 is a circuit diagram including a delay circuit of an input unit of the liquid crystal device according to the present invention.

FIG. 13 is a conceptual diagram of a liquid crystal panel of a liquid crystal device according to the present invention.

FIG. 14 is a graph for judging the quality of an etching process in manufacturing a liquid crystal device according to the present invention.

FIG. 15 is a conceptual diagram of a liquid crystal projector using the liquid crystal device according to the present invention.

FIG. 16 is a circuit block diagram showing the inside of the liquid crystal projector according to the present invention.

FIG. 17 is an overall configuration diagram showing an embodiment of an optical system of a projection type liquid crystal display device according to the present invention.

FIG. 18 is a spectral reflection characteristic diagram of a dichroic mirror used in an optical system of a projection type liquid crystal display device according to the present invention.

FIG. 19 is a perspective view of a color separation illumination unit of the optical system of the projection type liquid crystal display device according to the present invention.

FIG. 20 is a sectional view of one embodiment of a liquid crystal panel according to the present invention.

FIG. 21 is a diagram illustrating the principle of color separation and color synthesis of a liquid crystal panel according to the present invention.

FIG. 22 is a partially enlarged top view of the liquid crystal panel of one embodiment of the present invention.

FIG. 23 is a partial configuration diagram showing a projection optical system of a projection type liquid crystal display device according to the present invention.

FIG. 24 is a block diagram showing a drive circuit system of the projection type liquid crystal display device according to the present invention.

FIG. 25 is a partially enlarged view of a projected image on a screen of the projection type liquid crystal display device according to the present invention.

FIG. 26 is a partial sectional view of a liquid crystal panel according to an embodiment of the present invention.

FIG. 27 is a partially enlarged top view of the liquid crystal panel of one embodiment of the present invention.

FIG. 28 is a partially enlarged top view and a sectional view of a liquid crystal panel of one embodiment according to the present invention.

FIG. 29 is a conceptual diagram showing a light beam traveling direction of a liquid crystal panel of a liquid crystal device.

FIG. 30 is a configuration diagram of a color pixel of a liquid crystal panel of a liquid crystal device.

[Explanation of symbols]

In FIG. 1, 1 semiconductor substrate 2 LOCOS insulating film 3 gate electrode 4 BPSG film 5 metal wiring electrode 6 first interlayer insulating film 7 first inorganic SOG film 8 second interlayer insulating film 9 second inorganic SOG film 10 third interlayer insulating 2, a semiconductor substrate 2 LOCOS insulating film 3 BPSG film 4 metal wiring electrode 5 first interlayer insulating film 6 first inorganic SOG film 7 second interlayer insulating film 8 second inorganic SOG film 9 third interlayer insulating film In 3, 1 semiconductor substrate 2 LOCOS insulating film 3 gate electrode 4 BPSG film 5 metal wiring electrode 6 first interlayer insulating film 7 first inorganic SOG film 50 UV light or O ₂ plasma 9 second inorganic SOG film 10 second interlayer insulating In FIG. 7, reference numeral 1 denotes a semiconductor substrate 2 LOCOS insulating film 3 gate electrode 4 BPSG film 5 metal wiring Pole 6 First interlayer insulating film 7 First inorganic SOG film 8 Second interlayer insulating film 9 Second inorganic SOG film 10 Third interlayer insulating film 51 P well 52 N well 53 Gate oxide film 54 NLD 55 NSD 56 PLD 57 PSD 58 Light shielding film 59 P-SiN 60 Pixel electrode isolation region 61 Through hole 62 Reflecting electrode 63 Opposing substrate 64 Transparent electrode 65 Liquid crystal In FIG. 8, 1 Semiconductor substrate 2 LOCOS insulating film 3 Gate electrode 4 BPSG film 5 Metal wiring electrode 6 First interlayer Insulating film 7 SOG 8 second interlayer insulating film 9 concave portion 10 step 201, 501 semiconductor substrate 202, 502 scribe region 203, 503 selective oxide film 504 well 205, 505, 705, 805 first insulating film 207, 507, 707, 808 Contact 209, 509, 709, 809 Metal layer 02,603 Metal layer 601 Effective area 511 Through hole 701,802 Insulating substrate 810 Transparent insulating film 301 Semiconductor substrate 302,302 'P-type and n-type well 303,303' Source region 304 Gate region 305,305 'Drain region 306 LOCOS Insulating layer 307 Light shielding layer 308 Insulating layer 309 Plasma SiN 310 Source electrode 311 Connecting electrode 312 Reflecting electrode & pixel electrode 313 Anti-reflection film 314 Liquid crystal layer 315 Common transparent electrode 316 Counter electrode 317, 317 'High-concentration impurity region 319 Display region 320 Reflection Prevention film 321, 322 shift register 323 nMOS 324 pMOS 325 storage capacitor 327 signal transfer switch 328 reset switch 329 reset pulse input terminal 330 reset power supply terminal 331 video signal Input terminal 332 Step-up level shifter 342 Inverter for pulse delay 343 Switch 344 Output 345 Capacity 346 Protection circuit 351 Seal section 352 Electrode pad 353 Clock buffer 371 Light source 372 Condenser lens 373,375 Fresnel lens 374 Color separation optical element 376 Mirror Field lens 378 Liquid crystal device 379 Aperture section 380 Projection lens 381 Screen 385 Power supply 386 Plug 387 Lamp temperature detection 388 Control board 389 Filter safety switch 453 Main board 454 Liquid crystal panel drive head board 455, 456, 457 Liquid crystal device 1220 Micro lens (reflow heat drip type) 1251 spacer pillar 1252 peripheral seal 1301 projection lens 1302 liquid crystal with micro lens Flannel 1303 Polarizing beam splitter (PBS) 1306 Rod integrator 1307 Elliptical reflector 1308 Arc lamp 1309 Screen 1310 Panel driver 1311 Decoder 1312 Interface circuit 1314 Ballast (Arch lamp lighting circuit) 1320 Liquid crystal panel with micro lens 1321 Micro lens glass substrate 1322 Micro lens (Index distribution formula) 1323 Sheet glass 1324 Opposing transparent electrode 1325 Liquid crystal 1326 Pixel electrode 1327 Active matrix drive circuit section 1328 Silicon semiconductor substrate 1329 Basic picture element unit 1340 R reflection dichroic mirror 1341 B / G reflection dichroic mirror 1342 B reflection dichroic mirror 1343 High reflection mira 1350 Fresnel lens (second condenser lens) 1351 first condenser lens

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/316 H01L 21/316 M

Claims (12)

[Claims] 1. An interlayer insulating film of a semiconductor device, comprising: an interlayer insulating film having a structure in which an insulating film and an inorganic SOG film are formed in a plurality of layers on a metal wiring. 2. A method for forming an interlayer insulating film of a semiconductor device, comprising: repeating a step of forming an insulating film on a metal wiring and a step of forming an inorganic SOG film thereon; Forming an interlayer insulating film having a multi-layer structure. 3. The step of forming the inorganic SOG film includes the step of forming the inorganic SOG film and the step of forming a UV light on the inorganic SOG film.
Irradiating with light or O ₂ plasma;
3. The method for manufacturing a semiconductor device according to claim 2, further comprising the step of forming an OG film. 4. A method for forming an interlayer insulating film of a semiconductor device, comprising: forming a first insulating film on a metal wiring, forming a first inorganic SOG film thereon, and further forming a second inorganic SOG film thereon;
Forming a second inorganic SOG film thereon, and further forming an interlayer insulating film having a third insulating film formed thereon. 5. A method for forming an interlayer insulating layer of a semiconductor device, comprising: forming a first insulating film on a metal wiring, forming a first inorganic SOG film thereon, irradiating UV light, and 2
An inorganic SOG film is formed, a second insulating film is formed thereon, a third inorganic SOG film is further formed thereon, and then an interlayer insulating film formed with a third insulating film is formed. A method for manufacturing a semiconductor device, comprising: 6. A method for forming an interlayer insulating film of a semiconductor device, comprising: forming a first insulating film on a metal wiring, forming a first inorganic SOG film thereon, and irradiating O ₂ plasma; An interlayer insulating film in which a second inorganic SOG film is formed again, a second insulating film is formed thereon, a third inorganic SOG film is further formed thereon, and then a third insulating film is further formed Forming a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 2, wherein a film stress of the insulating film above, below, or both of the inorganic SOG film is the inorganic SOG film. A method of manufacturing a semiconductor device, wherein the semiconductor device has a stress in a direction opposite to a film stress of the semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 3, wherein the UV light is irradiated in an atmosphere containing an O ₂ component,
The method for manufacturing a semiconductor device, wherein the wavelength is one of 172 nm, 185 nm, and 254 nm. 9. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of forming a contact opening and a step of forming a wiring section, wherein said contact opening has a diameter of 0.1 mm. A method for manufacturing a semiconductor device, comprising: 6 to 1.2 μm, and the wiring interval is 0.5 to 1.5 μm. 10. A liquid crystal display device comprising the semiconductor device according to claim 1 and a liquid crystal layer. 11. A projection type liquid crystal display device using the liquid crystal display device according to claim 10. 12. The projection type liquid crystal display device according to claim 11, wherein the liquid crystal panel has at least three colors for three colors.
And separates blue light with a high reflection mirror and a blue reflection dichroic mirror, further separates red and green with a red reflection dichroic mirror and a green / blue reflection dichroic mirror, and projects each liquid crystal panel. A projection type liquid crystal display device characterized by the above-mentioned.