JP3423592B2 - Display substrate, method of manufacturing the same, liquid crystal display device, and projection type liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a substrate for a display device and
The present invention relates to a manufacturing method, a liquid crystal display device, and a projection type liquid crystal display device.

[0002]

2. Description of the Related Art A conventional liquid crystal display device is disclosed in Japanese Patent Laid-Open No. 8-17.
As described in Japanese Patent No. 9377, it is configured as follows. FIG. 6 is a plan view of a conventional liquid crystal display device, which includes a display pixel area 51, a signal / scanning drive circuit 5.
2. Dummy pixel 53. Bonding pads that draw in power or signals from the outside are not entered here, but normally bonding pads are
It is formed on the peripheral portion of the chip outside the scan drive circuit 52.

[0003]

SUMMARY OF THE INVENTION In the above conventional example,
The pixel electrode is a CMP (Chemical Mechanical)
The surface is flattened and smoothed by cal polishing, and at the same time, it is formed by being insulated and separated from the adjacent pixel electrode.

This CMP has a characteristic that the polishing rate depends on the pattern density of the polishing region, and as a result, the finished state of polishing differs between a dense pattern portion and a sparse pattern portion in the chip. There's a problem. For example, in the image display area having a small area to be polished and the bonding pad area having a large area to be polished, the polishing rate of CMP is higher in the image display area, and when the polishing amount is adjusted to the image display area, the bonding pad area is increased. However, the polishing is insufficient, and the electrode material is likely to remain between the adjacent bonding pads, and in the worst case, there is a problem that the bonding pads are short-circuited.

[0005]

[Means for Solving the Problems] To solve the above problems
As a means for achieving this, the substrate for a display device of the present invention is substantially flat.
Multiple pixel electrodes with flat surfaceImage display unit having
When,The aboveInput and output polished together with pixel electrodes
In a display device substrate having an electrode,
Around the poleThe image display sectionTo have the same polishing rate as
Placed,An electrically floating dummy electrodePrevious
Around the output electrodeDisplay device characterized by having
Substrate.

Further, the dummy electrode is made of the same material as the pixel electrode, and the dummy electrode has a plurality of dummy electrodes.
The dummy electrode per unit area around the output electrode
The area occupancy of the pole is the unit area of the image display unit.
Is also a display device substrate, wherein the relative area occupancy of the pixel electrode of the or is within 20% ±.

Further, the dummy electrode and the pixel electrode are
If the same material is used and there are multiple dummy electrodes,
Of dummy electrode per unit area around the output electrode
Area occupancy per unit area in the image display unit
And the area occupancy of the pixel electrode is
It is also a display device substrate.

Further, the dummy electrode and the pixel electrode are
Shape, size, distance between electrodes, positional relationship between adjacent electrodes
The same applies to a display device substrate.

For the display device according to any one of the above
A substrate and a counter electrode arranged to face the display device substrate.
A polar substrate, the active matrix substrate and the counter electrode.
And a liquid crystal sandwiched between polar substrates.
It is also an indicating device .

In addition, the fact that the above liquid crystal display device is used is
It is also a characteristic projection type liquid crystal display device .

The present invention also has a substantially flat surface.
And an image display unit having a plurality of pixel electrodes,
And an input / output electrode formed by polishing together with the pole
In the method of manufacturing a display device substrate, a pattern is formed on the surface of the substrate.
The formed insulating layer is selectively removed, and the pixel electrode, the
The input / output electrodes and the periphery of the input / output electrodes are the same as the image display unit.
Arranged around the input / output electrodes to achieve the same polishing rate.
Of each electrically floating dummy electrode
Forming an insulating layer region for separation;
After forming the layer region, the pixel electrode and the input layer are formed on the surface of the substrate.
Form the electrode material that will become the output electrode and the dummy electrode
And a step of polishing the electrode material on the insulating layer region.
The pixel electrode separated by removing the electrode material,
Forming an input / output electrode and the dummy electrode;
Having the pixel electrode, the input / output electrode, and the dummy
The electrodes and the periphery of the input / output electrodes are the same as the image display unit.
The electrode material is polished to obtain the same polishing rate.
A method of manufacturing a substrate for a display device, which is characterized in that
Is the law.

[0012]

[0013]

[0014]

[0015]

[0016]

[Operation] With the above configuration of the present invention, the area to be polished per unit area of the image display section and the area to be polished per unit area of the bonding pad section other than the image display section are equalized. By keeping the polishing rate in the chip substantially constant, the finished surface shape after CMP can be made uniform.

[0018]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

Although the embodiments of the present invention will be described with reference to a plurality of liquid crystal panels, the embodiments are not limited to the respective embodiments. It goes without saying that the effect is increased by combining the technologies of the mutual forms. Further, although the structure of the liquid crystal panel is described using the semiconductor substrate, the structure is not necessarily limited to the semiconductor substrate, and the structure described below may be formed on an ordinary transparent substrate. . The liquid crystal panels described below are all MOS
Although it is an FET or TFT type, it may be a two-terminal type such as a diode type. Furthermore, the liquid crystal panel described below is used as a display device for home televisions, projectors, head-mounted displays, 3D video game devices, laptop computers, electronic organizers, video conference systems, car navigation systems, airplane panels, etc. It is valid.

FIG. 7 shows a cross section of the liquid crystal panel portion of the present invention. In the figure, 301 is a semiconductor substrate, and 302 and 30.
2'denotes p-type and n-type wells, 303 and 30 respectively
3 ', 303 "is a source region of the transistor, 304 is a gate region, and 305, 305', 305" are drain regions.

As shown in FIG. 7, since a high breakdown voltage of 20 to 35 V is applied to the transistor in the display region, the source and drain layers are not formed in a self-aligned manner with respect to the gate 304 and have an offset. so, the source region 303 therebetween ', the drain region 305' as shown in a low concentration in the p-well n ^- layer of low concentration in the n-well p ^- layer is provided. By the way, the offset amount is 0.5-2.0μ
m is preferred. On the other hand, a part of the peripheral circuit is shown in FIG.
In some peripheral circuits, the source and drain layers are formed in self-alignment with the gate.

Here, the source and drain offsets have been described, but it is effective to change the offset amount according to each withstand voltage, and to optimize the gate length, in addition to the presence / absence thereof. This is because a part of the peripheral circuit is a logic circuit, and this part is generally 1.5 to 5V.
Since the system drive is sufficient, the self-alignment structure is provided in order to reduce the transistor size and improve the transistor driving force. The substrate 301 is made of a p-type semiconductor,
The substrate has the lowest potential (usually the ground potential), and the n-type well receives the voltage applied to the pixel, that is, 20 to 35 V in the case of the display region, while the logic part of the peripheral circuit has the logic drive voltage 1 0.5 to 5V is applied. With this structure, it is possible to configure an optimum device according to each voltage, and it is possible not only to reduce the chip size but also to realize high pixel display by improving the driving speed.

In FIG. 7, 306 is a field oxide film, 310 is a source electrode connected to the data wiring, and 3 is a source electrode.
Reference numeral 11 is a drain electrode connected to the pixel electrode, 312 is a pixel electrode which also serves as a reflecting mirror, 307 is a light-shielding layer covering the display region and the peripheral region, and Ti, TiN, W, Mo and the like are suitable.
As shown in FIG. 7, the light-shielding layer 307 is covered in the display region except for the connection portion between the pixel electrode 312 and the drain electrode 311, but in the peripheral pixel region, some video lines, clock lines, etc. The area where the wiring capacitance becomes heavy is excluding the light shielding layer 307, and the portion where the high speed signal is excluding the light shielding layer 307 is mixed with the illumination light to cause a malfunction of the circuit. The device is designed so that it can be transferred. 308 is a light shielding layer 30
In the insulating layer under 7, the P-SiO layer 318 was planarized by SOG, and the P-SiO layer 318 was further covered with the P-SiO layer 308 to ensure the stability of the insulating layer 308. . In addition to flattening by SOG, P-TE
OS (Phospho-Tetraetoxy-Sil
Needless to say, a method may be used in which the (ane) film is formed, the P-SiO layer 318 is further covered, and then the insulating layer 308 is subjected to CMP treatment to be planarized.

Reference numeral 309 denotes the reflective electrode 312 and the light shielding layer 3
07 is an insulating layer provided between the insulating layer 309 and
It serves as a charge holding capacity of the reflective electrode 312. Big
SiO for capacitance formation₂ Besides, high dielectric constant PS
iN, Ta₂ O_Five , Or SiO ₂ And laminated films are effective
It The light-shielding layer 307 has a flat surface made of Ti, TiN, Mo, W, or the like.
By installing on metal, 500 to 5000 angs
A film thickness of about Trohm is suitable.

Further, 314 is a liquid crystal material, 315 is a common transparent electrode, 316 is a counter substrate, 317 and 317 'are high-concentration impurity regions, 319 is a display region, and 320 is an antireflection film.

As shown in FIG. 7, high-concentration impurity layers 317 and 317 'having the same polarity as the wells 302 and 302' formed under the transistors are formed around the wells 302 and 302 '. Even when a high-amplitude signal is applied to the source, the well potential is fixed at a desired potential in the low resistance layer, and thus stable and high-quality image display can be realized. Further, the high-concentration impurity layers 317 and 317 'are provided between the n-type well 302' and the p-type well 302 via a field oxide film, which is directly under the field oxide film used in a normal MOS transistor. No channel stop layer is required.

These high-concentration impurity layers 317 and 317 '
Can be done simultaneously in the source and drain layer formation process, so the number of masks and man-hours in the manufacturing process can be reduced.
Cost reduction was achieved.

Next, reference numeral 313 denotes an antireflection film provided between the common transparent electrode 315 and the counter substrate 316, which is configured to reduce the interface reflectance in consideration of the refractive index of the liquid crystal at the interface. To be done. In that case, an insulating film having a smaller refractive index than the counter substrate 316 and the transmissive electrode 315 is preferable.

Next, a plan view of the present invention is shown in FIG. In the figure, 321 is a horizontal shift register, 322 is a vertical shift register, 323 is an n-channel MOSFET, 3
24 is a p-channel MOSFET, 325 is a storage capacitor,
326 is a liquid crystal layer, 327 is a signal transfer switch, 328 is a reset switch, 329 is a reset pulse input terminal,
Reference numeral 330 is a reset power supply terminal, and 331 is a video signal input terminal. Although the semiconductor substrate 301 is p-type in FIG. 7, it may be n-type.

The well region 302 'is formed on the semiconductor substrate 301.
To the opposite conductivity type. Therefore, in FIG. 7, the well region 302 is p-type. p-type well region 302
It is preferable that the n-type well region 302 ′ and the n-type well region 302 ′ be implanted with impurities at a higher concentration than the semiconductor substrate 301.
The impurity concentration of the semiconductor substrate 301 is 10 ¹⁴ to 10 ¹⁵ (cm
^-3 ), the impurity concentration of the well region 302 is 10 ¹⁵ to
10 ¹⁷ (cm ⁻³ ) is desirable.

The source electrode 310 is a data line to which a display signal is sent, and the drain electrode 311 is a pixel electrode 3.
Connect to 12. These electrodes 310 and 311 are usually formed of Al, AlSi, AlSiCu, AlGeCu, Al.
Cu wiring is used. When a via metal layer made of Ti and TiN is used for the contact surface between the lower part of these electrodes 310 and 311 and the semiconductor, stable contact can be realized. Further, contact resistance can be reduced. The pixel electrode 312 has a flat surface and is preferably made of a high-reflecting material, and is a normal wiring metal such as Al, AlSi, AlSiCu, AlGeCu, A.
Besides lCu, it is possible to use materials such as Cr, Au, and Ag. Further, in order to improve the flatness, the surfaces of the base insulating layer 309 and the pixel electrode 312 are processed by the chemical mechanical polishing (CMP) method.

The storage capacitor 325 is a capacitor for holding a signal between the pixel electrode 312 and the common transparent electrode 315. A substrate potential is applied to the well region 302. In this embodiment, the transmission gate configuration of each row is
In the first row from the top, the top is the n-channel MOSFET 323.
Then, the lower row is the p-channel MOSFET 324, the second row is the p-channel MOSFET 324, and the lower row is the n-channel MOSFET 323. As described above, not only is the striped well in contact with the power supply line around the display region, but a thin power supply line is also provided in the display region for contact.

At this time, stabilization of the well resistance is key. Therefore, in the case of a p-type substrate, a structure is adopted in which the contact area or the number of contacts inside the display region of the n-well is increased more than that of the p-well. Since the p-well has a constant potential on the p-type substrate, the substrate plays a role as a low resistance body. Therefore, the influence of the fluctuation of the signal input / output to / from the source and drain of the island-shaped n-well is likely to be large, but this can be prevented by increasing the contact from the upper wiring layer. As a result, stable and high-quality display was realized.

A video signal (video signal, pulse-modulated digital signal, etc.) is input from the video signal input terminal 331, the signal transfer switch 327 is opened / closed according to the pulse from the horizontal shift register 321, and each data wiring is connected. Output. From the vertical shift register 322, a high pulse is applied to the gate of the n-channel MOSFET 323 and a low pulse is applied to the gate of the p-channel MOSFET in the selected row.

As described above, the switch of the pixel portion is composed of a single-crystal CMOS transmission gate, and the signal to be written to the pixel electrode does not depend on the threshold value of the MOSFET and has the advantage that the signal of the source can be fully written. Have.

Further, since the switch is composed of a single crystal transistor, there is no unstable behavior at the crystal grain boundaries of the polysi-TFT, and highly reliable and high-speed driving without variation can be realized.

Next, the configuration of the panel peripheral circuit is shown in FIG.
Will be explained. In FIG. 9, 337 is a liquid crystal display area, 332 is a level shifter circuit, 333 is a video signal sampling switch, 334 is a horizontal shift register, 335 is a video signal input terminal, and 336 is a vertical shift register.

With the above-described structure, the logic circuit such as the shift register for both H and V has the video signal input terminal 3
Since the amplitude of about 25V, 30V is supplied from 35,
It can be driven at an extremely low value of about 1.5 to 5 V, and high speed and low power consumption can be achieved. Horizontal and vertical SR here is
The scanning direction is bidirectional with a selection switch, and it is possible to respond to changes in the layout of the optical system without changing the panel, and the same panel can be used for different product series, reducing cost. There is a merit that can be achieved. Further, in FIG. 9, the video signal sampling switch is described as a one-transistor one-transistor configuration, but the present invention is not limited to this, and a CMOS transmission gate configuration can be used to write all input video lines to signal lines. It goes without saying that you can do it.

In addition, when the CMOS transmission gate structure is adopted, there is a problem that the video signal is fluctuated due to the difference in the NMOS gate and PMOS gate area and the overlapping capacitance between the gate and the source / drain. To prevent this, by connecting the source and drain of the MOSFET having a gate amount of about ½ of that of the MOSFET of each polarity sampling switch to the signal line and applying a reverse-phase pulse, the swing can be prevented. , A very good video signal was written to the signal line. This has made it possible to display even higher quality.

Next, the direction in which the video signal and the sampling pulse are accurately synchronized will be described with reference to FIG. For this purpose, it is necessary to change the delay amount of the sampling pulse. 324 is a pulse delay inverter, 343 is a switch for deciding which delay inverter to select, 344 is an output whose delay amount is controlled, 345 is a capacitor (outB is a reverse phase output, o
ut is an in-phase output). Reference numeral 346 is a protection circuit.

From SEL1 (SEL1B) to SEL3 (S
Depending on the combination of EL3B), how many passes through the delay inverter 342 can be selected.

Since this synchronizing circuit is built in the panel, the delay amount of the pulse from the outside of the panel is
R. G. In the case of the B3 plate panel, even if the symmetry is broken due to the jig or the like, it can be adjusted with the above selection switch. G. B
A good display image was obtained with no displacement due to the high pulse phase region of. Further, it goes without saying that it is also effective to incorporate a temperature measuring diode inside the panel and refer to the delay amount from the table by the output thereof to correct the temperature.

Next, the relationship with the liquid crystal material will be described.
In FIG. 7, a flat counter substrate structure is shown, but the common electrode substrate 316 is formed with irregularities in order to prevent interface reflection of the common transparent electrode 315, and the common transparent electrode 315 is formed on the surface thereof.
Is provided. Further, an antireflection film 320 is provided on the opposite side of the common electrode substrate 316. In order to form these irregularities, a method of sand-polishing with fine abrasive grains is also effective for high contrast.

Polymer network liquid crystal PNLC was used as the liquid crystal material. However, PDLC or the like may be used as the polymer network liquid crystal. The polymer network liquid crystal PNLC is produced by a polymerization phase separation method. A liquid crystal and a polymerizable monomer or oligomer are used to form a solution, which is then injected into a cell by a usual method, and then the liquid crystal and the polymer are phase-separated by UV polymerization to form a polymer in the liquid crystal network. PNLC has many liquid crystals (70-9
0 wt%).

In PNLC, the anisotropy of refractive index (Δ
When a nematic liquid crystal having a high n) is used, light scattering is not strong, and when a nematic liquid crystal having a large dielectric anisotropy (Δε) is used, it can be driven at a low voltage. The size of the polymer network, that is, the distance between the centers of the meshes is 1 to 1.5.
At (μm), the light scattering is strong enough to obtain high contrast.

Next, the relationship between the seal structure and the panel structure will be described with reference to FIG. In FIG.
Reference numeral 351 is a seal portion, 352 is an electrode pad, and 353 is a clock buffer circuit. The amplifier section (not shown) is used as an output amplifier at the panel electrical inspection.
Further, there is an Ag paste portion (not shown) for taking the potential of the counter substrate, and 356 is a display portion made of a liquid crystal element, and 357 is a peripheral circuit portion such as a horizontal / vertical shift register (SR). A seal portion 351 indicates a contact area of a pressure-bonding material or an adhesive agent for bonding a pixel electrode 312 provided on the semiconductor substrate 301 on four sides of the display portion 356 and a glass substrate having a common electrode 315 to each other. After they are attached to each other at the portion 351, liquid crystal is sealed in the display portion 356 and the shift register portion 357.

As shown in FIG. 11, according to the present embodiment, the total amount of chips inside or outside the seal is determined.
The circuit is provided so that the size becomes small. In the present embodiment, the pad is pulled out to one side of the panel.
Although it is concentrated on one side, it is also possible to take out from both sides of the long side and also from multiple sides instead of one side, which is effective when handling a high-speed clock.

Further, since the panel of the present invention uses a semiconductor substrate such as a Si substrate, when the substrate is irradiated with intense light like a projector and the side wall of the substrate also receives light, the substrate potential fluctuates, It may cause malfunction of the panel. Therefore, the side wall of the panel and the peripheral circuit portion of the display area on the upper surface of the panel serve as a substrate holder that can shield light, and the back surface of the Si substrate has a high thermal conductivity via an adhesive having a high thermal conductivity. It has a holder structure in which a metal such as Cu is connected.

Next, an optical system incorporating the reflective liquid crystal panel of the present invention will be described with reference to FIG. 12
371, a light source such as a halogen lamp, 372, a condenser lens for narrowing down the light source image, 373, 375, a planar convex Fresnel lens, and 374, an R.I. G. It is a color separation optical element that decomposes into B, and a dichroic mirror, a diffraction grating, etc. are effective.

376 is the R. G. Each of the lights separated into the B light is converted into R. G. The respective mirrors 377 leading to the B3 panel are field lenses for illuminating the condensed beam to the reflection type liquid crystal panel by parallel light, and the reference numeral 378 is limited to the position of the reflection type liquid crystal element 379 described above. Further, reference numeral 380 denotes a projection lens which combines and enlarges a plurality of lenses, and 38
Reference numeral 1 denotes a screen, which is usually composed of two plates, a Fresnel lens for converting the projection light into parallel light and a lenticular lens for displaying a wide viewing angle vertically and horizontally, so that a clear and high-contrast bright image can be obtained. . In the configuration of FIG. 12, only one color panel is shown, but the space between the color separation optical element 374 and the narrowed portion 379 is divided into three colors, and three panel panels are arranged. Further, it is needless to say that by providing a microlens array on the surface of the reflective liquid crystal device panel and irradiating different pixel regions with different incident light, not only three plates but also a single plate structure can be used. A voltage is applied to the liquid crystal layer of the liquid crystal element, and the light specularly reflected by each pixel passes through the narrowed portion 379 and is projected on the screen.

On the other hand, when a voltage is not applied and the liquid crystal layer is a scatterer, the light incident on the reflection type liquid crystal element is isotropically scattered and the angle of viewing the aperture of the diaphragm portion 379. Other than the scattered light inside, there is no need for a projection lens. This displays black. As can be seen from the above optical system, since a polarizing plate is not necessary and the entire surface of the pixel electrode has a high reflectance of the signal light in the projection lens, a display that is 2-3 times brighter than the conventional one can be realized. As described in the above embodiments, anti-reflection measures are taken on the surface and the interface of the counter substrate, the noise light component is extremely small, and high contrast display can be realized. Further, since the panel size can be made small, all the optical elements (lenses, mirrors etc.) are made compact, and low cost and light weight are achieved.

The color unevenness, the brightness unevenness, and the fluctuation of the light source can be corrected by inserting an integrator (fly-eye lens type rod type) between the light source and the optical system. Was solved.

Peripheral electric circuits other than the liquid crystal panel will be described with reference to FIG. In the figure, reference numeral 385 denotes a power source, which is mainly separated into a lamp power source and a panel or signal processing circuit driving system power source. 386 is a plug, 387 is a lamp temperature detector, and if there is an abnormality in the lamp temperature, the control board 388 performs control such as stopping the lamp. This is controlled not only by the lamp but also by the 389 filter safety switch. For example, when a high temperature lamp house box is opened, safety measures are taken so that the box will not be damaged. 390 is a speaker, 391 is an audio board, and a processor for 3D sound, surround sound, or the like can be built in as required. An expansion board 392 is an external device 396 such as a video signal S terminal, a video signal composite image, and audio.
And an input terminal for selecting a signal to be selected and a tuner 394, and a signal is sent to the expansion board 2 via the decoder 393. On the other hand, the expansion board 2 mainly has a video from another system and a Dsub 5 pin terminal of a computer, and is connected to the A / D via the switch 450 for switching the video signal from the decoder 393.
It is converted into a digital signal by the converter 451.

Reference numeral 453 is a main board mainly composed of a memory such as a video RAM and a CPU. The NTSC signal A / D converted by the A / D converter 451 is once stored in the memory and is allocated to a high pixel number,
The signal processing is performed by interpolating a signal of lack of empty elements that does not match the number of liquid crystal elements, and performs signal processing such as γ conversion edge gradation and bright adjustment bias adjustment suitable for liquid crystal display elements. If not only the NTSC signal but also the computer signal, for example, the VGA signal, in the case of the high resolution XGA panel, the resolution conversion processing is also performed. The main board 453 performs not only one image data but also processing such as synthesizing a computer signal with NTSC signals of a plurality of image data. The output of the main board 453 is converted from serial to parallel, and is supplied to the head board 454 in a form that is less susceptible to noise. This headboard 454 again performs parallel / serial conversion, D / A conversion, and division according to the number of video lines on the panel, and via the drive amplifier,
B. G. A signal is written in the R color liquid crystal panels 455, 456, 457. Reference numeral 452 is a remote control operation panel, and the computer screen can be easily operated in the same manner as a TV. Further, each of the liquid crystal panels 455, 456, 457 has the same liquid crystal device configuration provided with a color filter of each color, and the above-mentioned horizontal / vertical scanning circuit is applied. As described above, each liquid crystal device can process images that do not necessarily have high resolution into high-quality images.
The display result of the present invention enables an extremely beautiful image display. The method of forming the bonding pad portion, which is a feature of this embodiment, will be described below.

FIG. 1 is a schematic sectional view showing a process of the first embodiment.

In FIG. 1A, 1 is a Si substrate, 2 is a Field oxide film, 3 is BPSG, 4 is an AL1 (input / output electrode) to which a power source, a video signal, a clock and the like are input, and 5 is P. -Interlayer insulating film such as SiO, 6 is P-SiN,
7 is P-SiO. The interlayer insulating film 5 is flattened by SOG or CMP.

In FIG. 1B, the groove 8 is formed by patterning P-SiO7. The etching process for forming the groove 8 is 1 to prevent the loading effect and to prevent the deposition of the polymer during etching.
Etching with CF ₄ alone is effective at a pressure of rr or less.

In FIG. 1 (c), a through hole 9 for establishing conduction with AL1 (4) is formed.

In FIG. 1D, AL2 (10) is deposited. Since the thickness of AL2 (10) is made larger than that of P-SiO7 and the through hole 9 is completely filled,
For example, it is effective to use an AL reflow technique in which pure AL is deposited and held in a high vacuum of 10 ⁻⁷ torr or less at a high temperature of 400 ° C. or more for a time of 5 minutes or more. Further, the same effect can be obtained even if the AL film is formed after the through hole 9 is filled by the tungsten CVD or the like.

The AL2 (10) is an image display section (not shown).
In this case, since a reflective electrode (pixel electrode) is formed, if a metal material having a high reflectance characteristic with respect to visible light such as Ag or Pt is used in addition to AL, high brightness and high contrast of a display image are obtained. Is effective in terms of.

In FIG. 2E, CMP (Chemi
cal mechanical polishing) is used to planarize the surface and at the same time AL2 on P-SiO7.
By removing (10), the bonding pad 11 and the dummy electrode 12 which is electrically floating are formed.

The CMP conditions were EPO-114 manufactured by EBARA CORPORATION, Supreme RN-H manufactured by Rodel manufactured by Rodel as a polishing cloth, and PLANERLITE-5102 manufactured by Fujimi Incorporated as a slurry, and a wafer pressing load of 300 gf / cm. ² , wafer rotation speed 31 rpm, turntable rotation speed 30 rp
m, the flow rate of the slurry is 75 ml / min. The dressing of the polishing cloth is an in-sifu dressing in which a nylon brush having a diameter of 0.13 mm is used and dressing is performed simultaneously with polishing at a load of 98 gf / cm ² and a rotation speed of 32 rpm. The polishing conditions are not limited to the above conditions, and devices and consumable members sold by each manufacturer can be used as appropriate.

As the CMP apparatus, one capable of quickly cleaning and drying the wafer after polishing is desired, and a dry-in / dry-out apparatus having a cleaning unit or an apparatus inline with the cleaning apparatus is effective. This is to prevent minute corrosion that occurs when a metal material such as AL is immersed in pure water for several tens of minutes or more.

As the polishing slurry, a large selection ratio of the polishing rates of AL2 (10) and P-SiO7 can be obtained.
A slurry containing an oxidizing agent, which is capable of suppressing the generation of minute scratches and is composed of abrasive grains having a particle size of 100 nm or less, is effective. The polishing cloth is a suede type polishing cloth that has a small hardness to suppress scratches and a small bore diameter, and a polishing cloth with a small polishing coefficient is effective in improving the uniformity of the polishing rate on the wafer surface. Is.

The polishing parameters also differ depending on the structure of the device, the polishing apparatus, and the consumable member, and are appropriately optimized.

FIG. 2 (f) shows a perspective view of FIG. 2 (e). The feature of this embodiment is that the dummy electrodes 12 that are electrically floating are arranged all around the bonding pad 11, and the shape and size of the dummy electrodes, the distance between the dummy electrodes, and the distance between the adjacent dummy electrodes. The positional relationship is the same as that of the pixel electrode of the image display section (not shown). As a result, the polishing rate around the bonding pad 12 and the polishing rate of the image display section can be made equal, and when the polishing amount is adjusted to the image display section, the polishing residue around the bonding pad section can be prevented, and the bonding It is possible to prevent a short circuit between the pad parts.

Further, even if the wire bonding is misaligned and the bonding portion protrudes from the bonding pad, an electrical path to the adjacent bonding pad is not formed, so that a short circuit between the pads can be prevented.

Although the periphery of the bonding pad 12 is described here, it is needless to say that the periphery of the bonding pad 12 can be formed around the exposed electrode exposed on the device surface.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention. The feature of this embodiment is that the bonding pad 1 is used.
1. The electrically floating dummy electrode 12 arranged around 1 has an arbitrary shape and arbitrary size, and the area occupancy rate of the dummy electrode 12 per unit area, for example, per 1 mm ² is the pixel of the image display unit. This is a point within ± 20% of the area occupancy of the electrode (not shown).

The effect of this embodiment will be described with reference to FIGS. 3B and 4. In FIG. 3B, 1 is a Si substrate, 5 is an interlayer insulating film, 6 is P-SiN, 7 is P-SiO, 8 is a groove in which an electrode is formed, and 10 is AL2.

The AL2 (10) side of this structure was CMP-polished to obtain the polishing rate of AL2 20 on P-SiO7,
FIG. 4 shows the correlation of the area ratio occupied by 1 mm ^{2 of the} groove 8 in which the electrode is formed, that is, the electrode area occupation ratio.
Is. Here, the CMP condition is the condition described in the first embodiment.

As shown in FIG. 4, the convex portion AL2 (2
The polishing rate of 0) depends on the area occupancy of the electrode.

Here, for example, when the area occupation ratio of the pixel electrode of the image display portion is 70%, the polishing Al polishing rate of the convex portion of the image display portion is about 3500Å / min. 70% of the electrode area occupation rate of the dummy electrode around the bonding pad
When it is set to ± 20%, the convex Al polishing rate at the electrode area occupancy rate of 50% is about 3200Å /
min, electrode area occupancy 90%, approximately 3800Å
/ Min, and the polishing rate for the convex Al on the image display is about 3
It is understood that it is possible to suppress the range to ± 10% of 500Å / min.

Under the current CMP conditions, the in-plane uniformity of the AL polishing rate is (MAX-MIN) / AV.
ERAGE is 20-30%, so 10 of the above 2
It can be seen that the difference in polishing rate of not more than% is sufficiently smaller than the in-plane distribution of the polishing rate and is not a dominant factor that influences the finish of the device surface after CMP.

Therefore, the pattern of the dummy electrode 12 can be formed with a high degree of freedom under the condition that the difference in area occupation ratio between the dummy electrode 12 and the pixel electrode is 20% or less.

(Third Embodiment) A third embodiment of the present invention is shown in FIG. In the figure, 30 is a quartz substrate and 31 is a single crystal Si layer. In the figure, the same parts as those in the above-mentioned embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The feature of this embodiment is that SOI (Silico)
n On Insulator) substrate is used. As a result, the peripheral circuits and the switching elements of the pixel portion can be driven at high speed, and the display device can have high definition.

(Fourth Embodiment) FIG. 14 is a block diagram showing the optical system of front and rear projection type liquid crystal display devices using the liquid crystal display device of the present invention. This figure is a top view of FIG.
(A), FIG. 14 (b) showing a front view, FIG. 1 showing a side view
It consists of 4 (c). In the figure, 1301 is a projection lens for projecting on a screen, 1302 is a liquid crystal panel with microlenses, 1303 is a polarization beam splitter (PBS), 1340 is an R (red light) reflection dichroic mirror, and 1341 is B / G (blue & green). Light) reflection dichroic mirror, 1342 B (blue light) reflection dichroic mirror, 1343 high-reflection mirror that reflects all color light, 1350 Fresnel lens, 1351 convex lens, 1306 rod-type integrator, 1307 elliptic reflector, 1308 Metal Halide, UHP
Etc. is an arc lamp. Here, R (red light) reflection dichroic mirror 1340, B / G (blue & green light)
The reflection dichroic mirror 1341 and the B (blue light) reflection dichroic mirror 1342 each have a spectral reflection characteristic as shown in FIG. And these dichroic mirrors together with the high reflection mirror 1343,
As shown in the perspective view of FIG. 16, they are arranged three-dimensionally, and as described later, white illumination light is color-separated into RGB and each primary color light is three-dimensionally different with respect to the liquid crystal panel 1302. The liquid crystal panel 1302 is illuminated from the direction.

Here, the description will be given according to the traveling process of the luminous flux. First, the luminous flux emitted from the lamp 1308 of the light source is white light, which is condensed by the elliptical reflector 1307 at the entrance of the integrator 1306 in front of it, and the inside of the integrator 1306 is controlled. The spatial intensity distribution of the light flux becomes uniform as the light travels while repeating the reflection. Then, the light flux emitted from the integrator 1306 is the convex lens 1
351 and the Fresnel lens 1350 form a parallel light beam in the x-axis-direction (reference to the front view of FIG. 14B), and first reach the B reflection dichroic 19-ic mirror 1342. Only the B light (blue light) is reflected by the B reflection dichroic mirror 1342, and the z-axis-direction, that is, the lower side (see FIG. 14).
Heading toward the R reflection dichroic mirror 1340 at a predetermined angle with respect to the z-axis (based on the front view of (b)). On the other hand, the color light (R / G light) other than the B light passes through the B reflection dichroic mirror 1342, is reflected at a right angle by the high reflection mirror 1343 in the z-axis (downward) direction, and is also directed to the R reflection dichroic mirror 1340. . Here, the B-reflection dichroic mirror 1342 and the high-reflection mirror 1343 are, based on the front view of FIG. 14A, the light flux (x-axis direction) from the integrator 1306, the z-axis-direction (lower side). The high-reflecting mirror 1343 has an inclination of 45 ° with respect to the xy plane with the y-axis direction as the rotation axis. On the other hand, the B-reflecting dichroic mirror 1342 still has the x-axis as the rotation axis in the y-axis direction.
The angle is set to be shallower than 45 ° with respect to the -y plane. Therefore, while the R / G light reflected by the high-reflection mirror 1343 is reflected at a right angle to the z-axis − direction,
The B light reflected by the B reflection dichroic mirror 1342 heads downward at a predetermined angle (x-z in-plane tilt) with respect to the z axis. Here, the B light and R / G light liquid crystal panel 13
02, the shift amounts and tilt amounts of the high-reflecting mirror 1343 and the B-reflecting dichroic mirror 1342 are selected so that the chief rays of the respective colored lights intersect on the liquid crystal panel 1302.

Next, as described above, the downward direction (z-axis direction)
The R / G / B light directed to the R head goes to the R reflection dichroic mirror 1340 and the B / G reflection dichroic mirror 1341.
2 and the lower side of the high reflection mirror 1343. First, B /
The G reflection dichroic mirror 1341 is arranged at an angle of 45 ° with respect to the xz plane with the x axis as the rotation axis, and the R reflection dichroic mirror 1340 is also arranged with respect to the xz plane with the x axis direction as the rotation axis. The angle is set to be shallower than 45 °. Therefore, of the R / G / B light incident on these, first the B / G light is the R reflection dichroic mirror 13.
After passing 40, the B / G reflection dichroic mirror 13
PBS 130 is reflected at a right angle to the y-axis + direction,
After being polarized through 3, the liquid crystal panel 1302 arranged horizontally in the xz plane is illuminated.

Of these, the B light is as described above (see FIG. 14).
(A) and FIG. 14 (b)), since the light beam travels at a predetermined angle (xz in-plane tilt) with respect to the x-axis, after reflection by the B / G reflection dichroic mirror 1341, the y-axis is displayed. On the other hand, a predetermined angle (tilt in the xy plane) is maintained, and the angle is defined as the incident angle (direction of the xy plane).
Illuminate 02.

The G light is reflected at a right angle by the B / G reflection dichroic mirror 1341, travels in the y-axis + direction, is polarized by the PBS 1303, and then has an incident angle of 0.
° That is, the liquid crystal panel 1302 is illuminated vertically. The R light is reflected in the y-axis + direction by the R reflection dichroic mirror 1340 by the R reflection dichroic mirror 1340 arranged in front of the B / G reflection dichroic mirror 1341 as described above. )
As shown in (side view), a predetermined angle (y
-Z in-plane tilt) to advance in the y-axis + direction, and PBS1303
After being polarized through, the liquid crystal panel 1302 is illuminated with the angle with respect to the y-axis as the incident angle (y-z plane direction). Further, similar to the above, the liquid crystal panel 1 for each color of RGB light
In order to match the illumination range on 302, the shift amount and tilt amount of the B / G reflection dichroic mirror 1341 and the R reflection dichroic mirror 1340 are selected so that the chief rays of each color light intersect on the liquid crystal panel 1302. . Further, as shown in FIG. 15A, the cut wavelength of the B reflection dichroic mirror 1341 is 480 nm,
As shown in FIG. 15B, the cut wavelength of the B / G reflection dichroic mirror 1341 is 570 nm.
As shown in (c), the R reflection dichroic mirror 13
Since the cut wavelength of 40 is 600 nm, unnecessary orange light is transmitted through the B / G reflection dichroic mirror 1341 and is discarded. This makes it possible to obtain the optimum color balance.

A liquid crystal panel 1302 will be described later.
Each RGB light is reflected and polarization modulated by PBS1303
Then, the light flux reflected in the x-axis + direction on the PBS surface 1303a of the PBS 1303 becomes image light, and the projection lens 13
Through 01, enlarged projection is performed on a screen (not shown). By the way, each RG that illuminates the liquid crystal panel 1302
Since the B light has a different incident angle, the RGB light reflected from the B light also has a different outgoing angle.
As 301, a lens having a lens diameter and an aperture large enough to take in all of them is used. However, the inclination of the light beam incident on the projection lens 1301 is made parallel by each color light passing twice through the microlens, and the inclination of the incident light on the liquid crystal panel 1302 is maintained. However, as shown in FIG. 26, in the transmissive type of the conventional example, the luminous flux emitted from the liquid crystal panel spreads further due to the condensing effect of the microlens, so that the projection lens for taking in this luminous flux is larger. The numerical aperture is calculated,
It was an expensive lens. However, in this example, since the spread of the light flux from the liquid crystal panel 2 is relatively small in this way, a sufficiently bright projection image can be obtained on the screen even with a projection lens having a smaller numerical aperture, and the projection lens is less expensive. Can be used. Although an example of a stripe type display method in which the same colors are arranged in the vertical direction shown in FIG. 27 can be used in this embodiment, it is not preferable in the case of a liquid crystal panel using microlenses, as described later. .

Next, the liquid crystal panel 13 of the present invention used here
02 will be described. FIG. 17 shows the liquid crystal panel 1302.
16 is an enlarged cross-sectional schematic diagram (corresponding to the yz plane of FIG. 16).
In the figure, 1321 is a microlens substrate, 1322
Is a micro lens, 1323 is a sheet glass, 1324
Is a transparent counter electrode, 1325 is a liquid crystal layer, 1326 is a pixel electrode, 1327 is an active matrix drive circuit portion, 1
328 is a silicon semiconductor substrate. Further, 1252 is a peripheral seal portion. Here, in the present embodiment, R,
G and B pixels are integrated into one panel, and the size of one pixel is reduced. Therefore, it is very important to increase the aperture ratio, and the reflective electrode must exist in the range of the condensed light. The micro lens 1322 is
The pixel electrode 1 is formed on the surface of a glass substrate (alkali glass) 1321 by a so-called ion exchange method.
A two-dimensional array structure is formed with a pitch twice the pitch of 326.

The liquid crystal layer 1325 employs a so-called DAP, HAN or other ECB mode nematic liquid crystal adapted to the reflection type, and a predetermined alignment is maintained by an alignment layer (not shown). Since the voltage value is lower than that of the other embodiments and the accuracy of the potential of the pixel electrode 1326 becomes more important, the circuit and configuration of the present invention are effective, and the number of pixels is large on a single plate, and therefore the video line is large. Since the number of the above is large, it is very effective to reduce the coupling capacity in the other embodiments. The pixel electrode 1326 is made of Al and also serves as a reflecting mirror. In order to improve the surface property and improve the reflectance, so-called CMP treatment is performed in the final step after patterning (details will be described later).

Active matrix drive circuit section 132
Reference numeral 7 denotes a semiconductor circuit provided on a so-called silicon semiconductor substrate 1328, which drives the pixel electrodes 1326 in an active matrix, and a gate line driver (vertical register or the like) not shown is provided around the circuit matrix. And signal line driver (horizontal register, etc.)
Is provided (details will be described later). These peripheral drivers and active matrix drive circuits are
Each of the primary color image signals of GB is configured to be written in a predetermined RGB pixel, and each pixel electrode 1326 does not have a color filter, but each R of the primary color image signals written by the active matrix drive circuit is used.
They are distinguished as GB pixels and form a predetermined RGB pixel array described later.

Here, looking at the G light that illuminates the liquid crystal panel 1302, the G light is P light as described above.
The liquid crystal panel 13 after being polarized by BS1303
It is incident perpendicularly to 02. An example of a light beam that enters one microlens 1322a among these light beams is shown by an arrow G (in / out) in the figure. As shown here, the G ray is condensed by the microlens 1322 and illuminates the G pixel electrode 1326g. Then, the light is reflected by the pixel electrode 1326g made of Al and again emitted to the outside of the panel through the same microlens 1322a. In this way, when passing back and forth through the liquid crystal layer 1325, the G ray (polarized light) is modulated by the operation of the liquid crystal by the electric field formed between the counter electrode 1324 and the signal voltage applied to the pixel electrode 1326g, Exiting the liquid crystal panel,
Return to PBS 1303.

Here, depending on the degree of modulation, the PBS surface 1
The amount of light reflected by 303a and directed to the projection lens 1301 changes, and so-called gray scale display of each pixel is performed. On the other hand, as described above, the cross section (y-
For the R light incident from the diagonal direction in the (z plane),
Focusing on the R ray that is polarized by the PBS 1303 and then enters the microlens 1322b, for example, as shown by an arrow R (in) in the figure, the R ray is condensed by the microlens 1322b and is located on the left side of the point just below. The R pixel electrode 1326r at the shifted position is illuminated. Then, it is reflected by the pixel electrode 1326r, and as shown in the drawing, the adjacent microlens 1 (-z direction) is moved this time.
Light is emitted to the outside of the panel through 322a (R (ou
t)).

At this time, the R ray (polarized light) is also applied to the counter electrode 13 by the signal voltage applied to the pixel electrode 1326r.
The liquid crystal panel is modulated by the operation of the liquid crystal by the electric field according to the image signal formed between 24 and 24, and is emitted from the liquid crystal panel.
Return to PBS 1303. Then, in the subsequent process, the image light is projected from the projection lens 1301 in exactly the same manner as the case of the G light described above. By the way, in the drawing of FIG. 17, the G light and R light on the pixel electrode 1326g and the pixel electrode 1326r overlap so that they partially overlap with each other, but this is typically the thickness of the liquid crystal layer. This is because the drawing is enlarged and exaggerated. Actually, the thickness of the liquid crystal layer is 1 to 5 μm.
The sheet glass 1323 is much thinner than 50-100 μm, and such interference does not occur regardless of the pixel size.

Next, FIG. 18 shows an explanatory view of the principle of color separation / color combination in this example. Here, FIG. 18A is a schematic top view of the liquid crystal panel 1302, and FIGS. 18B and 18C are AA ′ (x) with respect to the schematic top view of the liquid crystal panel, respectively.
(Direction) cross-sectional schematic diagram, BB '(z direction) cross-sectional schematic diagram. Here, the microlens 1322 is shown in FIG.
As indicated by the alternate long and short dash line, one corresponds to each half of the two color pixels adjacent to each other with the G light as the center. Of these, FIG. 18C corresponds to FIG. 17 showing the yz cross section, and shows how the G light and the R light entering and exiting each microlens 1322 are input and output. As can be seen, each G pixel electrode is arranged directly below the center of each microlens, and each R pixel electrode is arranged directly below the boundary between each microlens. Therefore, the incident angle of R light is tan
It is preferable to set θ to be equal to the ratio of the pixel pitch (B & R pixel) and the distance between the microlens and the pixel electrode. On the other hand, FIG. 18B shows x- of the liquid crystal panel 1302.
This corresponds to the y section. In this xy cross section, B pixel electrodes and G pixel electrodes are alternately arranged as in FIG. 18C, and each G pixel electrode is also arranged directly below the center of each microlens and each B pixel electrode is arranged. The pixel electrode is arranged directly below the boundary between the microlenses.

By the way, the B light illuminating the liquid crystal panel is polarized by the PBS 1303 as described above, and then enters from the oblique direction of the cross section (xy plane) in FIG. In exactly the same manner, the B ray incident from each microlens 1322 is reflected by the B pixel electrode 1326b as illustrated, and is emitted from the microlens 1322 adjacent to the incident microlens 1322 in the x direction. The modulation by the liquid crystal on the B pixel electrode 1326b and the projection of the B emitted light from the liquid crystal panel are the same as those of the G light and the R light described above.

Further, each B pixel electrode 1326b is arranged directly below the boundary between the microlenses, and the incident angle of B light with respect to the liquid crystal panel is the same as ta of the R light.
It is preferable to set nθ to be equal to the ratio of the pixel pitch (G & B pixel) and the distance between the microlens and the pixel electrode. By the way, in the liquid crystal panel of this example, as described above, the arrangement of the RGB pixels is RGRRGRG ...
In addition, the arrangement of BGBGBG ... Is arranged in the x direction, and FIG. 18A shows the arrangement in plan view. In this way, each pixel size is approximately half the size of the microlens both vertically and horizontally, and the pixel pitch is half that of the microlens in both xz directions. Also,
The G pixel is also located directly below the center of the microlens in plan view, the R pixel is located between the G pixels in the z direction and at the microlens boundary, and the B pixel is located between the G pixels in the x direction and at the microlens boundary. There is. The shape of one microlens unit is rectangular (double the size of a pixel).

FIG. 19 shows a partially enlarged top view of the present liquid crystal panel. Here, a broken-line lattice 1329 in the drawing indicates a group of RGB pixels which form one picture element. That is, when each RGB pixel is driven by the active matrix drive circuit unit 1327 of FIG. 17, the RGB pixel unit indicated by the broken line grid 1329 corresponds to the R corresponding to the same pixel position.
It is driven by a GB video signal. Here, the R pixel electrode 132
6r, a G pixel electrode 1326g, and a B pixel electrode 1326b.
326r is a microlens 1 as indicated by an arrow r1.
It is illuminated by the R light obliquely incident from 322b as described above, and the R reflected light is emitted through the microlens 1322a as indicated by an arrow r-2. B pixel electrode 132
6b is a microlens 132 as indicated by an arrow b1.
As described above, the B light is obliquely incident from 2c, and the B reflected light is also emitted through the microlens 1322a as shown by an arrow b2. Further, the G pixel electrode 1326g is illuminated by the G light vertically (inwardly toward the paper surface) incident from the microlens 1322a, as indicated by the front rear surface arrow g12, and the G reflected light is the same microlens 1322a. The light is emitted vertically through (through the direction toward the front of the paper).

Thus, in the present liquid crystal panel, 1
Although the incident illumination positions of the respective primary color illumination lights are different for the RGB pixel units forming one picture element, they are the same microlens (in this case, 1322) for their emission.
from a). This also holds for all other picture elements (RGB pixel units).

Therefore, as shown in FIG. 20, all the light emitted from the liquid crystal panel is reflected by the PBS 1303 and the projection lens 13.
When the image is projected on the screen 1309 through 01, the position of the microlens 1322 in the liquid crystal panel 1302 is optically adjusted so as to be image-projected on the screen 1309, and the projected image is a grid of microlenses as shown in FIG. The constituent elements are picture elements in a state in which light emitted from the RGB pixel units constituting each picture element is mixed, that is, in the state where the same pixels are mixed. Then, it is possible to display a good color image with high texture without the so-called RGB mosaic as in the past.

Next, as shown in FIG. 17, the active matrix drive circuit portion 1327 is arranged in each pixel electrode 1326.
The RGB pixels forming the picture elements are simply drawn side by side in the circuit cross-sectional view of FIG. 17 because they exist below the pixel. However, the drain of each pixel FET has a two-dimensional structure as shown in FIG. To each RGB pixel electrode 1326 in a physical arrangement.

By the way, FIG. 21 shows an overall block diagram of a drive circuit system of the present projection type liquid crystal display device. Here, 1310 is a panel driver, which inverts the polarities of the RGB video signals and forms a liquid crystal drive signal which is amplified by a predetermined voltage, and drives the counter electrode 1324.
It forms various timing signals. An interface 1312 decodes various video and control transmission signals into standard video signals and the like. Reference numeral 1311 denotes a decoder which decodes and converts the standard video signal from the interface 1312 into RGB primary color video signals and synchronization signals, that is, image signals corresponding to the liquid crystal panel 1302. 1314 is a ballast, which drives and lights the arc lamp 1308 in the elliptical reflector 1307. 1
A power supply circuit 315 supplies power to each circuit block. Reference numeral 1313 denotes a controller having an operation unit (not shown) therein, which comprehensively controls the above circuit blocks. As described above, the drive circuit system of the present projection type liquid crystal display device is very common as a single-plate type projector, and particularly, the drive circuit system is not burdened and the above-described RGB mosaic is not required. It is possible to display a color image with various textures.

By the way, FIG. 23 shows a partially enlarged top view of another embodiment of the liquid crystal panel in the present embodiment. Here, the B pixel electrode 132 is located directly below the center of the microlens 1322.
6b are arranged, and G pixels 1326g are arranged in the left-right direction.
The R pixels 1326r are arranged so as to be alternately arranged in the vertical direction so that the pixels are alternately arranged. Even if it arranges like this,
By setting the B light to be vertically incident and the R / G light to be obliquely incident (at the same angle in different directions) so that the reflected light from the RGB pixel units forming the picture element is emitted from one common microlens, It is possible to obtain exactly the same effect. In addition, the R is placed directly below the center of the microlens 1322.
Pixels are arrayed and other color pixels are placed in the left or right or up and down directions.
G and B pixels may be arranged alternately with respect to the pixels.

(Fifth Embodiment) FIG. 24 shows another embodiment of the liquid crystal panel according to the present invention. The figure is a partially enlarged sectional view of the present liquid crystal panel 1320. To describe the difference from the other embodiments, first, the sheet glass 1323 is used as the counter glass substrate, and the microlens 1220 is used.
Is formed on the sheet glass 1323 by a so-called reflow method using a thermoplastic resin. Further, a spacer column 1251 is formed in the non-pixel portion by photolithography using a photosensitive resin. The liquid crystal panel 1
A partial top view of 320 is shown in FIG. As can be seen from this figure, the spacer columns 1251 are formed in the non-pixel regions at the corners of the microlenses 1220 at a predetermined pixel pitch. AA ′ passing through this spacer column 1251
A sectional view is shown in FIG. This spacer pillar 125
Regarding the formation density of No. 1, it is preferable to provide them in a matrix form with a pitch of 10 to 100 pixels.
It is necessary to set both the planarity of 3 and the liquid crystal injecting property that are contradictory to the number of spacer columns. Further, in the present embodiment, the light shielding layer 1221 having a metal film pattern is provided to prevent leakage of light from the boundary of each microlens. As a result, it is possible to prevent the saturation of the projected image from being reduced (due to the color mixture of the primary color image light) and the contrast from being reduced due to the leaked light. Therefore, by using the present liquid crystal panel 1320 to configure a projection display device including the liquid crystal panel according to the present embodiment, it is possible to obtain more distinct and favorable image quality.

[0100]

As described above, the polishing rate per unit area of the image display section and the polishing rate per unit area of the bonding pad section other than the image display section are set equal to each other. It is possible to make the finished surface shape after CMP uniform by keeping the value substantially constant.

Therefore, according to the present invention, since the polishing rate in the chip can be made equal, a short circuit of the bonding pad exposed on the chip surface can be prevented and the yield can be improved. In addition, the margin of the CMP process can be increased.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a bonding pad portion according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a bonding pad portion according to the first embodiment of the present invention.

FIG. 3 is a perspective view (a) of a bonding pad portion and a sectional view of a dummy electrode portion according to a second embodiment of the present invention.

FIG. 4 is a correlation diagram of a convex portion polishing rate and a dummy electrode area occupation rate.

FIG. 5 is a manufacturing process diagram of a bonding pad portion according to a third embodiment of the present invention.

FIG. 6 is a plan view of an image display unit of a conventional example.

FIG. 7 is a cross-sectional view of a liquid crystal device manufactured by CMP according to the present invention.

FIG. 8 is a schematic circuit diagram of a liquid crystal device according to the present invention.

FIG. 9 is a block diagram of a liquid crystal device according to the present invention.

FIG. 10 is a circuit diagram including a delay circuit of an input unit of the liquid crystal device according to the present invention.

FIG. 11 is a conceptual diagram of a liquid crystal panel of a liquid crystal device according to the present invention.

FIG. 12 is a conceptual diagram of a liquid crystal projector using a liquid crystal device according to the present invention.

FIG. 13 is a circuit block diagram showing the inside of a liquid crystal projector according to the present invention.

FIG. 14 is an overall configuration diagram showing an embodiment of an optical system of a projection type liquid crystal display device according to the present invention.

FIG. 15 is a spectral reflection characteristic diagram of a dichroic mirror used in the optical system of the projection type liquid crystal display device according to the present invention.

FIG. 16 is a perspective view of a color separation illumination unit of the optical system of the projection type liquid crystal display device according to the present invention.

FIG. 17 is a sectional view of an embodiment of a liquid crystal panel according to the present invention.

FIG. 18 is a diagram illustrating the principle of color separation / color combination of the liquid crystal panel according to the present invention.

FIG. 19 is a partially enlarged top view of the liquid crystal panel according to the embodiment of the present invention.

FIG. 20 is a partial configuration diagram showing a projection optical system of a projection type liquid crystal display device according to the present invention.

FIG. 21 is a block diagram showing a drive circuit system of a projection type liquid crystal display device according to the present invention.

FIG. 22 is a partially enlarged view of a projected image on a screen of the projection type liquid crystal display device according to the present invention.

FIG. 23 is a partial cross-sectional view of a liquid crystal panel according to an embodiment of the present invention.

FIG. 24 is a partially enlarged cross-sectional view of a liquid crystal panel according to an embodiment of the present invention.

FIG. 25 is a partially enlarged top view and a cross-sectional view of a liquid crystal panel according to an embodiment of the present invention.

FIG. 26 is a conceptual diagram showing a luminous flux traveling direction of a liquid crystal panel of a liquid crystal device.

FIG. 27 is a color pixel configuration diagram of a liquid crystal panel of a liquid crystal device.

[Explanation of symbols]

1 Si substrate 2 Field oxide film 3 BPSG 4 AL1 5 Interlayer insulation film 6 P-SiN 7 P-SiO 8 grooves 9 through holes 10 AL2 11 Bonding pad 12 dummy electrode 20 Convex part AL2 30 quartz substrate 31 Single crystal Si layer 51 display pixel area 52 signal, scan drive circuit 53 dummy pixels 301 Semiconductor substrate 302,302 'p-type and n-type wells 303, 303 ', 303 "Source area 304 gate area 305, 305 ', 305 "drain region 306 LOCOS insulation layer 307 Light-shielding layer 308 PSG 309 Plasma SiN 310 Source electrode 311 Connection electrode 312 Reflective electrode & pixel electrode 314 Liquid crystal layer 315 Common transparent electrode 316 Counter electrode 317, 317 'High concentration impurity region 319 display area 320 Antireflection film 321 and 322 shift registers 332 Boost level shifter 342 inverter 351 seal 378 liquid crystal device 455, 456, 457 liquid crystal device 201,501 Semiconductor substrate 202,502 scribe area 203,503 Selective oxide film 504 well 205, 505, 705, 805 First insulating film 207, 507, 707, 808 contacts 209, 509, 709, 809 Metal layer 602,603 Metal layer 601 effective area 511 through hole 701, 802 insulating substrate 810 Transparent insulating film 301 Semiconductor substrate 302,302 'p-type and n-type wells 303,303 'Source area 304 gate area 305, 305 'drain region 306 LOCOS insulation layer 307 Light-shielding layer 308 PSG 309 Plasma SiN 310 Source electrode 311 Connection electrode 312 Reflective electrode & pixel electrode 313 Antireflection film 314 Liquid crystal layer 315 Common transparent electrode 316 Counter electrode 317, 317 'high-concentration impurity region 319 display area 320 Antireflection film 321 and 322 shift registers 323 nMOS 324 pMOS 325 holding capacity 327 Signal transfer switch 328 reset switch 329 Reset pulse input terminal 330 Reset power supply terminal 331 Video signal input terminal 332 Boost level shifter 342 Inverter for pulse delay 343 switch 344 output 345 capacity 346 protection circuit 351 Seal part 352 electrode pad 353 clock buffer 371 light source 372 condenser lens 373,375 Fresnel lens 374 Color Separation Optical Element 376 mirror 377 field lens 378 liquid crystal device 379 aperture 380 projection lens 381 screen 385 power supply 386 plug 387 Lamp temperature detection 388 control board 389 Filter Safety Switch 453 Main board 454 LCD panel drive head board 455, 456, 457 liquid crystal device 1220 micro lens (reflow heat sagging type) 1251 spacer pillar 1252 peripheral seal part 1301 Projection lens 1302 LCD panel with micro lens 1303 Polarizing beam splitter (PBS) 1306 Rod type integrator 1307 Elliptical reflector 1308 arc lamp 1309 screen 1310 panel driver 1311 Decoder 1312 Interface circuit 1314 Ballast (arc lamp lighting circuit) 1320 LCD panel with micro lens 1321 microlens glass substrate 1322 micro lens (index distribution type) 1323 sheet glass 1324 Opposite transparent electrode 1325 liquid crystal 1326 Pixel electrode 1327 Active matrix drive circuit unit 1328 Silicon semiconductor substrate 1329 Basic pixel unit 1340 R reflective dichroic mirror 1341 B / G reflective dichroic mirror 1342 B reflective dichroic mirror 1343 High reflection mirror 1350 Fresnel lens (second condenser lens) 1351 first condenser lens

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-9-148329 (JP, A) JP-A-7-74175 (JP, A) JP-A-6-196570 (JP, A) JP-A-11- 72804 (JP, A) JP 9-15649 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1343 G02F 1/1368

Claims (7)

(57) [Claims] 1. A display device substrate comprising: an image display unit having a plurality of pixel electrodes having a substantially flat surface; and an input / output electrode formed by polishing together with the pixel electrodes. a substrate for a display device characterized by having the surroundings are positioned to the same polishing rate as the image display unit, an electrically floating dummy electrode around the input and output electrodes of the electrode. 2. The input / output in which the dummy electrode is made of the same material as the pixel electrode and has a plurality of dummy electrodes.
Of the dummy electrode per unit area around the electrode
Area occupancy per unit area in the image display unit
Display device substrate according to claim 1, characterized in that within 20% ± relative area occupancy of the pixel electrodes. 3. The dummy electrode is the same as the pixel electrode.
The input / output made of a material and having a plurality of the dummy electrodes
Area of dummy electrode per unit area around the electrode
The occupancy ratio is in front of the unit area in the image display unit.
Display device substrate according to <br/> claim 1, characterized in that the same as the area proportion of the serial pixel electrode. 4. The dummy electrode is formed with the pixel electrode.
Shape, size, distance between electrodes, positional relationship between adjacent electrodes
The display device substrate according to claim 1, wherein the substrates are the same. 5. A display device according to claim 1.
A mounting substrate and a pair arranged to face the display device substrate.
Counter electrode substrate, the active matrix substrate and the pair.
A liquid crystal display device comprising: a liquid crystal sandwiched between counter electrode substrates . 6. A projection type liquid crystal display device using the liquid crystal display device according to claim 5 . 7. A plurality of pixels having a substantially flat surface.
Image display unit with electrodes and polishing with the pixel electrodes
Substrate for display device having an input / output electrode formed by
In the manufacturing method of 1., the insulating layer formed on the surface of the substrate is selectively removed,
In front of the pixel electrode, the input / output electrode, and the periphery of the input / output electrode
The input-to-output voltage to the same polishing rate as serial image display unit
An electrically floating dummy placed around the pole
Form an insulating layer region for separating each electrode
And after forming the insulating layer region, the pixel electrodes are formed on the surface of the substrate.
Electrode material for electrodes, the input / output electrodes, and the dummy electrodes
Forming a material, and polishing the electrode material to form the electrode material on the insulating layer region.
The pixel electrode and the input / output electrodes separated by removing the material.
A step of forming a pole and the dummy electrode, and the pixel electrode, the input / output electrode, and the dummy electrode.
The periphery of the input / output electrodes is the same as the image display unit.
The electrode material so that
A method of manufacturing a substrate for a display device, comprising: