JPH11121554A - Wafer batch type probe card and inspection method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a probe card of a structure, in which at batch wafer type measurement inspection such as wafer type burn-in inspection, semiconductor devices of adjacent chips in a wafer are hardly affected via a common substrate (wafer), and an inspection method of a semiconductor which uses the probe card. SOLUTION: This probe card is provided with a plurality of two- dimensionally arranged bump electrodes and a multilayered wiring board connected electrically with the bump electrodes. A multilayered wiring of the multilayered wiring board contains a plurality of chip selection signal lines CS1-CS4. A plurality of the bump electrodes contain a plurality of bump electrodes (black dots) for chip selection signal, which have a function of supplying the chip selection signal to a plurality of chips contained in a wafer. Among the bump electrodes for the chip selection signal, the bump electrodes connected with a common chip selection signal line are so arranged as to supply the chip selection signal to the plurality of chips selected so as not to be adjacent in a wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer type probe card and a method for inspecting a semiconductor device.

[0002]

2. Description of the Related Art In recent years, electronic devices equipped with a semiconductor integrated circuit device (hereinafter, referred to as a "semiconductor device") have been remarkably reduced in size and price, and accordingly, the size of the semiconductor device has been reduced. Also, demands for lower prices are increasing.

In general, a semiconductor device is supplied after a semiconductor chip and a lead frame are electrically connected to each other by bonding wires, and then the semiconductor chip and the lead frame are supplied in a state of being sealed with resin or ceramics, and mounted on a printed circuit board. Is done. However, due to the demand for miniaturization of electronic equipment, a method of directly mounting a semiconductor device in a state of being cut out from a semiconductor wafer (hereinafter, the semiconductor device in this state is referred to as a bare chip) on a circuit board has been developed. It is desired to supply guaranteed bare chips at a low price.

In order to guarantee the quality of bare chips, it is necessary to inspect semiconductor devices such as burn-in in a wafer state. However, since it takes a lot of time to perform one or several separate inspections on a plurality of bare chips formed on a semiconductor wafer many times, it is realistic in terms of time and cost. is not. Therefore, it is required to perform inspection such as burn-in on all bare chips in a wafer state at once.

In order to inspect a bare chip collectively in a wafer state, a power supply voltage and a signal are simultaneously applied to electrodes of a plurality of semiconductor chips formed on a semiconductor wafer,
It is necessary to operate the plurality of semiconductor chips. For this purpose, it is necessary to prepare a probe card having a very large number of probe needles (usually several thousand or more). To do so, a conventional needle type probe card has a problem in terms of the number of pins. Also can not respond in terms of price.

Therefore, there has been proposed a probe card capable of collectively contacting probe electrodes with a large number of pad electrodes on a wafer (Japanese Patent Application Laid-Open No. Hei 7-231019). According to this technique, a large number of bumps are formed on a probe card, and these bumps are used as probe electrodes.

[0007]

When an inspection such as a burn-in inspection is performed using a wafer batch type probe card, a large number of chips included in each wafer are operated simultaneously. In such an inspection, the operation of a semiconductor device included in each chip may affect the operation of a semiconductor device in another adjacent chip via a common substrate (wafer). In particular, when the semiconductor device is a dynamic RAM (DRA)
In the case where a substrate potential generating circuit is provided as in M), if there is a defective chip such as a substrate leak, an adjacent chip is greatly affected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device of an adjacent chip in a wafer in a wafer batch type inspection such as a wafer batch type burn-in inspection. It is an object of the present invention to provide a probe card having a structure that is hardly affected via a (wafer), and a method for inspecting a semiconductor device using such a probe card.

[0009]

According to the present invention, there is provided a probe card comprising: a plurality of probe electrodes arranged two-dimensionally; and a multilayer wiring board electrically connected to the plurality of probe electrodes. The multilayer wiring of the multilayer wiring board includes a plurality of chip selection signal lines, and the plurality of probe electrodes have a function of supplying a chip selection signal to a plurality of chips included in a wafer. Of the plurality of chip selection signal probe electrodes, the probe electrodes connected to a common chip selection signal line are selected so as not to be adjacent in the wafer. It is arranged to supply the chip select signal to a plurality of chips.

[0010] The probe electrode may be a bump electrode.

[0011] A conductive rubber may be provided between the probe electrode and the multilayer wiring board for electrically connecting the probe electrode to the multilayer wiring.

[0012] The probe electrode may be formed on a thin film that is stretched with tension applied to a rigid ring.

[0013] The probe electrode may be formed from at least a part of the multilayer wiring.

A method for testing a semiconductor device according to the present invention uses a probe card having a plurality of two-dimensionally arranged probe electrodes and a multilayer wiring board electrically connected to the plurality of probe electrodes. In the inspection method of a wafer batch type semiconductor device to be performed, an inspection is performed by supplying a chip selection signal for each set of chips selected so as not to be adjacent to each other among a plurality of chips included in a wafer.

[0015] The probe electrode may be a bump electrode.

[0016] A conductive rubber may be provided between the probe electrode and the multilayer wiring board for electrically connecting the probe electrode to the wiring of the multilayer wiring board.

[0017] The probe electrode may be formed on a thin film that is stretched with tension applied to a rigid ring.

[0018] The probe electrode may be formed from at least a part of wiring of the multilayer wiring board.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, in order to facilitate understanding of the present invention, a description will be given of a wafer collective type measurement / inspection technique to which the present invention is applied.

FIG. 1 shows a probe card 1 which can collectively contact probe electrodes with a large number of pad electrodes on a wafer. A wafer (for example, a silicon wafer having a diameter of 200 mm) on which elements and circuits to be measured and inspected are formed is placed on a wafer tray 3 as it is without being divided into chips.
During measurement and inspection, the wafer 2 is sandwiched between the probe card 1 and the wafer tray 3. A small space formed between the probe card 1 and the wafer tray 3 is sealed from the atmosphere by a seal ring 4. The space is depressurized through the vacuum valve 5 (for example, 200
The pressure is reduced to about millitorr), so that the probe card 1 uniformly presses the wafer 2 by applying the force of the atmospheric pressure. As a result, the probe electrodes of the probe card 1 can press the pad electrodes on the wafer 2 with a uniform force over the entire surface of the wide wafer 2. In order to ensure that a large number of probe electrodes on the probe card 1 are in contact with predetermined pad electrodes on the wafer 2, it is necessary to perform alignment between the probe card 1 and the wafer 2 with high accuracy before the contact. There is.

According to such a wafer collective type measurement / inspection technique, a large number of pad electrodes formed on the probe card 1 are provided for a large number of thousands to tens of thousands of pad electrodes formed on the entire surface of the wafer 2. The probe electrodes can be simultaneously and reliably contacted.

FIG. 2 shows an example of a sectional configuration of the probe card 20 of the present invention.

The probe card 20 has a multi-layer wiring board 21 to be electrically connected to a measurement / inspection device.
, A polyimide thin film 22 with bumps, and a localized anisotropic conductive rubber 23 provided therebetween. The localized type anisotropic conductive rubber 23 is used for the multilayer wiring board 2.
This is an elastic member that electrically connects the first electrode wiring 21b and the bump 22b of the polyimide thin film 22 with bump. FIG. 2 shows a state in which the three members 21 to 23 are separated in the vertical direction. One probe card 20 is formed by tightly fixing these members 21 to 23.

As the multilayer wiring board 21, the glass substrate 2
1a in which a multilayer wiring 21b is formed can be used. The glass substrate 21a is preferable because a glass substrate having high flatness over a wide area can be relatively easily manufactured. In addition, since the thermal expansion coefficient of glass is close to the thermal expansion coefficient of a silicon wafer, glass is particularly suitable as a material for a multilayer wiring board of a burn-in probe card.

The formation of the multilayer wiring 21b can be performed by using a known thin film deposition technique and a known patterning technique. For example, if a conductive thin film such as copper (Cu) is deposited on a glass substrate 21a by a sputtering method or the like and then the conductive thin film is patterned by a photolithography and etching process, a wiring 21b having an arbitrary pattern is formed. be able to. Different levels of wiring 21b are
1c. The interlayer insulating film 21c is formed, for example, by coating a polyimide thin film on the glass substrate 2 by a method such as spin coating.
It is obtained by forming on 1a. The multilayer wiring 21b is
A large number of bumps (probe electrodes) 22b two-dimensionally arranged in a plane are electrically connected to connection electrodes and connectors (not shown) provided in a peripheral area of the probe card 20 to provide an external inspection device or inspection. This enables electrical connection between the circuit and the probe electrode 22b.

The bumped polyimide thin film 22 is obtained, for example, as follows. First, a large number of openings (20 to 30 μm in inner diameter) are formed in a base material in which a polyimide thin film 22 a having a thickness of about 18 μm and a copper thin film
Degree). Each opening is filled with a metal material such as Ni by using a method such as electrolytic plating to form the bump 22b. If unnecessary portions of the copper thin film are removed from the polyimide thin film 22a by etching, the bumped polyimide thin film 22 as shown is obtained. The height of the bump 22b is
As an example, it is about 20 μm. The lateral size of the bump is about 40 μm. Polyimide thin film 22a
The position of the bump 22b to be formed is determined depending on the position of the pad electrode 26 formed on the wafer 25 to be measured.

In the localized type anisotropic conductive rubber 23, conductive particles 23b are arranged at a specific location in a silicone rubber sheet (about 200 μm thick) 23a, and the conduction direction (film thickness direction) ) In a chain. By interposing elastic rubber between the multilayer wiring board 21 and the bumps 22b, the bumps 22b of the probe card 20 and the wafer 25 are not affected by the steps on the wafer 25 and the warpage of the wafer 25. The contact with the upper electrode 26 can be reliably realized.

When such a probe card 20 is used for burn-in inspection, the coefficient of thermal expansion of the polyimide thin film 22a (about 16 × 10 ⁻⁶ / ° C.) and the coefficient of thermal expansion of the wafer 25 (about 3 × 10 ⁻⁶ / ° C.) ), The bump 22b on the polyimide thin film 22a during heating for burn-in.
Is shifted laterally with respect to the position of the pad electrode 26 on the wafer 25. This displacement is greater at the peripheral portion than at the central portion of the wafer 25, and normal electrical contact between the wafer 25 and the probe card 20 cannot be obtained. To solve such a problem, Japanese Patent Laid-Open No. 7-2
As disclosed in Japanese Patent Publication No. 31019, it is effective to attach a polyimide thin film 22a to a rigid ring (not shown) such as a ceramic ring having a thermal expansion coefficient close to that of a silicon wafer, and to apply a tension to the polyimide thin film 22a in advance. It is. In this case, it is better to form the bump 22b after attaching the polyimide thin film 22a to the rigid ring. This is because the position of the bump 22b is not easily shifted.

The wafer 25 is placed on a wafer tray 28. After performing an alignment process so that the wafer tray 28 on which the wafer 25 is mounted is located at an appropriate position with respect to the probe card 20, the distance between the probe card 20 and the wafer tray 28 is reduced. As a result, the pad electrode 26 on the wafer 25 and the bump 22b of the probe card 20
Makes physical contact. As described above, by reducing the pressure in the sealed space between the probe card 20 and the wafer tray 28, each bump 22b presses the pad electrode 26 on the wafer 25 with a substantially uniform force. Thereafter, an electric signal and a power supply voltage from a drive circuit and an inspection circuit (not shown) are supplied to the pad electrodes 26 on the wafer 25 via the bumps 22 of the probe card 20. In the case of the burn-in inspection, the probe card 20, the wafer 25, and the wafer tray 28 are integrally inserted into the burn-in device and heated in a state as shown in FIG.

The probe card 20, the wafer 25, and the wafer tray 28 are maintained in the state shown in FIG. 3 before and after the inspection / measurement. These members integrally hold the wafer 25 without separating from the probe card 20 in the wafer tray 28 in which the above-mentioned closed space is in a reduced pressure state.

When the wafer type inspection / measurement is completed,
The pressure in the closed space formed between the probe card 20 and the tray 28 is increased to restore the pressure to about atmospheric pressure. As a result, the tray 28 is separated from the probe card 20, and the wafer 25 is taken out from the inside.

Hereinafter, a probe card according to the present invention and a method for inspecting a semiconductor device using the probe card will be described in detail with reference to FIG.

FIG. 4 shows a part of a semiconductor integrated circuit chip (hereinafter, referred to as a “chip”) included on a wafer and a part of wiring on a probe card (input / output data lines Data1 to Data1).
Data5 and chip select signal lines CS1 to CS8) are schematically shown. In the present specification, each chip that is finally cut out from the wafer by dicing or the like, even in a state before being cut out from the wafer,
It will be referred to as “chip”.

As shown in FIG. 4, wiring on the probe card is electrically connected to pad electrodes in each chip via bumps (shown by black dots in the figure) on the probe card. Is done. In the example of FIG. 4, a chip belonging to a certain row on the wafer is connected to any of the chip selection signal lines CS1 to CS8 on the probe card. Chips belonging to a certain column on the wafer are connected to any of the common input / output data lines Data1 to Data5 on the probe card. Although FIG. 4 shows only 20 chips,
In reality, more chips are arranged on one wafer, and more input / output data lines and chip select signal lines are provided on the probe card than shown. The number of chips included in one wafer varies depending on the wafer size and chip size, but is typically several hundred.

FIG. 5A schematically shows an example of the arrangement of input / output pads 50 to 53 and a chip selection signal pad 54 on one chip. On the contrary,
FIG. 5B shows an input / output data line 55 on the probe card.
To 58, a chip selection signal line 59, and a part of the bump 60. The bump 60 of FIG.
Are arranged so as to contact the input / output pads 50 to 53 and the chip selection signal pad 54 in FIG. FIG. 5B is a layout diagram of the wiring and bumps seen transparently from the back side of the probe card.

On the actual probe card, a number of other wirings and bumps connected thereto are provided. These different types of wiring are multilayered and insulated from each other via an insulating film so as not to short-circuit each other. The input / output data lines 55 to 58 in FIG. 5B are also formed at a level different from that of the chip select signal line 59 and are insulated from each other.

As shown in FIG. 5A, a chip selection circuit 42 is provided in the internal circuit 41 of the chip, and the chip selection circuit 42 has a chip selection signal pad 59.
It is connected to the. In the wafer batch type burn-in inspection of the present embodiment, the chip selection circuits 42 of the chips belonging to a certain column on the wafer are connected to the common chip selection line 59 on the probe card via the respective chip selection signal pads 54. Receive a chip select signal. When operating chips belonging to a certain row (in some cases, all rows or one row), the chip select signal lines connected to the row (in some cases, in a plurality of rows, in the case of a single row) ) May be applied to the chip selection signal. as a result,
The internal circuit 42 of the chip belonging to the selected row operates, and various operations such as data input / output are executed.

In the present embodiment, the internal circuits 41 of the chips belonging to a certain column on the wafer are connected to the common input / output data lines 55 to 55 on the probe card via the respective input / output pads 50 to 53. 58. Therefore,
When trying to read data in a plurality of chips belonging to a certain column from the input / output data lines 55 to 58, data in a plurality of chips cannot be read at the same time. It is necessary to sequentially read each data from. In order to execute such sequential reading, the above-described chip selection signal may be sequentially applied to the chip selection signal lines CS1 to CS8 so as not to be temporally overlapped. In order to execute such sequential reading, the above-described chip selection signal is applied to the chip selection signal lines CS1 to CS1.
It suffices to sequentially apply the voltage to CS8 so as not to overlap with time. On the other hand, at the time of burn-in inspection, when data is written to each of a plurality of chips belonging to a certain row, inspection data may be written to each chip collectively.

In FIG. 5A, each chip is provided with four input / output pads. However, the number of input / output pads may be one or four or more. . The number of input / output pads differs depending on the bit width of the data to be handled. Further, the number of chips connected to one chip selection line is not limited to the example (five) shown in FIG. Needless to say, the rows and columns may be switched by rotating the running direction of the chip select signal line and the input / output data line by 90 degrees.

Next, the wiring configuration of the probe card according to this embodiment will be described in more detail with reference to FIG. 4 again.

In this embodiment, chips belonging to the same row are alternately connected to two chip select signal lines. For example, in the uppermost row in FIG. 4, the leftmost chip in the figure is connected to the chip select signal line CS2, while the second chip from the left is connected to the chip select signal line CS1. Hereinafter, each chip in that row is alternately connected to a chip selection signal line CS2 and a chip selection signal line CS1. Similarly, in other rows, the chips are alternately connected to two chip select signal lines.

By adopting such a configuration, adjacent chips in the same row can be operated at different timings. Hereinafter, this point will be specifically described.

First, consider a case where a chip select signal is applied to the chip select signal line CS1 and no chip select signal is applied to the other chip select signal lines. In this case, FIG.
, The hatched chip operates. An unselected chip exists between the two hatched chips.
Thus, in this embodiment, adjacent chips in the same row do not operate at the same time. Therefore, it is prevented from being affected by the operation of another adjacent chip via the common substrate. If a defective chip is present next to the chip, it is not adversely affected by the defective operation, so that the inspection can be performed normally.

Next, in addition to the chip selection signal line CS1,
Consider a case where a common chip selection signal is applied to a chip selection signal line CS5 belonging to a row that is not adjacent to the chip row to which the chip selection signal line CS1 belongs, and no chip selection signal is applied to the other chip selection signal lines. . In this case, in addition to the hatched chip, the chip selection signal line CS5
The chip connected to is also operated. However, also in this case, chips operating simultaneously are not adjacent to each other. Therefore, the above-described effects can be obtained. As described above, it is not necessary to apply the chip selection signal lines to all of the plurality of chip selection signal lines at different timings. The effects of the present invention can be sufficiently achieved by connecting each chip select signal line to each chip so that adjacent chips do not receive the chip select signal substantially simultaneously.

FIG. 6 shows four chip select signal lines CS1 to CS1.
An example of a connection relationship between CS4 and chips in a wafer is schematically shown. A chip selection signal can be applied to each of the chip selection signal lines CS1 to CS4 at a different timing. In FIG. 5, the chips connected to the chip selection signal line CS1 are shaded. As is clear from FIG. 5, the chip selection signal line CS1 is not connected to an adjacent chip. Other chip select signal lines CS2 to CS
The same applies to No. 4. By employing such a configuration, it is possible to prevent adjacent chips from operating at the same time. Note that, depending on the inspection mode, a chip selection signal may be simultaneously applied to the chip selection signal lines CS1 to CS4 to operate all the chips in the wafer at the same time.

FIGS. 4 and 5 show that the positions of the pads connected to the chip select signal line are shifted for each chip. However, this is to make the drawing easier to see, and it is not necessary to alternately shift the positions of the pads in the actual chip. For example, as shown in FIG. 7, the chip selection signal line CS1 and the chip selection signal line CS
By patterning 2, the position of the pad does not have to be shifted for each chip. Further, if the chip selection signal lines are formed using three or more layers of multilayer wiring, three or more different chip selection signal lines are allocated to chips belonging to the same chip row, and one chip selection signal line is assigned to one chip selection signal line. Two or more chips connected to another chip select signal line can be arranged between the connected chips. By doing so, the interval between chips operating simultaneously can be further increased.

In the example of the probe card shown in FIG. 2, the multilayer wiring in the multilayer wiring board and the bumps are electrically connected by using the localized anisotropic conductive rubber 23. The multilayer wiring and the bump may be directly contacted without using the conductive rubber 23. Conversely, if bumps are formed on the wafer to be measured, there is no need to form bumps on the probe card side. In that case,
If the tip of the localized anisotropic conductive rubber 23 of the probe card is pressed against the bump on the wafer, the wafer batch type measurement / inspection can be performed. Further, the multilayer wiring of the multilayer wiring board may be directly contacted with the bump on the wafer without using the localized anisotropic conductive rubber 23.

[0048]

According to the probe card of the present invention, a plurality of probe electrodes connected to a common chip select signal line among the probe electrodes for chip select signals are selected so as not to be adjacent in the wafer. Since the chip selection signal is arranged to be supplied to the chip, even if the chip selection signal is applied to the chip selection signal line, chips operating simultaneously are not adjacent on the wafer. Therefore, the influence of the operation of the adjacent chip is not received via the substrate. In particular, when the semiconductor device includes a substrate potential generating circuit such as a dynamic ram (DRAM), if there is a defective chip such as a substrate leak, a problem occurs in measurement of a normal chip. Adverse effects from adjacent chips can be eliminated.

[Brief description of the drawings]

FIG. 1 is a perspective view for explaining a wafer batch type measurement / inspection technique.

FIG. 2 is a cross-sectional view showing a configuration of a probe card, a wafer, and a wafer tray used in a wafer batch type measurement / inspection technique.

FIG. 3 is a sectional view showing the relationship between a probe card, a wafer, and a wafer tray during measurement.

FIG. 4 is a plan layout diagram showing an arrangement of chip select signal lines in the probe card of the present invention.

FIG. 5A is a plan view schematically showing an example of arrangement of input / output pads and chip selection signal pads on one chip, and FIG. 5B is a plan view showing input / output data lines and chips on a probe card; FIG. 3 is a plan layout diagram schematically showing a part of a selection signal line and a bump.

FIG. 6 is a plan layout diagram schematically illustrating an example of a connection relationship between a chip selection signal line and a chip in a wafer.

FIG. 7 shows a chip selection signal line CS1 and a chip selection signal line C;
FIG. 3 is a plan layout diagram illustrating an example of a pattern of S2.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Probe card 2 Wafer (for example, 200 mm diameter silicon wafer) 3 Wafer tray 4 Seal ring 5 Vacuum valve 20 Probe card 21 Multilayer wiring board 21a Glass substrate 21b Electrode wiring 21c Interlayer insulating film 22 Polyimide thin film with bump 22a Polyimide thin film 22b Bump 23 Station Static anisotropic conductive rubber 25 Wafer 26 Pad electrode 28 Wafer tray CS1-CS7 Chip select signal line 50-53 I / O data line 54 Chip select signal pad 55-58 I / O data line 60 Bump

Claims (11)

[Claims] 1. A probe card comprising: a plurality of probe electrodes arranged two-dimensionally; and a multi-layer wiring board electrically connected to the plurality of probe electrodes. Includes a plurality of chip select signal lines, and the plurality of probe electrodes include a plurality of chip select signal probe electrodes having a function of supplying a chip select signal to a plurality of chips included in the wafer. A probe electrode connected to a common chip selection signal line among the plurality of chip selection signal probe electrodes,
A probe card, which is arranged to supply the chip selection signal to a plurality of chips selected so as not to be adjacent in the wafer. 2. The probe card according to claim 1, wherein said probe electrode is a bump electrode. 3. The device according to claim 2, further comprising a conductive rubber between said probe electrode and said multilayer wiring board for electrically connecting said probe electrode to said multilayer wiring. Probe card. 4. The probe card according to claim 2, wherein said probe electrode is formed on a thin film that is stretched while tension is applied to a rigid ring. 5. The probe card according to claim 1, wherein the probe electrode is formed from at least a part of the multilayer wiring. 6. A wafer batch type semiconductor device inspection using a probe card including a plurality of two-dimensionally arranged probe electrodes and a multilayer wiring board electrically connected to the plurality of probe electrodes. A method for inspecting a semiconductor device, comprising: supplying a chip selection signal to each of a set of chips selected so as not to be adjacent to each other among a plurality of chips included in a wafer to perform an inspection. 7. The method according to claim 6, wherein the probe electrode is a bump electrode. 8. A conductive rubber for electrically connecting the probe electrode to wiring of the multilayer wiring board between the probe electrode and the multilayer wiring board. 8. The method for inspecting a semiconductor device according to claim 7. 9. The method for inspecting a semiconductor device according to claim 7, wherein said probe electrode is formed on a thin film in which a tension is applied to a rigid ring. 10. The method according to claim 6, wherein the probe electrode is formed from at least a part of a wiring of the multilayer wiring board. 11. The method according to claim 6, wherein the inspection is a burn-in inspection.