JP2003297887A - Manufacturing method for semiconductor integrated circuit device and semiconductor inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a burn-in inspection and a probe inspection at a wafer level even under a condition that a chip is divided into multiple pins, a test pad is turned to have a narrow pitch and a scribe region between adjacent chips is narrowed. <P>SOLUTION: All the chips 51 within a wafer 4 to be inspected are covered by a semiconductor inspection device by a plurality of times of contacts of the device. By selecting the chips 51 to be inspected per contact by each other column within the main surface of the wafer 4 to be inspected for instance, all the chips 51 within the wafer 4 to be inspected can be covered by twice the contact. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique and a semiconductor inspection device, and more particularly to a technique effectively applied to burn-in inspection and probe inspection in a semiconductor wafer state.

[0002]

2. Description of the Related Art For example, as a technique for inspecting a semiconductor integrated circuit device, a burn-in inspection for screening a chip which may be defective in the future by applying temperature and voltage stress in a high temperature or low temperature atmosphere, and a predetermined function. There are a function test for confirming whether or not they operate normally, and a probe inspection for performing a DC operation characteristic test and an AC operation characteristic test to determine a non-defective product / defective product.

In recent years, in burn-in inspection and probe inspection of semiconductor integrated circuit devices, wafer shipment support (quality differentiation), KGD (Known Good Die) support (MCP)
(Multi-Chip Package Yield Improvement), Burn-In Defective Products Relief, Burn-In Defective Test Data Feedback, Total Cost Reduction, etc. have been used to perform burn-in inspection and probe inspection in the wafer state. .

Regarding the inspection and manufacturing technology of the semiconductor integrated circuit device, the inventors of the present invention have studied the technology related to burn-in inspection and probe inspection. For example, JP-A-11-16963 and JP-A-9-283 disclose.
575, JP-A-11-121535, JP-A-11-121554, and JP-A-3-276656.
Japanese Patent Laid-Open No. 7-235572, Japanese Patent Laid-Open No. 2001-2001
-210685, JP 2001-77162 A, JP 64-39559 A, JP 2001-9 A
1544, JP 2001-174078 A,
And January 1, 2000, published by Nikkei BP, "Nikkei Microdevice 2000 January", P148-P1.
53, and the like.

Japanese Unexamined Patent Application Publication No. 11-16963 uses a probe card having a plurality of stylus groups at a plurality of spaced positions, and a plurality of semiconductors included in a semiconductor wafer (hereinafter simply referred to as a wafer) corresponding to the probe card. Chip (hereinafter,
A technique of dividing a plurality of chips into a plurality of blocks and inspecting each of the chips at a separated position is disclosed.

In Japanese Patent Laid-Open No. 9-283575, when the electrodes of each chip on the wafer are arranged in the X and Y directions, a probe unit extending in the X direction and a probe unit extending in the Y direction are disclosed. A technique for inspecting all the chips on a wafer by a small number of simultaneous contacts by using a probe card formed by combining with a probe unit is disclosed.

Japanese Unexamined Patent Publication No. 11-121553 discloses a probe including a plurality of two-dimensionally arranged probe electrodes and a wiring board in which wirings electrically connected to the plurality of probe electrodes are formed in multiple layers. There is a description of a technique that uses a card to perform burn-in inspection, etc., on multiple chips contained in the wafer in a wafer state, and divides the wafer into multiple blocks so that the number of chips that can be inspected at one time is optimized. Disclosed is a technique for collectively performing inspection for each block by arranging data lines on the probe card so that data can be collectively read out in block units from a plurality of chips.

Japanese Unexamined Patent Publication (Kokai) No. 11-121554 discloses a probe comprising a plurality of two-dimensionally arranged probe electrodes and a wiring board in which wirings electrically connected to the plurality of probe electrodes are formed in multiple layers. There is a description of a technique of performing burn-in inspection in a wafer state on a plurality of chips included in a wafer by using a card. The wiring formed on the wiring board includes a plurality of chip selection signal lines, A technique is disclosed in which a plurality of chips to be inspected are selected so as not to be adjacent to each other by a signal and inspected.

Japanese Unexamined Patent Publication (Kokai) No. 3-276656 discloses a test using a semiconductor test apparatus having a probe card for positioning test probe needles on electrodes in a chip area arranged in a matrix in a wafer. There is a description of the technique to be carried out, and the probe card has a substrate provided with a plurality of probe centers corresponding to the center of the chip region sandwiching at least one chip region, and arranged around each probe center. A technique for simultaneously testing three or four chip areas by using the semiconductor testing device having a plurality of probe needles and having such a probe card is disclosed.

Japanese Unexamined Patent Publication No. 7-235572 uses a probe card having a plurality of vertical probe needles corresponding to 8 continuous chips in the wafer and 2 continuous chips in the wafer. After setting the chip area of 1 as one index area, and then setting this area on the wafer as the contact area, the area that is the minimum area formed when all the chips on the wafer are covered , A technique for reducing the number of index feeds and improving the inspection efficiency by index-feeding a wafer in the contact region according to the shortest path from the first index region to the last index region is disclosed.

Japanese Patent Laid-Open No. 2001-210685 discloses that
A technology for performing an inspection without using a tester by forming an inspection circuit on a probe card or a wafer on which a chip to be inspected is formed and electrically connecting the inspection circuit and the inspected chip to perform the inspection. There is a description about
A technique of disposing inspection circuit modules at a predetermined interval on a probe card formed on a wafer different from the wafer to be inspected, and inspecting a plurality of chips on the wafer to be inspected by one corresponding inspection circuit module. Is disclosed.

In Japanese Unexamined Patent Publication No. 2001-77162, a wafer having a plurality of chips having a plurality of external pads arranged in a matrix is prepared, and a plurality of terminals for receiving an inspection signal and a power supply signal transmitted from a tester are prepared. And at least one probe card having a plurality of probe groups provided corresponding to the plurality of external pads is prepared, and a test signal and a power signal are independently supplied from the tester to the probe groups. In this way, a test signal and a power supply signal are independently and simultaneously supplied to chips in two rows and at least two columns, and electrical characteristics of a plurality of chips are independently and simultaneously measured.

In Japanese Patent Laid-Open No. 64-39559, a probe made of a conductive elastic material is provided perpendicular to the main surface of each pad so that the pads of a plurality of chips in a wafer can be probed at one time. There is a description of a technique for performing an inspection using a probe card provided as described above, and a technique for making good contact between the probe and the pad by applying a uniform stylus pressure to the pad by high-pressure gas is disclosed. ing.

In Japanese Unexamined Patent Publication No. 2001-91544, a beam having elastic properties in the vertical direction is formed on a silicon substrate by a micromachining technique, and microcontacts are arranged at the tip of the beam so as to be opposed to the electrodes of the wafer. A technique for forming a pin by processing a conductive thin film on the tip portion is disclosed.

Japanese Patent Laid-Open No. 2001-174078 discloses that
In a probe card for electrically inspecting a semiconductor integrated circuit in a wafer state, there is a description of a technique for collectively forming metal bumps for contacting pads or solder balls on a wafer on an insulating substrate. By inserting an elastic layer corresponding to the metal bump in a one-to-one relationship between the metal bump and the metal bump, the metal bump is independently suspended, and the insulating substrate is selected as a material having the same coefficient of thermal expansion as the wafer to be inspected. A technique for preventing the pad and the metal bump from being displaced from each other even under high temperature conditions is disclosed.

"Nikkei Microdevice January 2000" includes a TPS (Three Parts) consisting of three parts: a multilayer wiring board, a thin film sheet with bumps, and an anisotropic conductive rubber.
Structure) A method using a probe, or a multilayer wiring board and a probe terminal. The probe terminal has a structure in which a copper post penetrates through a resin sheet. When pressed, this copper post is crushed and the height variations of the electrodes are absorbed. The method is described.

[0017]

DISCLOSURE OF THE INVENTION By the way, as a result of the present inventors' examination of the above-mentioned techniques relating to burn-in inspection and probe inspection, the following has been clarified.

In the technique of performing the burn-in inspection and the probe inspection in the wafer state, a probe of 10,000 pins or more is required on the entire surface of the wafer, but the number of probe pins that can be measured by a measuring device such as an LSI tester and a burn-in device is limited. However, there is a problem that measurement cannot be performed on a wafer that requires a probe having a pin number exceeding the limit.

Further, there is a restriction on the maximum value of the pressing load of the wafer batch contactor. For example, in the case of a wafer batch contactor by vacuum suction, the atmospheric pressure (1 kgf / c
The pressing load of m ² ) becomes maximum. Here, assuming that the pin load on the probe necessary for making electrical connection between the probe and the inspection pad is 10 gf per pin, 1 cm ²
If the number of pins exceeds 100 pins, that is, if the wafer has 100 or more pads per cm ^2, there is a problem that measurement cannot be performed.

With the increase in the number of pins on the chip, the narrower pitch of the test pads, and the narrower scribe area between adjacent chips, the wiring sheet of the wafer batch contactor, the wiring pattern on the wiring board, and Since it becomes difficult to secure the minimum required area for securing the wiring interval, there is a problem that the routing and drawing of the wiring are restricted. Further, if the number of the extraction pads included in the wafer batch contactor increases, the area required for arranging the extraction pads also increases, so that there is a problem in that the wafer batch contactor is restricted in external dimensions.

When the number of contact pins of the wafer to be measured increases, the wiring routing area and the signal line branch of the wafer batch contactor increase,
Due to the increase of resistance, capacitance and noise of the wiring,
There is a problem that the electrical characteristics of the wafer batch contactor deteriorate and the measurement accuracy decreases.

Further, when the test pads of the chip to be measured are arranged in the peripheral portion on the pad arrangement surface of the chip, if the scribe area between the adjacent chips is narrowed, the test pads of the adjacent chips are separated from each other. There is a problem that it is difficult to secure the beam length of the contact probe and the area for routing the wiring with respect to the distance.

An object of the present invention is to perform burn-in inspection and probe inspection in a wafer state even in a situation where the number of pins of a chip is increased, the pitch of test pads is narrowed, and the scribe area between adjacent chips is narrowed. It is to provide the technology that can.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0025]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention is divided into a plurality of chip regions, a semiconductor integrated circuit is formed in each of the plurality of chip regions, and a plurality of terminals electrically connected to the semiconductor integrated circuit on the main surface. A step of preparing a semiconductor wafer on which is formed, a plurality of contact mechanisms for contacting the plurality of terminals, and a first wiring electrically connected to the plurality of contact mechanisms, A step of preparing a first substrate holding the plurality of contact mechanisms so that each tip projects toward the main surface of the semiconductor wafer; and the semiconductor integrated circuit by contacting the plurality of contact mechanisms with the plurality of terminals. Performing an electrical inspection of a circuit, the main surface of the semiconductor wafer is divided into a plurality of first regions, each of the plurality of chip regions are arranged in any of the plurality of first regions, Serial electrical testing is performed for each of the plurality of first regions.

Further, the present invention (a) is arranged on the main surface of a semiconductor wafer divided into a plurality of chip regions, and is electrically connected to a semiconductor integrated circuit formed in each of the plurality of chip regions. A plurality of contact mechanisms for contacting a plurality of terminals; (b) a first wiring electrically connected to the plurality of contact mechanisms; (c) each tip of the plurality of contact mechanisms is the main part of the semiconductor wafer. A first substrate that holds the plurality of contact mechanisms so as to project toward a surface, and the plurality of contact mechanisms are brought into contact with the plurality of terminals to electrically test the semiconductor integrated circuit; In the electrical inspection, the main surface of the semiconductor wafer is divided into a plurality of first regions, each of the plurality of chip regions is arranged in one of the plurality of first regions, and then the plurality of first regions are arranged. This is done for each of the areas.

[0028]

DETAILED DESCRIPTION OF THE INVENTION Before describing the present invention in detail,
The meanings of the terms in the present application are as follows.

A wafer is a single crystal silicon substrate (generally a substantially circular plane) used for manufacturing integrated circuits, or SOI (Si
licon On Insulator) substrate, sapphire substrate, glass substrate, other insulating, anti-insulating or semiconductor substrate, and a composite substrate thereof. Further, in the present application, the semiconductor integrated circuit device is not limited to a device formed on a semiconductor or an insulating substrate such as a silicon wafer or a sapphire substrate, and unless otherwise specified, T
FT (Thin Film Transistor) and STN (Super-Tw
isted-Nematic) It includes those made on other insulating substrates such as glass such as liquid crystal.

The device surface is the main surface of the wafer and
A surface on which a device pattern corresponding to a plurality of chip regions is formed by lithography is referred to.

The contact mechanism is a wafer process similar to that used for manufacturing a semiconductor integrated circuit, that is, a photolithography technique, CVD (Chemical V).
apordeposition) technology, sputtering technology, etching technology, and other patterning techniques are used to integrally form a test needle having a wiring layer and a tip connected to it, as well as on a polyimide film or other sheet-like insulating film. Including printed wiring and needles.

The probe needle, or simply a needle, is not limited to a traditional probe needle-shaped tip, but also a needle-shaped contact terminal with a narrowed tip, a pyramid-shaped contact terminal, a bump electrode of another shape, etc. Shall be included.

The probe inspection is to conduct an electrical inspection of a semiconductor integrated circuit by applying a tip of a probe needle to a terminal formed on the main surface of a chip area, and whether or not the semiconductor integrated circuit operates according to a predetermined function. The non-defective product / defective product is determined by performing a functional test for confirming the above and a DC operation characteristic test and an AC operation characteristic test.

The burn-in test is a screening of chips that may be defective in the future by applying temperature and voltage stress in a high temperature or low temperature atmosphere.

KGD (Known Good Die) means a chip which is mounted in a bare chip state such as flip chip bonding and is guaranteed to be a good product. Here, the guarantee of non-defective products means that they have been screened.

The wafer map is a display of the inspection results of each chip in the wafer inspection according to the arrangement of the chips, and is used to judge the distribution of the processing state of the wafer and the quality of the wafer processing.

The index time is the time until the inspection of one chip or wafer is completed and the positioning of the next chip or wafer is completed and the inspection can be started when the chips or wafers are continuously inspected. It means the time.

In the following embodiments, when there is a need for convenience, they will be described by being divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, One is in the relation of some or all of modifications of the other, details, supplementary explanations, and the like.

In the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.) of elements, it is limited to a specific number when explicitly stated and in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relations, etc. of constituent elements, etc., except when explicitly stated or when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included or similar. This also applies to the above numerical values and ranges.

Further, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

Further, in the drawings used in the present embodiment, even in a plan view, the chip regions related to the steps are hatched in order to make the drawings easy to see.

Further, in this embodiment, a MISFET (Metal Insulato) representing a field effect transistor is used.
r Semiconductor Field Effect Transistor)
Abbreviated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the same reference numerals will be repeated. The explanation is omitted).

(Embodiment 1) First, an example of a method of manufacturing the semiconductor integrated circuit device of Embodiment 1 will be described with reference to FIG. FIG. 1 is a flow chart showing a method for manufacturing a semiconductor integrated circuit device. In the first embodiment, an SRAM (Static Random Access Memory) is used as a semiconductor integrated circuit device.
y) and electrical batch erase type EEPROM (Electric Erase
MCP (Multi Chip Pac) with embedded asable Programmable Read Only Memory;
kage) will be described as an example.

First, a large number of elements forming each of the SRAM and the flash memory are formed on the device surfaces (main surfaces) of different wafers by the pretreatment process.
That is, in this step, based on the specifications of the SRAM and the flash memory, for example, oxidation, diffusion, impurity implantation, wiring pattern formation, insulation layer formation and wiring layer formation are performed on a semiconductor wafer made of single crystal silicon. Each wafer processing step is repeated to form a desired integrated circuit (steps SS1 and SF1).

Next, a TEG (Test Eleme) formed in a scribe area that divides the wafer into a plurality of chip areas.
nt group) to perform DC operation characteristic test of MIS. That is, the threshold voltage of the MIS forming the TEG is measured to measure the threshold voltage of the MIS forming each of the SRAM and the flash memory (steps SS2 and SF2).

Next, an inspection (wafer level inspection) is performed on the wafer on which many elements are formed. Here, the burn-in inspection and the probe inspection are performed in that order, and a simple probe inspection may be inserted before the burn-in inspection if necessary. In the burn-in inspection, for example, in a high temperature (for example, 125 to 150 ° C.) atmosphere of a wafer, a power supply voltage higher than or equal to the rated voltage is applied to cause current to flow through an integrated circuit, and temperature and voltage stress may be applied to cause future defects. Screen for potential chips. In this wafer-level burn-in inspection process, a wafer whole surface contact type inspection device of a divided contactor integrated type described later is used. Also,
In the probe inspection, for example, the wafer is heated to a high temperature (for example, 8
(5 to 95 ° C.) In a atmosphere, a function test for testing the memory function by using a predetermined test pattern by writing and reading operations to the SRAM and the flash memory and confirming whether or not the memory cell operates according to the predetermined function, Open / short test between input / output terminals, leak current test, DC test such as power supply current measurement, memory control A
An AC test for testing the C timing is performed. Also in this wafer level probe inspection process, it is possible to use the inspection apparatus of the integrated wafer whole surface contact method by the division contactor integrated type described later (step SS).
3, SF3). By performing such a wafer level inspection, it becomes possible to feed back defective data such as a burn-in inspection to the pretreatment process. Thereby, the trouble of the pretreatment process can be improved.

Further, the steps SS3 and SF as described above are performed.
In item 3, an inspection having a long inspection time like the burn-in inspection time (about 8 hours to 48 hours), for example, a long cycle test or a refresh test (about 1 hour to several tens of hours) may be performed. By performing such an inspection with a long inspection time at the wafer level, the throughput of manufacturing the semiconductor integrated circuit device according to the first embodiment is significantly increased as compared with the case where such an inspection is performed after dividing into individual chips. Can be improved.

Next, as a result of the burn-in test and the probe test, a defective element is irradiated with laser light to be repaired. That is, in this step, the probe inspection result is analyzed to find the defective bit in the SRAM and the flash memory, the fuse of the redundant repair bit corresponding to this defective bit is blown with laser light, and the redundant repair process is performed to perform repair. This is done (step SS4, SF
4). After this repair process, the same wafer level burn-in inspection process and wafer level probe inspection process as the wafer level burn-in inspection process and wafer level probe inspection process shown in steps SS3 and SF3 may be performed. This step is to confirm that the defective bit can be switched to the redundant relief bit by the redundant relief process. Here, an interference test of the memory cells of the SRAM and the flash memory, which can be performed only after the redundancy repair process, such as a disturb refresh test, may be performed. Further, the memory cells of the flash memory may be tested for writing and erasing at the wafer level (steps SS5 and SF5).

Next, each of the wafer on which the SRAM is formed and the wafer on which the flash memory is formed is cut into individual chips (steps SS6 and SF6). Here, it is also possible to ship a non-defective wafer as a product as it is without cutting (steps SS7, SF7).

When assembling the chip in which the SRAM is formed and the chip in which the flash memory is formed in the MCP, the die bonding step of mounting the chip in which the SRAM is formed and the chip in which the flash memory is formed on the mounting substrate, A wire bonding process for electrically connecting the pads of each chip to the pads on the mounting substrate with wires, a resin molding process for molding with a resin to protect the chip and wire portions, and molding and surface treatment of external leads. Performs lead forming process. Not limited to wire bonding, flip chip bonding or the like is also possible (step SP
7). The MCP assembled in this way can be shipped as a product and provided to the user (step SP
8).

According to the method of manufacturing a semiconductor integrated circuit device of the first embodiment as described above, the burn-in inspection and the probe inspection are performed before the MCP is assembled, so that a defect due to the burn-in inspection or a defect due to the probe inspection is found. It is also possible to remedy chips that have been damaged. As a result, since the MCP can be assembled by KGD, the yield of the MCP can be greatly improved. Further, the effect increases as the number of chips mounted on the MCP increases.

Further, by applying the burn-in inspection and the probe inspection at the wafer level, the total index time can be shortened. Furthermore, by carrying out the wafer level inspection, the number of chips that can be inspected at the same time can be increased. From these, it is possible to improve the throughput of the wafer inspection process.
It is possible to reduce the manufacturing cost of the semiconductor integrated circuit device of the first embodiment.

Next, an example of the semiconductor inspection apparatus according to the first embodiment for performing the above-mentioned burn-in inspection at the wafer level will be described with reference to FIGS.

The semiconductor inspection apparatus according to the first embodiment is a semiconductor inspection apparatus for performing burn-in inspection by a mechanical pressure method. As shown in FIG. 2, the semiconductor inspection apparatus according to the first embodiment includes, for example, a plurality of divided silicon contactor blocks (first substrate) 1 and a guide frame that integrates these silicon contactor blocks 1 with high accuracy. 2, the elastomer 3 that absorbs the probe height variation of the silicon contactor block 1, the silicon contactor block 1 integrated with the guide frame 2, and the elastomer 3, and the wafer 4 to be inspected is sandwiched and packed from above and below. Therefore, the wafer cassette is composed of an upper lid (first holding mechanism) 5 and a lower lid (first holding mechanism) 6 for the above. On the upper portion of the upper lid 5, a wiring board electrically connected to the multilayer wiring board of each silicon contactor block 1 by a cable and used for burn-in inspection of the wafer 4 to be inspected (first
A wiring board) 7 is provided.

Since the semiconductor inspection apparatus according to the first embodiment shown in FIG. 2 adopts the divided contactor integrated type system, repair can be performed for each divided silicon contactor block 1, thereby reducing the cost. It is possible to plan. For example, one silicon contactor block 1 realizes a chip count = 8 chips × 4 rows = 32 chips. In the semiconductor inspection apparatus according to the first embodiment, with respect to one inspected wafer 4, the silicon contactor block 1 covers the entire surface of the inspected wafer 4.
For example, 22 chips are required according to the number of chips acquired.

Each silicon contactor block 1 includes, for example, as shown in FIG. 3, a silicon contactor (contact mechanism) 11 having a plurality of test needles, and a ceramic substrate 12 electrically connected to the silicon contactor 11.
An ACF (Anisotropic Conductive Film) 13 for adhering the silicon contactor 11 and the ceramic substrate 12,
It is composed of a connector 14 for electrically connecting the ceramic substrate 12 and the wiring substrate 7, and a cover 15 for covering these from the top. The connector 14 has an FPC (Flexible Printed Circuit) for electrically connecting to the wiring board 7.
cuit) Cable is connected.

The silicon contactor 11 of each silicon contactor block 1 is a member that makes contact with a plurality of chips of the wafer 4 to be inspected.
And a silicon substrate which is a material having the same thermal expansion coefficient. On the surface (lower side in FIG. 3) of this silicon contactor 11, for example, as shown in FIG.
A plurality of probe portions (for example, the number of probes corresponding to the inspection pads formed on 32 chips) including 7 and beams 18 that support the probes 17 are provided.
Each probe 17 has a protrusion shape that makes electrical contact with an inspection pad of each chip of the wafer 4 to be inspected, and is formed in a pyramid shape by a micromachining technique such as anisotropic etching. Further, the portion of the beam 18 around the probe 17 can be deformed, for example, from the state of FIG. 5 to the state of FIG. 6 by the pressure by the mechanical pressurizing method.
7 is uniformly contacted with the inspection pad of each chip of the wafer 4 to be inspected at a predetermined pressure. 5 and 6 are cross-sectional views taken along the line AA in FIG.

On the front and back surfaces of the silicon contactor 11, for example, Au (gold), Cu (copper), Ni
(Nickel), Rh (Rhodium), Pd (Palladium)
A wiring layer made of a combination of the above is formed by plating, and the wiring patterns on the front wiring layer and the back wiring layer can be electrically connected through through holes. For example, as shown in FIGS. 4 to 6, the protrusions of the probe 17 of the silicon contactor 11 include the wiring patterns (first wiring) 21 and 21A of the wiring layer on the front surface, the through holes 22 penetrating from the front surface to the rear surface, and the back surface. The wiring pattern (first wiring) 23, 23A of the wiring layer is electrically connected to the pad 24. The surface of the silicon contactor 11 is covered with an insulating film 25 so that the protrusion of the probe 17 is exposed. The wiring patterns 21, 21A, 23, 23A on the front surface and the back surface are, for example, as shown in FIG. 4, compared to the wiring patterns 21, 23 for the signal line, the wiring patterns 21A, 23 for the power supply and ground lines.
A has a thick wiring width. Further, as shown in FIG. 5, for example, the wiring patterns 21 (21
A) and 23 (23A), the protrusion of the probe 17 has a thin plating thickness, and the other portions have a thicker plating thickness in order to lower the resistance value.

The ceramic substrate 12 is a substrate member having a multilayer wiring structure made of a ceramic base material, in which a large number of wirings corresponding to a plurality (for example, 32) chips of one silicon contactor 11 are routed. Further, it has a structure capable of converging (for example, 1/10) input signals from a plurality of chips. Further, on the surface (upper side in FIG. 3) of the ceramic substrate 12, for example, a chip resistor 31 and a chip capacitor 32 for protection against power fluctuation, overcurrent and noise are mounted, and a connector 14 can also be mounted. (See Figure 3). This ceramic substrate 12
Is a land (not shown) on which the chip resistor 31, the chip capacitor 32, the connector 14 and the like are mounted,
It is electrically connected to the pad on the back surface through the wiring pattern and the through hole. The pad on the back surface of the ceramic substrate 12 is electrically connected to the pad 24 of the silicon contactor 11 via the ACF 13 bonded to the back surface of the ceramic substrate 12, whereby the probe 17 of the silicon contactor 11 is connected to the ceramic substrate 12 ,
Wiring board 7 through connector 14 and FPC cable
Electrically connected up to.

The cover 15 is a member for covering the silicon contactor block 1 and is adhered to the ceramic substrate 12 to serve as a reinforcement. For example, as shown in FIG. 3, the connector 15 of the ceramic substrate 12 is provided on the cover 15.
A through hole 33 for the FPC cable connected to 4 is formed, and an escape space (not shown) for the chip resistor 31 and the chip capacitor 32 is also formed inside. Further, a screw hole 34 is formed in the cover 15, and the cover 15, the ceramic substrate 12, the ACF 13, and the silicon contactor 11 are bonded and integrated, and are inserted from the upper portion of the upper lid 5 through the elastomer 3. Then cover 15
It is adapted to be positioned by a hanging screw 35 which is screwed into the screw hole 34 (see FIG. 2).

The guide frame 2 of the wafer level burn-in cassette is divided into silicon contactor blocks 1
Is a member for integrally fixing the horizontal position and is made of a material having a thermal expansion coefficient close to that of the wafer 4 to be inspected, such as 42 alloy or nickel alloy. For example, each of the divided silicon contactor blocks 1 is positioned in each of the guide frames 2 divided into a plurality of frames, and each of the divided silicon contactor blocks 1 is individually housed in a state of independently moving in the vertical direction (see FIG. 2). As a result, a contact method for the entire surface of the wafer is realized by the integrated contactor type.

The elastomer 3 (see FIG. 2) is a member for absorbing the height variation of the probe of the silicon contactor block 1, and is made of a polymer material such as silicon rubber. The elastomer 3 allows the silicon contactor blocks 1 integrated with the guide frame 2 to move independently, so that the height variations of the probes 17 (see FIGS. 4 to 6) of the silicon contactors 11 are absorbed. .

The upper lid 5 and the lower lid 6 shown in FIG. 2 are made of, for example, SUS or aluminum. Figure 7
As shown in FIG. 2, by using the upper lid 5 and the lower lid 6, the wafer 4 to be inspected is sandwiched, and the silicon contactor block 1 and the elastomer 3 integrated with the guide frame 2 are provided above the wafer 4 to be inspected. It can be packed from the top and bottom. The upper lid 5 and the lower lid 6 can be positioned by a fixing screw 36 which is inserted from the upper portion of the upper lid 5 and screwed into the lower lid 6. Also,
The inner surface of the lower lid 6 is flat, and
A vacuum suction mechanism including a vacuum holding hole 37 (see FIG. 2), a vacuum holding groove 38 (see FIG. 2), a micro coupler 39 (see FIG. 2), and the like for sucking so as to evenly warp and swell the same, and temperature conditions. A temperature control mechanism including a surface heater 40, a temperature sensor 41, contacts 42 (see FIG. 2) and a connector 43 (see FIG. 2) for controlling

The wiring substrate 7 (see FIG. 2) is the ceramic substrate 12 of the silicon contactor block 1 (see FIG. 3).
And a burn-in device (not shown). In the burn-in inspection, a test control signal is supplied from the burn-in device, and the test is performed by acquiring the test result signal. Further, the wiring board 7 is provided with an overcurrent cutoff circuit (not shown) or the like to cut off the overcurrent of each chip of the wafer 4 to be inspected, thereby suppressing the separation of defective chips and the occurrence of latch-up. There is.

When performing the burn-in inspection at the wafer level using the mechanical pressure type semiconductor inspection apparatus of the first embodiment as described above, the upper cover 5 and the lower cover 6 are integrated with the guide frame 2. Silicon contactor block 1,
With the elastomer 3 and the wafer to be inspected 4 packed, each individually moving silicon contactor block 1 is mechanically pressed to cause each probe 17 of the silicon contactor 11 to inspect each chip of the wafer to be inspected 4. To a uniform pressure. Then, a test control signal for burn-in inspection is supplied from the burn-in device to each chip of the inspected wafer 4 via the wiring board 7 and each ceramic substrate 12, and this test result signal is supplied from each chip of the inspected wafer 4 to the ceramic. By using the burn-in device to obtain the chips via the substrate 12 and the wiring substrate 7, it is possible to screen chips that may be defective in the future.

At this time, the wafer 4 to be inspected has the vacuum holding hole 3
A vacuum suction mechanism including a vacuum holding groove 38, a micro coupler 39, and the like suctions the lower lid 6 by suction so as to smooth warpage and undulation, and then packs by mechanical pressure. Further, the surface heater 40 is formed by connecting the contact 42 provided on the upper lid 5 and the connector 43 provided on the lower lid 6,
The temperature control mechanism including the temperature sensor 41 and the like operates to control the temperature condition of the wafer 4 to be inspected. Further, even under the high temperature condition during the burn-in inspection, the wafer 4 to be inspected and the silicon contactor 11 similarly thermally expand, and the guide frame 2 also has a thermal expansion close to that of the wafer 4 to be inspected. The alignment accuracy between each probe 17 and each inspection pad of each chip of the wafer 4 to be inspected can be sufficiently obtained.

By the way, as for the technique of performing the burn-in inspection at the wafer level by using the semiconductor inspection device having the silicon contactor, for example, Japanese Patent Application No. 2 by the present inventors.
000-304099 and US patent application 09/96
No. 4,708. Further, the semiconductor inspection apparatus according to the first embodiment described above uses the wafer-level probe inspection described above with reference to FIG. 2 (step SS3,
It may be used in SF3).

Next, the wafer level inspection of the first embodiment will be described in detail with reference to FIGS.

As shown in FIG. 8, each chip 51 of the wafer 4 to be inspected has a DFT (Design For Testability) design, in addition to the memory circuit 52, for example, a BIST (Built-In Self Test) circuit for wafer level burn-in. 53
Are formed. The BIST circuit 53 is provided with a register circuit 54, a control circuit 55, a counter circuit 56, a decoder circuit 57 and the like. Chip 5
By incorporating the BIST circuit 53 in the chip 1, the number of inspection pads (first terminals) 58 required for inspection is 40 to 80 out of all pads (terminals) provided in one chip 51. It can be reduced to about 6 to 20. For example, as the inspection pad 58, 6 pins of a wafer level burn-in clock signal, a test mode set signal, a wafer level burn-in entry signal, an input / output signal, a power supply and a ground can be assigned. A method of arranging the inspection pad 58 will be described later in detail. In the first embodiment, the BIS
The case of forming the T circuit 53 has been exemplified, but the BIS
A circuit similar to the T circuit 53 may be formed outside the chip 51 (for example, the wiring board 7 (see FIG. 2)) to form a so-called BOST (Built-Out Self Test) circuit. The technique using the BOST circuit is described in, for example, Japanese Patent Application No. 2001-398832.

In wafer-level burn-in BIST circuit 53, register circuit 54, control circuit 55 and counter circuit 56 operate in synchronization with a wafer-level burn-in clock signal. The wafer level burn-in operation is started by the input of the test mode set signal and the wafer level burn-in entry signal, the test data input to the register circuit 54 is used as the input signal, and the counter circuit 56 is controlled based on the control of the control circuit 55. While the address is being incremented, the decoder circuit 57 decodes it into a test pattern to perform a burn-in test of the memory circuit 52. As a result of the burn-in inspection, the determination signal of good or bad of the memory circuit 52 is
It is output as an output signal via the determination circuit 59. Further, as an output signal, a carry signal of counter circuit 56 is output as a signal for confirming burn-in operation.

9 to 12 show the wafer 4 to be inspected of the chip (first region) 51 (see FIG. 8) inspected by one contact of the semiconductor inspection apparatus of the first embodiment.
It is a top view which shows the selection method in the inside, and the selected chip 51 is shown with hatching. Also, FIG.
In FIG. 12, the arrangement of the chips 51 in the region SCBR covered by one silicon contactor block 1 is enlarged and shown. In addition, the case where six silicon contactor blocks 1 are applied to the entire surface of the wafer is shown.

9 and 10 show a chip 51 for covering all the chips 51 in the wafer 4 to be inspected by two contacts of the semiconductor inspection device of the first embodiment.
It shows the selection method of. The example shown in FIG. 9 is 1
Chips 51 to be inspected by each contact are selected every other row in the main surface of the wafer 4 to be inspected. In the example shown in FIG. It is selected so as to have a so-called checkered pattern, which is arranged on a diagonal line.

FIG. 11 shows a method of selecting the chips 51 for covering all the chips 51 in the wafer 4 to be inspected by three contacts of the semiconductor inspection apparatus of the first embodiment. The figure shows a case where chips 51 to be inspected by each contact are selected every two rows in the main surface of the wafer 4 to be inspected. FIG. 12 shows a method of selecting the chips 51 for covering all the chips 51 in the wafer 4 to be inspected by four contacts of the semiconductor inspection apparatus of the first embodiment. It shows the case where every other chip 51 to be inspected by the contact is selected so as not to be adjacent to each other.

Here, in the semiconductor inspection apparatus according to the first embodiment, the probe 17 described with reference to FIGS. 4 to 6 has 10,000 pins on the main surface of the wafer 4 to be inspected and is formed on the chip 51. Assuming that there are 20 inspection pads 58 (see FIG. 8), when the number of chips 51 formed on the wafer 4 to be inspected exceeds 500, all the chips 51 are formed at one time. The probe 17 cannot be brought into contact with all the inspection pads 58.
In particular, when a wafer having a large diameter (for example, a wafer having a diameter of 12 inches (about 30.48 cm)) is handled as the inspection wafer 4, the number of chips 51 formed on the inspection wafer 4 also increases. There is a high possibility that the probes 17 cannot be brought into contact with all the inspection pads 58 formed on all the chips 51 at one time. Therefore, FIG.
As shown in FIG. 12, in the wafer 4 to be inspected, a chip 51 to be inspected by one contact of the semiconductor inspecting apparatus of the first embodiment is selected, and all chips 51 are inspected by a plurality of contacts. Perform an inspection. As a result, the chips 5 formed on the wafer 4 to be inspected
Even when the number of inspection pads 58 exceeds 1 and the number of inspection pads 58 exceeds 1, the burn-in inspection can be performed at the wafer level.

Further, for example, the pin load on the probe 17 required for making electrical connection between the probe 17 and the inspection pad 58 is 10 gf per pin, and the diameter of the wafer 4 to be inspected is about 8 inches. 20.32 cm), the maximum load resistance of the vacuum suction mechanism (see FIG. 2) including the vacuum holding hole 37, the vacuum holding groove 38, the micro coupler 39, and the like included in the semiconductor inspection apparatus of the first embodiment is 12 at maximum.
Assuming 0 kgf, when the number of inspection pads 58 in the main surface of the wafer 4 to be inspected exceeds 12000, the pin load on the probe 17 necessary for electrical connection is insufficient. Will end up. That is,
When the number of inspection pads 58 formed on the chip 51 is 20, the chips 5 formed on the wafer 4 to be inspected
If the number of 1's exceeds 600, all the chips 51 cannot be inspected by the contact of the semiconductor inspecting device of the first embodiment. Therefore,
As described above with reference to FIG. 8, in the first embodiment, each chip 51 is provided with a wafer-level burn-in BIST.
By incorporating the circuit 53, the number of inspection pads 58 required for inspection is reduced, and further, as shown in FIGS. 9 to 12, the semiconductor inspection according to the first embodiment is performed within the wafer 4 to be inspected. Chips 51 to be inspected by one contact of the device are selected, and all chips 51 are inspected by a plurality of contacts. As a result, it is possible to prevent the problem that the pin load on the probe 17 necessary for making the electrical connection between the probe 17 and the inspection pad 58 is insufficient. As a result, even if the number of the inspection pads 58 increases in the main surface of the wafer 4 to be inspected, the burn-in inspection can be performed at the wafer level.

13 to 15 show an example of the arrangement of pads on the main surface of the chip 51. Due to the relationship with the adjacent chips 51, the area that can be evenly allocated to the pads on one side is shown by the area surrounded by the chain double-dashed line.

From the case where the pads are arranged in one row in the center of the main surface of the chip 51 (see FIG. 13) to the case where the pads are arranged along the two opposite sides of the outer periphery of the chip 51 (see FIG. 14), As the pads are arranged along the four sides of the outer circumference of 51 (see FIG. 15), the area that can be uniformly allocated to the pads on one side becomes narrower. Further, as shown in FIG. 16, when the scribe region (the region indicated by X) between the adjacent chips 51 becomes narrower, the beam 18 around the probe 17 is adjusted accordingly (see FIGS. 4 to 6).
Will be difficult to form. Especially tip 5
When the pads are arranged along the four sides of the outer circumference of 1, it is difficult to form the probes 17 and the beams 18 corresponding to the pads arranged at the corners of the chip 51. Further, as the area that can be uniformly allocated to the pads on one side becomes narrower, the wiring patterns 21, 21A, 2 formed on the silicon contactor 11 (see FIG. 3) are reduced.
The area where the wirings 3, 23A can be routed and the area where the wiring formed on the wiring substrate 7 (see FIG. 2) can be routed are also narrowed. As a result, those wiring patterns 2
It becomes difficult to arrange the wirings formed on the wiring boards 7, 21A, 23, 23A.

Therefore, in the first embodiment, when the pads are arranged along the four sides of the outer periphery of the chip 51, the inspection pads 58 are arranged in one row or in the main surface of the chip 51. They are arranged in two rows. 13 to 15, the inspection pad 5 is used.
No. 8 is shown with hatching. As a result, the region where the probe 17 and the beam 18 corresponding to each inspection pad 58 can be formed is widened, so that the probe 17 and the beam 18 can be formed with a margin.
In addition, in the first embodiment, as described above with reference to FIGS. 9 to 12, every one chip or every two chips 51 to be inspected by the contact of the semiconductor inspection device is selected. If the probe 17 and the beam 18 are formed in accordance with the selected arrangement of the chip 51, the region where the probe 17 and the beam 18 corresponding to each inspection pad 58 can be formed can be further expanded. As a result, it becomes possible to form the probe 17 and the beam 18 with a further margin. In addition, each inspection pad 58
By expanding the region where the probe 17 and the beam 18 corresponding to the wiring can be formed, the wiring patterns 21, 21A, 2
It is possible to arrange the wirings formed on the wiring boards 3 and 23A and the wiring board 7 with a margin. As a result, the wiring patterns 21, 21A, 23, 23A and the wirings formed on the wiring board 7 can be easily designed with equal-length wiring patterns in consideration of electrical characteristics.

Further, as described above, when the pads are arranged along the four sides of the outer periphery of the chip 51, the inspection pads 58 are arranged in one or two rows in the main surface of the chip 51. By arranging in this manner, the flexibility of the chip 51 layout design and the pad layout design can be improved. As a result, the design efficiency for inspection including the DFT design can be improved, and the TAT and the cost required for the design and development of the semiconductor integrated circuit device according to the first embodiment can be reduced.

Next, referring to FIG. 17, an example of the wafer level burn-in inspection process using the semiconductor inspection apparatus of the first embodiment will be described.

As described above with reference to FIGS. 9 to 12, in the first embodiment, the wafer level burn-in inspection is performed by the contact between the semiconductor inspection device and the wafer 4 to be inspected 4 (see FIG. 2) 2 to 4 times. Is to do. In the first embodiment, a wafer cassette (see FIG. 2) is prepared for the number of contacts corresponding to the two to four contacts, and the semiconductor inspection device and the wafer 4 to be inspected All the chips 51 in the wafer 4 to be inspected (see FIGS.
2)).

First, the wafer to be inspected 4 (see FIG. 2) is stored in the wafer cassette (see FIG. 2) (step ST).
1). Then, step SS3 described above with reference to FIG.
A burn-in inspection of SF3 is performed (step ST2). Next, the inspected wafer 4 is taken out from the wafer cassette (step ST3), and the taken out inspected wafer 4 is stored in another wafer cassette (step ST1). By repeating such steps ST1, ST2, and ST3 for the prepared wafer cassette, it is possible to obtain the inspection result for all the chips 51 formed on the wafer 4 to be inspected. Next, a wafer map can be formed by synthesizing the obtained inspection results of all the chips 51 using, for example, a computer (step ST4).

In the first embodiment, the case in which all the chips 51 formed on the wafer 4 to be inspected are covered by using the wafer cassette for the number of contacts has been exemplified, but only one wafer cassette is prepared. ,
All the chips 51 formed on the inspected wafer 4 may be covered by moving the arrangement position of the inspected wafer 4 in the wafer cassette by the number of contacts. In this case, the wafer to be inspected 4 can be placed at a predetermined position by controlling the operation of the alignment device that determines the placement position of the wafer to be inspected 4 in the wafer cassette by software.

The semiconductor inspection apparatus according to the first embodiment as described above may be used for the threshold voltage measurement of MIS shown in steps SS2 and SF2 in FIG. 1 and the evaluation of TEG for chip diagnosis. . At this time, it is not necessary to inspect all the chips 51 in the main surface of the inspected wafer 4, and the defect distribution in the main surface of the inspected wafer 4 can be grasped by inspecting the selected specific chip 51. However, in the case where the pretreatment process shown in steps SS1 and SF1 (see FIG. 1) is to be evaluated,
It is possible to perform the measurement with one contact between the semiconductor inspection device and the wafer 4 to be inspected.

By the way, in the system LSI, it is required to quickly supply a small amount of a wide variety of custom products in accordance with the customer's request, and the product cycle has become shorter. Therefore, the development TAT (Turn Around Time) can be shortened. There is a strong demand. In such a case, a predetermined chip may be used as a process diagnostic TEG chip without disposing the TEG in the scribe region between the adjacent chips. In such a case, the process diagnostic TEG chips and the product chips are regularly arranged. For example, in FIG.
If the chip 51 indicated by hatching is the product chip and the other chips are the process diagnosis TEGs, the probe 17 (see FIGS. 4 to 6) and the semiconductor inspection apparatus contact only the product chip and Since the beam 18 (see FIGS. 4 to 6) is formed, the region where the probe 17 and the beam 18 can be formed is widened, and the probe 17 and the beam 18 can be formed with a margin. Further, since the semiconductor inspection device comes into contact with only the product chip, the number of contacts between the semiconductor inspection device and the wafer 4 to be inspected can be reduced. For example,
In the case of the array of product chips illustrated with reference to FIG. 9, the number of contacts between the semiconductor inspection device and the wafer 4 to be inspected is 1
Can be times.

(Second Embodiment) Next, a semiconductor inspection apparatus according to the second embodiment will be described with reference to FIGS. Since the wafer level inspection described in the first embodiment with reference to FIGS. 8 to 17 is the same in the second embodiment, the description thereof will be omitted.

The semiconductor inspection apparatus according to the second embodiment is a semiconductor inspection apparatus which performs a wafer level inspection by a vacuum pressurization method. As shown in FIG. 18, in the semiconductor inspection apparatus according to the second embodiment, the wafer 4 to be inspected is in the wafer tray (first
(Holding mechanism) 6A, and is sandwiched between the wafer tray 6A and the probe-attached thin film sheet (first substrate) 1A. The probe-attached thin film sheet 1A is fixed between the wafer tray 6A and the wiring substrate 7A by a thin film fixing ring 2A made of, for example, ceramic. Thin film sheet with probe 1A and wiring board (first wiring board) 7A
Between the thin film sheet 1A with the probe and the wiring board 7
An anisotropic conductive rubber sheet 61 that electrically connects A is sandwiched. The wafer 4 to be inspected is evacuated from the micro coupler 62A and the suction groove 63A by vacuuming the wafer tray 6A.
Is adsorbed on. Further, by sucking the wiring substrate 7A on the wafer tray 6A by drawing a vacuum from the micro coupler 62B and the suction hole 63B, the wafer to be inspected 4, the thin film fixing ring 2 by the wafer tray 6A and the wiring substrate 7A.
A, the thin film sheet with probe 1A and the anisotropic conductive rubber sheet 61 are packed. In this vacuum pressurization method,
A vacuum seal packing 64 is interposed between the wafer tray 6A and the wiring board 7A.

As shown in FIG. 19, the thin film sheet 1A with a probe has, for example, a base material 71 having two layers of a polyimide thin film and a Cu thin film, and a metal such as Ni in a large number of openings provided in the base material. It is formed of a multi-bump electrode (contact mechanism) 72 formed by embedding a material. The large number of bump electrodes 72 correspond to the inspection pads 58 (see FIGS. 13 to 16) provided on the main surfaces of the plurality of chips 51 (see FIGS. 9 to 12) formed on the wafer 4 to be inspected. It is located in the position

The anisotropic conductive rubber sheet 61 is composed of a rubber sheet 61A made of silicon and conductive particles (first layer) arranged at a specific position in the rubber sheet 61A made of silicon.
Wiring) 61B, and the conductive particles are connected in a chain shape in the conduction direction (the thickness direction of the rubber sheet 61A) at that location. By interposing the elastic rubber sheet 61A between the wiring substrate 7A and the bump electrode 72, contact between the bump electrode 72 and the inspection pad 58 without being affected by the warp of the wafer 4 to be inspected or the like. Can be realized.

The wiring board 7A has wirings 76 formed on a substrate 75 made of glass or polyimide, and many wirings corresponding to a plurality of chips formed on the wafer 4 to be inspected are arranged. . Also, the wiring board 7A
Is connected to, for example, a burn-in device (not shown). The wiring 76 formed in a different layer is the interlayer insulating film 77.
Are separated by. In the second embodiment, the case where the wirings 76 of a plurality of layers are formed is illustrated, but the wirings 76 may be formed of one layer. The bump electrode 72 is electrically connected to the wiring 76 via the conductive particles 61B arranged in the rubber sheet 61A, thereby realizing electrical connection with the burn-in device.

When performing the wafer level inspection using the vacuum pressure type semiconductor inspection apparatus of the second embodiment as described above, first, the inspected wafer 4 is sucked to a predetermined position on the wafer tray 6A. Then, the wafer tray 6A is attracted to the wiring board 7A with the thin film sheet with probe 1A and the anisotropic conductive rubber sheet 61 fixed by the thin film fixing ring 2A sandwiched between the wafer tray 6A and the wiring board 7A. , Inspected wafer 4, thin film sheet with probe 1A and anisotropic conductive rubber sheet 6
Pack 1 In this state, the probe-attached thin film sheet 1A is pressed by the atmospheric pressure so that each bump electrode 72 is brought into uniform contact with each inspection pad 58 of each chip 51 of the wafer 4 to be inspected at a predetermined pressure, and the test control signal By acquiring the test result signal with respect to the supply, it is possible to screen chips that may be defective in the future.

In the semiconductor inspection apparatus according to the second embodiment, the probe-attached thin film sheet 1A is placed under the atmospheric pressure (1 kgf /
Since the pressure is applied by cm ² ), assuming that the load on the bump electrode 72 required for making electrical connection between the bump electrode 72, the probe and the inspection pad 58 is 10 gf per piece, 100 pieces per cm ² If it exceeds, that is, if the inspected wafer 4 having 100 or more inspection pads 58 per cm ² cannot be measured, a problem occurs. Therefore, the second embodiment
Also in the first embodiment, as described above with reference to FIG. 8, each chip 51 has the wafer-level burn-in BIST circuit 53 built therein to reduce the number of inspection pads 58 required for the inspection. . Then, for example, as shown in FIG. 12 in the first embodiment, a chip 51 to be inspected by the contact per contact of the semiconductor inspection apparatus of the second embodiment is selected in the wafer 4 to be inspected, and a plurality of chips are selected. All chips 51 are inspected by one contact. Thereby, it is possible to prevent a problem that the load on the bump electrode 72 necessary for making the electrical connection between the bump electrode 72 and the inspection pad 58 is insufficient. As a result, even if the number of the inspection pads 58 increases in the main surface of the wafer 4 to be inspected, the burn-in inspection can be performed at the wafer level.

When the wiring 76 (see FIG. 19) included in the wiring board 7A (see FIG. 19) is formed in one layer, the wiring 76 is laid out as the inspection pads 58 become narrower in pitch. There is a concern that it will become difficult. However, as shown in FIG. 12, the chips 51 to be inspected by each contact of the semiconductor inspecting device of the second embodiment are selected at a predetermined interval, so that the substrate 75 ( (See FIG. 19)
The area where the wiring 76 can be routed is expanded by the area corresponding to the unselected chip 51. As a result, it is possible to prevent the problem that it becomes difficult to route the wiring 76 even when the inspection pads 58 have a narrow pitch.

Here, FIG. 20 is a plan view of essential parts showing the contents examined by the present inventors regarding the probe-attached thin film sheet 1A. According to a study made by the present inventors, when the diameter R ₁ of the bump electrode 72 is about 50 μm, the distance between the adjacent bump electrodes 72 is required in order to route the wiring 76 (see FIG. 19) corresponding thereto. X ₁ and Y ₁ are about 100μ
It turns out that m or more is necessary. At this time, when the distance between the adjacent inspection pads 58 is less than about 100 μm,
The width of the scribe area (area indicated by X in FIG. 16) between the adjacent chips 51 becomes small, and the adjacent chips 5
If the distance between the inspection pads 58 is less than about 100 μm, it becomes difficult to route the wiring 76. Therefore, the bump electrode 72 is provided at a predetermined position on the base material 71.
There is a concern that it will be difficult to place the. Therefore, in the second embodiment, first, by the DFT design described with reference to FIG. 8 in the first embodiment,
The number of inspection pads 58 required for inspection is reduced, and the inspection pads 58 are arranged so as not to be adjacent to each other. Next, as shown in FIG. 12, chips 51 to be inspected by one contact of the semiconductor inspection apparatus of the second embodiment are selected so as not to be adjacent to each other. As a result, a region where the wiring 76 can be routed is widened on the substrate 75, so that it is possible to prevent a problem that it is difficult to dispose the bump electrode 72 at a predetermined position of the base material 71. Become.

Also in the second embodiment as described above,
It is possible to obtain the same effect as that of the first embodiment.

(Third Embodiment) Next, a semiconductor inspection apparatus according to the third embodiment will be described with reference to FIGS. Since the wafer level inspection described in the first embodiment with reference to FIGS. 8 to 17 is the same in the third embodiment, the description thereof will be omitted.

As shown in FIGS. 21 to 24, in the third embodiment, the wafer to be inspected 4 is inspected by a semiconductor inspection apparatus in which a cantilever-shaped probe needle (contact mechanism) 81 is formed on a substrate made of, for example, ceramic. (See Figure 2)
The contact is made with the inspection pad 58 on the chip 51 formed on. Although illustration is omitted, regarding the configuration, for example, in the configuration shown in FIG. 2 in the first embodiment, the silicon contactor block 1 and the guide frame 2 are replaced with a substrate on which the cantilever-shaped probe needle 81 is formed. It can be 22 is a sectional view taken along the line BB in FIG. 21, and FIG. 24 is a sectional view taken along the line CC or DD in FIG. Although not shown, each probe needle 81 corresponds to the wiring board 7 shown in the first embodiment.
(See FIG. 2) or the same wiring board as the wiring board 7A shown in the second embodiment is electrically connected.

In the third embodiment, when the pads (inspection pads 58) are arranged along the two opposite sides of the outer periphery of the chip 51 (see FIGS. 21 and 22), for example, the above-described embodiment is used. In form 1, as shown in FIG. 11, chip 5 to be inspected by one contact
1 is selected every two columns within the main surface of the wafer 4 to be inspected.
Here, a chip 51 formed on one inspected wafer 4
Since the region where the probe needle 81 can be formed in the semiconductor inspection device of the third embodiment becomes narrower as the number of the probe needles 81 increases, the formation of the probe needle 81 in the semiconductor inspection device of the third embodiment (hereinafter , Needle stapling) will be difficult. However, as described above, by selecting the chips 51 to be inspected by one contact in the left-right direction in FIG. 11 so as not to be adjacent to each other, the probe needle 81 for the semiconductor inspection device of the third embodiment is provided. It is possible to increase the area where the needle can stand. As a result, it becomes possible to easily stand the probe needle 81 on the semiconductor inspection apparatus according to the third embodiment.

Further, when the pads (inspection pads 58) are arranged along the four sides of the outer periphery of the chip 51 (FIG. 2).
3 and FIG. 24), for example, the first embodiment.
In FIG. 10, the chips 51 to be inspected by one contact are selected so as to have a so-called checkered pattern. Even when the pads are arranged along the four outer sides of the chip 51, the number of chips 51 formed on one inspected wafer 4 as in the case described with reference to FIGS. 21 and 22. As
Since the area where the probe needle 81 can be raised to the semiconductor inspection device of the third embodiment is narrowed, it is expected that it will be difficult to raise the probe needle 81 to the semiconductor inspection device of the third embodiment. To be done. However, as described above, by selecting the chips 51 to be inspected by one contact so as not to be adjacent to each other, even when the pads are arranged along the four sides of the outer periphery of the chip 51, the present embodiment is performed. It is possible to increase the area where the probe needle 81 of the semiconductor inspection device of the third aspect can be raised. As a result, even when the pads are arranged along the four sides of the outer circumference of the chip 51, it is possible to easily set the probe needle 81 to the semiconductor inspection apparatus according to the third embodiment.

Also in the third embodiment as described above,
It is possible to obtain the same effects as those of the first and second embodiments.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first embodiment,
Although the case of using a plurality of divided silicon contactor blocks has been illustrated, a silicon contactor is formed by forming a number of probes corresponding to the inspection pads on a silicon wafer having a size equal to or larger than the wafer to be inspected. A single silicon contactor may cover the entire surface of the wafer to be inspected.

In the above description, SRA, which is the field of application behind the invention made mainly by the present inventor, is the background.
The case where it is applied during the manufacturing process of the MCP in which the M and the flash memory are mounted together has been described, but the present invention is not limited to this, and for example, a DRAM (Dynamic Ra
The present invention can also be applied during the manufacturing process of memory LSIs and logic LSIs having an ndom access memory).

[0107]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) In a wafer to be inspected (semiconductor wafer), a chip (chip area) to be inspected by one contact of a semiconductor inspection device is selected, and all chips are inspected by a plurality of contacts. Even if the number of chips formed on the wafer to be inspected increases and the number of inspection pads (terminals) formed on the chips exceeds the number of probes, the wafer-level inspection can be performed. . (2) Wafer level inspection B for each chip (chip area)
By incorporating the IST circuit, the number of inspection pads (terminals) required for inspection is reduced. Further, in the wafer to be inspected (semiconductor wafer), a chip to be inspected by one contact of the semiconductor inspecting apparatus is selected, and all chips are inspected by a plurality of contacts. As a result, it is possible to prevent a problem in which the pin load on the probe necessary for making electrical connection between the probe and the inspection pad is insufficient, so that the number of inspection pads in the main surface of the wafer to be inspected is reduced. Even if the number increases, the wafer level inspection can be performed. (3) Every other chip (chip area) inspected by one contact of the semiconductor inspection device or 2
An area where the probe corresponding to each inspection pad (terminal) and the beam supporting the probe can be formed because the probes and the beam supporting the probe are formed according to the arrangement of the selected chips. Can be extended.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a perspective view of a main part of a semiconductor inspection device according to an embodiment of the present invention.

3 is a perspective view of a main part of the semiconductor inspection device shown in FIG.

FIG. 4 is a plan view of a main part of a silicon contactor included in the semiconductor inspection device shown in FIG.

5 is a cross-sectional view of essential parts of a silicon contactor included in the semiconductor inspection device shown in FIG.

6 is a cross-sectional view of essential parts of a silicon contactor included in the semiconductor inspection device shown in FIG.

7 is a cross-sectional view of essential parts of the semiconductor inspection device shown in FIG.

FIG. 8 is a schematic block diagram showing each chip in the wafer to be inspected, which is inspected by the semiconductor inspection apparatus according to the embodiment of the present invention.

FIG. 9 is a plan view showing an arrangement in the wafer to be inspected of chips inspected by one contact of the semiconductor inspection device according to the embodiment of the present invention.

FIG. 10 is a plan view showing an arrangement in the wafer to be inspected of chips inspected by one contact of the semiconductor inspection device according to the embodiment of the present invention.

FIG. 11 is a plan view showing an arrangement in the wafer to be inspected of chips inspected by one contact of the semiconductor inspection apparatus according to the embodiment of the present invention.

FIG. 12 is a plan view showing an arrangement of chips to be inspected by a single contact of the semiconductor inspection apparatus according to the embodiment of the present invention in a wafer to be inspected.

FIG. 13 is a plan view of essential parts showing the arrangement of pads on the main surface of the chip inspected by the semiconductor inspection device according to the embodiment of the present invention.

FIG. 14 is a main-portion plan view showing the arrangement of pads on the main surface of the chip inspected by the semiconductor inspection apparatus according to the embodiment of the present invention;

FIG. 15 is a plan view of relevant parts showing an arrangement of pads on a main surface of a chip inspected by the semiconductor inspection apparatus according to the embodiment of the present invention.

FIG. 16 is a plan view of relevant parts for explaining a chip interval inspected by the semiconductor inspection device according to the embodiment of the present invention.

FIG. 17 is an explanatory diagram showing a work flow of an inspection process using the semiconductor inspection device according to the embodiment of the present invention.

FIG. 18 is a perspective view of essential parts of a semiconductor inspection device according to another embodiment of the present invention.

FIG. 19 is a cross-sectional view of essential parts of a semiconductor inspection device according to another embodiment of the present invention.

FIG. 20 is a plan view of a principal portion of a semiconductor inspection device according to another embodiment of the present invention.

FIG. 21 is a main-portion plan view illustrating an inspection step using the semiconductor inspection apparatus according to another embodiment of the present invention.

FIG. 22 is a cross-sectional view of essential parts for explaining an inspection process using a semiconductor inspection device which is another embodiment of the present invention.

FIG. 23 is a main-portion plan view illustrating an inspection step using a semiconductor inspection apparatus according to another embodiment of the present invention.

FIG. 24 is a main-portion cross-sectional view illustrating an inspection step using a semiconductor inspection device which is another embodiment of the present invention.

[Explanation of symbols]

1 Silicon contactor block (first substrate) 1A Thin film sheet with probe (first substrate) 2 guide frames 3 Elastomer 4 Inspected wafer 5 Top lid (first holding mechanism) 6 Lower lid (first holding mechanism) 6A wafer tray (first holding mechanism) 7 Wiring board (first wiring board) 7A wiring board (first wiring board) 11 Silicon contactor (contact mechanism) 12 Ceramic substrate 13 ACF 14 connector 15 cover 17 probes 18 beams 21, 21A wiring pattern (first wiring) 22 through hole 23, 23A wiring pattern (first wiring) 24 pads 25 insulating film 31 Chip resistance 32 chip capacitors 33 through hole 34 screw holes 35 hanging screw 36 fixed screw 37 Vacuum holding hole 38 Vacuum holding groove 39 Micro coupler 40 surface heater 41 Temperature sensor 42 contacts 43 connector 51 chips 52 memory circuit 53 Wafer level burn-in BIST circuit 54 register circuit 55 Control circuit 56 counter circuit 57 Decoder circuit 58 Inspection pad (first terminal) 59 Judgment circuit 61 anisotropic conductive rubber sheet 61A rubber sheet 61B Conductive particles (first wiring) 62A micro coupler 62B micro coupler 63A suction groove 63B suction hole 64 vacuum sealed packing 71 Base material 72 Bump electrode (contact mechanism) 75 substrate 76 wiring 77 Interlayer insulation film 81 Probe needle (contact mechanism) SCBR area SP7, SP8 steps SS1-SS7 steps SF1 to SF7 steps ST1 to ST4 steps

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 21/822 H01L 27/04 T 27/04 (72) Inventor Namba Iritsu Kamimizumoto-cho, Kodaira-shi, Tokyo 5-20-1 Incorporated company Hitachi, Ltd. Semiconductor Group (72) Inventor Yasuhiro Motoyama 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Incorporated Hitachi Ltd. Semiconductor Group (72) Incorporated Ryuji Kono Ibaraki F-term in the Institute of Mechanical Research, Hiritsu Seisakusho Co., Ltd. (Reference) 2G003 AA08 AA10 AC01 AG03 AG04 AG07 AG08 AH00 2G011 AA16 AA21 AB06 AB08 AE03 AF07 2G132 AA08 AB03 AE03 AF02 AJ01 AL00 AL21 4M106 A27 DD03 BA14 BA14 BA14 DD13 5F038 AV06 BE07 DF05 DT08 DT10 DT15 EZ20

Claims (23)

[Claims] 1. (a) A semiconductor integrated circuit is formed in each of the plurality of chip regions, and each of the plurality of chip regions is formed with a plurality of terminals electrically connected to the semiconductor integrated circuit on a main surface. A step of preparing a formed semiconductor wafer; (b) a plurality of contact mechanisms for contacting the plurality of terminals and a first wiring electrically connected to the plurality of contact mechanisms, and the plurality of contact mechanisms The step of preparing a first substrate holding the plurality of contact mechanisms such that each tip of the plurality of contact mechanisms protrudes toward the main surface of the semiconductor wafer, (c) bringing the plurality of contact mechanisms into contact with the plurality of terminals A step of electrically inspecting the semiconductor integrated circuit, the main surface of the semiconductor wafer is divided into a plurality of first regions, and each of the plurality of chip regions is located in any one of the plurality of first regions. Placed in the (( The method of manufacturing a semiconductor integrated circuit device, wherein the step c) is performed on each of the plurality of first regions. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step (c), (c1) the first substrate is brought into contact with the plurality of contact mechanisms and the plurality of terminals. And a step of holding the semiconductor wafer by a first holding mechanism, (c2) connecting the first wiring board having an inspection circuit and the first holding mechanism to each other so that the first wiring and the first wiring board are connected to each other. The method of manufacturing a semiconductor integrated circuit device is characterized in that the electrical inspection is a burn-in inspection. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the same number of the first holding mechanisms as the number of the plurality of first regions are prepared, and each of the first holding mechanisms is the plurality of the first holding mechanisms. A method of manufacturing a semiconductor integrated circuit device, wherein the contact positions of the plurality of contact mechanisms and the plurality of terminals are aligned in a one-to-one correspondence with each of the first regions. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step (c1) is performed by the plurality of first
A semiconductor including a step of aligning a holding position of the semiconductor wafer in the first holding mechanism so that the plurality of contact mechanisms and the plurality of terminals contact each other in a desired one of the areas. Manufacturing method of integrated circuit device. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the electrical inspection is a probe inspection. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the plurality of chip regions has a BIST circuit formed on the main surface of the semiconductor wafer, and the BIST circuit is The first of the plurality of terminals
A method of manufacturing a semiconductor integrated circuit device, comprising electrically connecting to a terminal and performing the electrical inspection by contact between the contact mechanism and the first terminal. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the number of the first terminals is 6 to 20 in each of the plurality of chip regions. Manufacturing method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first terminals are opposed to each other in one row or in four sides surrounding the main surface in each main surface of the plurality of chip regions. A method of manufacturing a semiconductor integrated circuit device, comprising arranging in two rows along two sides. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the plurality of first regions selects the chip region within the main surface of the semiconductor wafer at predetermined intervals. A method of manufacturing a semiconductor integrated circuit device, comprising: 10. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the number of the plurality of first regions is 2 to 4. 11. A contact for contacting a plurality of terminals arranged on a main surface of a semiconductor wafer divided into a plurality of chip regions and electrically connected to a semiconductor integrated circuit formed in each of the plurality of chip regions. A plurality of contact mechanisms, a first wiring electrically connected to the plurality of contact mechanisms, and a plurality of the contact mechanisms such that each tip of the plurality of contact mechanisms protrudes toward the main surface of the semiconductor wafer. A first substrate for holding the semiconductor integrated circuit, and the plurality of contact mechanisms are brought into contact with the plurality of terminals to perform an electrical inspection of the semiconductor integrated circuit. It is divided into a plurality of first regions, each of the plurality of chip regions is arranged in one of the plurality of first regions, and then the plurality of first regions is arranged.
A semiconductor inspection device characterized in that it is performed for each of the regions. 12. The semiconductor inspection apparatus according to claim 11, wherein in the electrical inspection, the first substrate and the semiconductor wafer are first held in a state where the plurality of contact mechanisms and the plurality of terminals are in contact with each other. The burn-in test is performed by electrically connecting the first wiring and the first wiring board by connecting the first holding mechanism and the first wiring board that is held by a mechanism and has an inspection circuit. A semiconductor inspection device characterized by the above. 13. The semiconductor inspection apparatus according to claim 12, wherein the same number of the first holding mechanisms as the number of the plurality of first areas are prepared, and each of the first holding mechanisms includes one of the plurality of first areas. A semiconductor inspection apparatus, wherein the contact positions of the plurality of contact mechanisms and the plurality of terminals are aligned in a one-to-one correspondence with each other. 14. The semiconductor inspection apparatus according to claim 12, wherein by aligning the holding position of the semiconductor wafer in the first holding mechanism, the plurality of the plurality of first regions are provided in the desired one of the plurality of first regions. The semiconductor inspection apparatus, wherein the contact mechanism of (1) and the plurality of terminals are in contact with each other. 15. The semiconductor inspection apparatus according to claim 11, wherein the electrical inspection is a probe inspection. 16. The semiconductor inspection apparatus according to claim 11, wherein each of the plurality of chip regions has a BIST circuit formed on the main surface of the semiconductor wafer, and the BIST circuit has the plurality of terminals. The semiconductor inspection apparatus is characterized in that the electrical inspection is performed by electrically connecting to the first terminal of the two and contacting the contact mechanism with the first terminal. 17. The semiconductor inspection device according to claim 16, wherein the number of the first terminals is 6 to 20 in each of the plurality of chip regions. 18. The semiconductor inspection apparatus according to claim 16, wherein the first terminal is arranged in a row in each main surface of each of the plurality of chip regions or on two opposite sides of four sides surrounding the main surface. A semiconductor inspection device characterized by being arranged in two rows along the line. 19. The semiconductor inspection apparatus according to claim 11, wherein each of the plurality of first regions is formed by selecting the chip regions within the main surface of the semiconductor wafer at predetermined intervals. Semiconductor inspection device characterized by being 20. The semiconductor inspection apparatus according to claim 11, wherein the number of the plurality of first regions is 2 to 4. 21. The semiconductor inspection apparatus according to claim 11, wherein the contact mechanism and the first substrate are separately manufactured by processing a substrate containing silicon as a main component, and then bonded. The semiconductor inspection device is characterized in that it is integrally formed. 22. The semiconductor inspection device according to claim 11, wherein the plurality of contact mechanisms are formed of bump electrodes. 23. The semiconductor inspection device according to claim 11, wherein the plurality of contact mechanisms are formed of conductive needles.