JPH1098166A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax a step difference between a memory cell region and a peripheral circuit region even with regard to the aluminum wiring line of DRAM. SOLUTION: A capacity insulating film of a memory capacitors is made of lead zirconate titanate (PZT) and upper and lower electrodes are made of platinum for increasing a memory capacity. A memory cell is made to have a capacitor-over-bitline(COB) structure. Provided in the peripheral circuit region are a polycide wiring line layer 10, which is the same layer as a bit line 10 of a memory cell region as well as a platinum-made wiring line layer 13a which is the same layer as a storage node 13 of the memory capacitor, thereby relaxing a step difference in an aluminum wiring line 17. In the peripheral circuit region, the platinum-made wiring layer 13a is used for connection of a CMOS structure and the aluminum wiring line 17 is contacted with the platinum-made wiring line layer 13a, thereby avoiding increase in the aspect ratio of a contact hole, caused by use of the aluminum wiring line 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, for example, a DRAM having a COB (Capacitor Over Bitline) structure using a high dielectric thin film for a capacitance insulating film (capacitor dielectric film) of a memory capacitor. (Dy
The present invention is particularly suitable when applied to a (Namic Random Access Memory) and a manufacturing method thereof.

[0002]

In recent years, high-dielectric thin film capacitor insulating film of the DRAM of the memory capacitor, for example, such Pb (Zr-Ti) as PZT (US Kurebaito trade name) O ₃ (P
It has been studied to increase the memory cell capacity by using a ferroelectric thin film made of a solid solution of bZrO ₃ and PbTiO ₃ ) or a high dielectric thin film made of Ta ₂ O ₅ .

On the other hand, these high dielectric thin films are generally
Since it cannot withstand a high temperature of 600 ° C. or more, the memory cell structure of the DRAM is formed by forming a memory capacitor after a high-temperature heat treatment such as a reflow process for planarizing an interlayer insulating film.
An OB structure has been proposed.

Conventionally, a wiring used in a general DRAM includes a polycide wiring which can withstand high-temperature heat treatment usually used as a data line (bit line);
Usually, metal wiring is used as a backing wiring of a word line made of polycrystalline silicon, and these wirings are used as wirings in a peripheral circuit part simultaneously with a cell array part. Of these, the polycide wiring needs to be connected to the n-type layer through an intra-cell bit contact, so that its conductivity type is usually n-type. However, in recent years CM
In the peripheral circuit section where the OS configuration is dominant, there are few opportunities to use the n-type polycide wiring, and the latter metal wiring is the main wiring.

[0005]

As the memory cell structure of a DRAM becomes more three-dimensional, the problem of a step between a memory cell region and a peripheral circuit region becomes more serious. When the memory cell structure has the above-described COB structure, the problem of the step between the memory cell region and the peripheral circuit region is almost solved for the polycide wiring used as the bit line.
However, the metal wiring used as a backing word line in the memory cell region above the memory capacitor and used as the main wiring in the peripheral circuit region has not yet solved the problem of the step.

That is, since the metal wiring is usually formed by a sputtering method, the aspect ratio of the contact hole has an upper limit (approximately 3.0). For this reason, the metal wiring is very high in the peripheral circuit region. It could not be formed at the hierarchical position. For this reason, it is inevitable that a certain level difference occurs between the memory cell region and the peripheral circuit region with respect to the metal wiring, and the level difference may exceed the depth of focus margin in the photolithography process of the metal wiring. Therefore, the patterning of the metal wiring may be hindered in some cases.

Therefore, an object of the present invention is to provide, for example, DRA
An object of the present invention is to provide a semiconductor memory device capable of reducing a step between a memory cell region and a peripheral circuit region with respect to a metal wiring used as a backing word line of M, and a method of manufacturing the same.

[0008]

According to a semiconductor memory device of the present invention for solving the above-mentioned problems, an access transistor formed in a memory cell region on a semiconductor substrate and one diffusion layer of the access transistor are electrically connected. A connected bit line, a memory capacitor having a lower electrode electrically connected to the other diffusion layer of the access transistor, and formed above the bit line, and the memory cell region on the semiconductor substrate. In a different peripheral circuit region, a first wiring layer formed of the same material as the bit line at the same hierarchical position as the bit line in the memory cell region, and in the peripheral circuit region, A second layer formed of the same material as the lower electrode at the same hierarchical position as the lower electrode of the memory capacitor; And a line layer.

In one embodiment of the present invention, the capacitor dielectric film of the memory capacitor is made of Pb (Zr-Ti) O ₃ , and the lower electrode and the second wiring layer of the memory capacitor are made of gold, platinum and It comprises at least one selected from the group consisting of strontium titanate.

In one embodiment of the present invention, the capacitor dielectric film of the memory capacitor is made of Ta ₂ O ₅ , and the lower electrode and the second wiring layer of the memory capacitor are formed of a barrier metal layer and a multilayer It is composed of a film having at least a two-layer structure provided with a crystalline silicon layer.

In one embodiment of the present invention, the barrier metal layer is made of one selected from the group consisting of a Ti film, a TiN film, and a stacked film of a Ti film and a TiN film.

In one embodiment of the present invention, the second wiring layer includes a wiring layer connecting the first and second semiconductor elements formed in the peripheral circuit region to each other.

In one embodiment of the present invention, the first semiconductor device is a p-channel MOSFET, and the second semiconductor device is an n-channel MOSFET.

In one embodiment of the present invention, a third wiring layer formed above the memory cell capacitor in the memory cell region, and a third wiring layer in the memory cell region in the peripheral circuit region. And a fourth wiring layer formed of the same material at substantially the same hierarchical position as the third wiring layer, wherein the fourth wiring layer is located at a predetermined position and the second wiring layer Is electrically connected to

Further, according to a method of manufacturing a semiconductor memory device of the present invention, in the method of manufacturing a semiconductor memory device having a memory cell having a transistor and a capacitor, the method is performed in a memory cell region on a semiconductor substrate where the memory cell is formed. Forming a transistor structure and forming first and second semiconductor elements in a peripheral circuit region different from the memory cell region on the semiconductor substrate; and forming an entire surface of the memory cell region and the peripheral circuit region on the semiconductor substrate. Forming a first interlayer insulating film, forming a first opening serving as a bit contact in the first interlayer insulating film in the memory cell region, and including the inside of the first opening. The first
After forming a first conductive film over the entire surface of the interlayer insulating film, the first conductive film is formed into a bit line shape in the memory cell region and a predetermined wiring shape in the peripheral circuit region. Processing, forming a second interlayer insulating film on the entire surface of the memory cell region and the peripheral circuit region, and forming a storage contact on the first and second interlayer insulating films in the memory cell region. And forming the first hole in the peripheral circuit region.
Forming at least a third opening serving as a contact hole for the first and second semiconductor elements in the second interlayer insulating film; and forming the second opening including the inside of the second and third openings. After forming a second conductive film on the entire surface of the interlayer insulating film, the second conductive film is formed in the shape of a lower electrode of a capacitor in the memory cell region, and the first and second conductive films are formed in the peripheral circuit region. Processing each of the second semiconductor elements into a predetermined wiring shape including wirings for electrically connecting the second semiconductor elements to each other.

In one embodiment of the present invention, at least in the memory cell region, after processing the second conductive film into a shape of a lower electrode of a capacitor, a capacitor dielectric film is formed thereon, and further, Forming an upper electrode of the capacitor.

In one embodiment of the present invention, a film having a two-layer structure including a barrier metal layer is formed as the second conductive film.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in accordance with preferred embodiments with reference to the accompanying drawings.

First, a DRAM according to a first embodiment of the present invention will be described with reference to FIGS. In each of FIGS. 1 and 2, the left diagram shows a peripheral circuit region, and the right diagram shows a memory cell region.

First, as shown in FIG. 1A, phosphorus (P) is ion-implanted into a predetermined region of the p-type silicon semiconductor substrate 1, and a high-temperature heat treatment at 1000 ° C. is performed in an N ₂ atmosphere, for example. An n-well region 2 is formed. Next, a thermal oxide film 4 having a thickness of about 40 to 60 nm is formed on the entire surface of the silicon semiconductor substrate 1, and a polycrystalline silicon film 6 doped with phosphorus and having a thickness of about 150 to 200 nm is formed thereon by CV.
The first cap oxide film 11 is also formed thereon by the CVD method. Next, the first cap oxide film 11 and the polycrystalline silicon film 6 are patterned by photolithography and anisotropic dry etching into a shape that is left only in a region to be a field region (element isolation region). Next, after an SiO ₂ film is formed on the entire surface by the CVD method, this is anisotropically dry-etched to form a sidewall on the side wall of the pattern of the first cap oxide film 11 and the polycrystalline silicon film 6 as shown in the figure. An oxide film is formed to complete an element isolation structure. Note that the thermal oxide film 4 above the element forming region surrounded by the field region is removed by anisotropic dry etching when forming the sidewall oxide film.

Next, as shown in FIG. 1B, after a gate oxide film 7 is formed on the surface of the silicon semiconductor substrate 1 in an element formation region surrounded by the field region in which the above-described element isolation structure is formed. On top of that, in the peripheral circuit region of the left figure, it becomes a gate electrode (not shown) of the transistor,
In the memory cell region shown on the right, an n-type polycrystalline silicon film 18 serving as a word line is formed on the entire surface, and a second cap oxide film 12 is further formed thereon. Then, after patterning the second cap oxide film 12 and the polycrystalline silicon film 18 into a predetermined shape, a sidewall oxide film is formed on the side walls thereof in the same manner as in the case of the above-described element isolation structure. Before forming the sidewall oxide film, ion implantation for forming a low concentration diffusion layer of the LDD structure transistor may be performed.

Next, as shown in FIG. 1 (c), a non-doped polycrystalline silicon film is
After being formed to a thickness of about m, arsenic (As) is ion-implanted into a predetermined region of the polycrystalline silicon film, and B is implanted into another region.
F ₂ is ion-implanted. Thereafter, a heat treatment is performed to form a p-type polysilicon layer 8 and an n-type polysilicon layer 9 respectively, and the heat of impurities from the p-type polysilicon layer 8 and the n-type polysilicon layer 9 is removed. A p-type diffusion layer 23 and an n-type diffusion layer 24 are formed in the surface region of the silicon semiconductor substrate 1 by diffusion. Then, the p-type polycrystalline silicon layer 8 and the n-type polycrystalline silicon layer 9 are patterned to separate them. These p-type polycrystalline silicon layers 8
The n-type polycrystalline silicon layer 9 constitutes an extraction electrode from each diffusion layer in the silicon semiconductor substrate 1, and is used to ease a margin for aligning a mask for a contact hole to be formed later. Further, by forming each diffusion layer in silicon semiconductor substrate 1 by thermal diffusion of impurities from p-type polycrystalline silicon layer 8 and n-type polycrystalline silicon layer 9, a shallow junction of the diffusion layer is achieved. There is also an effect.

Next, as shown in FIG. 1D, a BPSG film is formed as the interlayer insulating film 16 over the entire surface by the CVD method, and is then subjected to a reflow treatment at a temperature of 850 to 900 ° C. to flatten the surface. Become Next, as shown in the figure, a bit contact is made with the interlayer insulating film 16 at a position above the n-type polycrystalline silicon layer 9 connected to one of the diffusion layers 24 of the access transistor in the memory cell region by photolithography and dry etching techniques. An opening 100 is formed, and an opening 1 is formed in the interlayer insulating film 16 at a position above a predetermined n-type polycrystalline silicon layer 9 in the peripheral circuit region.
01 is formed. Then, a polycrystalline silicon film doped with phosphorus (P) is formed on the entire surface including the insides of the openings 100 and 101 by CV.
D method, and a WSi ₂ film is further formed thereon by CVD.
These polycrystalline silicon films and WSi ₂
The film is patterned to form a bit line (data line) in the memory cell area and a polycide wiring 10 forming a predetermined wiring in the peripheral circuit area.

Next, as shown in FIG. 2A, a BPSG film is formed again on the entire surface as the interlayer insulating film 16 and its surface is flattened by a reflow process. Next, the other diffusion layer 24 of the access transistor in the memory cell region
An opening 102 serving as a storage contact is formed in the interlayer insulating film 16 at a position above the n-type polycrystalline silicon layer 9 connected to the substrate, and a predetermined p-type polycrystalline silicon layer 8 and n-type polycrystalline An opening 103 is formed in the interlayer insulating film 16 at a position above the silicon layer 9. And
After a metal film made of gold, platinum or strontium titanate is formed on the entire surface including the insides of the openings 102 and 103 by a sputtering method, in the memory cell region, this metal film is formed on the lower electrode (storage node) 13 of the memory cell capacitor.
In the peripheral circuit region, a predetermined metal wiring layer 1 is formed.
Process into the shape of 3a. In the present embodiment, metal wiring layer 13a in the peripheral circuit region is connected to p-type polycrystalline silicon layer 8 connected to one diffusion layer 23 of the p-channel MOS transistor and one diffusion layer 24 of the n-channel MOS transistor. It is used as a part of a metal wiring for connecting the n-type polycrystalline silicon layer 9 to each other, for example, an input / output wiring of a CMOS inverter.

Next, as shown in FIG. 2B, in a memory cell region, a capacitor dielectric film (capacitive insulating film) of a memory capacitor is formed by a PZT thin film while the peripheral circuit region is covered with a photoresist (not shown). ) 20, on which an upper electrode (cell plate) 22 of a memory capacitor is formed by gold, platinum or strontium titanate.
To form

Next, as shown in FIG. 2C, a BPSG film is formed again on the entire surface as the interlayer insulating film 16, but no particular flattening process is performed. Then, after forming an opening 104 for contact at a predetermined position of the interlayer insulating film 16,
In the pattern including the inside of the opening 104, an aluminum wiring 17 mainly composed of Al and serving as a main wiring in the peripheral circuit area and a backing wiring of the word line 18 in the memory cell area is formed.

Thereafter, though not shown, a DRAM is completed by forming a protective film and the like.

In the present embodiment, as shown in FIG. 2C, in the peripheral circuit area, the polycide wiring 10 corresponding to the bit line in the memory cell area and the lower electrode 13 of the memory capacitor in the memory cell area. Metal wiring layer 1
The provision of the respective 3a reduces the step between the peripheral circuit region and the memory cell region particularly with respect to the aluminum wiring 17. Moreover, in the peripheral circuit area, the aluminum wiring 17
Need only be in contact with the metal wiring layer 13a, so that it is not necessary to form a contact hole having such a high aspect ratio. As a result, the aluminum wiring 17 can be formed at a relatively high hierarchical position even in the peripheral circuit region. it can.

If it is necessary to contact the aluminum wiring 17 with the diffusion layer formed in the silicon semiconductor substrate 1 in the peripheral circuit region, for example, as shown in FIG. For example, on the n-type polycrystalline silicon layer 9 connected to the n-type diffusion layer 24, the metal pad layer 13b and the metal wiring layer 13a are formed simultaneously with the metal wiring layer 13a using the same material as the lower electrode 13 of the memory capacitor in the memory cell region.
Is formed, and an aluminum wiring 1 is formed on the metal pad layer 13b.
If 7 is brought into contact, it is no longer necessary to form a contact hole having a high aspect ratio.

The structure similar to that of the metal pad layer 13b can be applied between the word line 18 in the memory cell region and the aluminum wiring 17 as the backing wiring.

Next, a second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, FIG.
As shown in FIG. 1A, FIG. 1 of the first embodiment described above.
After the step (d), a BPSG film is formed on the entire surface as the interlayer insulating film 16 as in the case of the first embodiment.
The surface is flattened by reflow treatment. Similarly to the first embodiment, an opening 102 serving as a storage contact is formed in a memory cell region, and a predetermined p-type polysilicon layer 8 and an n-type polysilicon layer are formed in a peripheral circuit region. An opening 103 serving as a contact hole for the layer 9 is formed.

Next, in the second embodiment, Ti
After a barrier metal layer 19 made of a film, a TiN film or a laminated film thereof is formed on the entire surface including the insides of the openings 102 and 103, an n-type polycrystalline silicon film 21 is formed thereon. Then, the n-type polycrystalline silicon film 21 and the barrier metal layer 19 are formed by photolithography and dry etching.
Is processed into the shape of the lower electrode 113 of the memory cell capacitor in the memory cell region, and into the shape of the predetermined wiring layer 113a in the peripheral circuit region. In this embodiment, the wiring layer 113a is formed by providing the barrier metal layer 19 that can withstand the formation temperature of the n-type polycrystalline silicon film (at most about 550 to 600 ° C.) under the n-type polycrystalline silicon film 21. Can be brought into contact with both the p-type polysilicon layer 8 and the n-type polysilicon layer 9.

Next, as shown in FIG. 4B, in a state where the peripheral circuit region is covered with a photoresist (not shown), the capacitor dielectric film 120 of the memory capacitor is formed of a Ta ₂ O ₅ thin film in the memory cell region. Is formed, and an upper electrode 122 of a memory capacitor made of an n-type polycrystalline silicon film is formed thereon.

Thereafter, as in the case of the first embodiment described above, as shown in FIG. 4D, a BPSG film is again formed on the entire surface as the interlayer insulating film 16, and the interlayer insulating film 16 is formed.
After a contact opening 104 is formed at a predetermined position, aluminum wiring 17 is formed in a pattern including the inside of the opening 104.
To form Thereafter, a protective film (not shown) and the like are formed to complete the DRAM.

In the second embodiment, substantially the same effects as in the first embodiment can be obtained.

[0037]

According to the present invention, for example, the C
The metal wiring used as the main wiring in the peripheral circuit region of the MOS structure can also reduce the step between the memory cell region and the peripheral circuit region, and as a result, the depth of focus margin in the photolithography process of the metal wiring can be reduced. Can solve the problem. In addition, since it is possible to promote multi-layer wiring particularly in the peripheral circuit region, it is possible to reduce the chip size.

Also, the present invention provides a DRA in which the memory capacity is increased by using a high dielectric thin film such as PZT or Ta ₂ O ₅ for the capacitor dielectric film of the memory capacitor.
Particularly effective in M and the like.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a DRAM according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing a configuration of another portion of the DRAM according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a method of manufacturing a DRAM according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon semiconductor substrate 2 n-well 8 p-type polycrystalline silicon layer 9 n-type polycrystalline silicon layer 10 polycide wiring (bit line) 13, 113 capacitor lower electrode 13 a metal wiring layer 13 b metal pad 17 aluminum wiring 18 polycrystalline silicon Film (word line) 19 Barrier metal layer 20, 120 Capacitor dielectric film 21 N-type polycrystalline silicon film 22, 122 Capacitor upper electrode 23 P-type diffusion layer 24 N-type diffusion layer 100 Opening (bit contact) 102 Opening ( Storage contact) 113a Wiring layer

Claims (10)

[Claims] An access transistor formed in a memory cell region on a semiconductor substrate; a bit line electrically connected to one of the diffusion layers of the access transistor; and an electrical connection to the other diffusion layer of the access transistor. A memory capacitor formed in a layer above the bit line and having a lower electrode connected to the same as the bit line in the memory cell region in a peripheral circuit region different from the memory cell region on the semiconductor substrate. A first wiring layer formed of the same material as the bit line at a hierarchical position; and a lower electrode at the same hierarchical position as the lower electrode of the memory capacitor in the memory cell region in the peripheral circuit region. And a second wiring layer formed of the above material. 2. The capacitor dielectric film of the memory capacitor is made of Pb (Zr—Ti) O ₃ , and the lower electrode and the second wiring layer of the memory capacitor are made of gold,
2. The semiconductor memory device according to claim 1, comprising at least one selected from the group consisting of platinum and strontium titanate. 3. The capacitor dielectric film of the memory capacitor is made of Ta ₂ O ₅ , and the lower electrode and the second wiring layer of the memory capacitor include a barrier metal layer and a polysilicon layer thereon. 2. The semiconductor memory device according to claim 1, comprising a film having at least a two-layer structure. 4. The method according to claim 1, wherein the barrier metal layer is a Ti film, TiN
4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is made of one selected from the group consisting of a film and a stacked film of a Ti film and a TiN film. 5. The semiconductor device according to claim 1, wherein the second wiring layer includes a wiring layer connecting the first and second semiconductor elements formed in the peripheral circuit region to each other. 2. The semiconductor memory device according to claim 1. 6. The semiconductor device according to claim 1, wherein the first semiconductor element is a p-channel MO.
An SFET, wherein the second semiconductor element is an n-channel M
6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is an OSFET. 7. A third wiring layer formed above the memory cell capacitor in the memory cell region, and substantially the same as the third wiring layer in the memory cell region in the peripheral circuit region. And a fourth wiring layer formed of the same material as the third wiring layer, and the fourth wiring layer is electrically connected to the second wiring layer at a predetermined position. The semiconductor memory device according to claim 1, wherein: 8. A method for manufacturing a semiconductor memory device having a memory cell having a transistor and a capacitor, comprising: forming a transistor structure in a memory cell region on a semiconductor substrate where the memory cell is formed; Forming first and second semiconductor elements respectively in a peripheral circuit region different from the memory cell region; and forming a first semiconductor device on the entire surface of the memory cell region and the peripheral circuit region.
Forming a first opening serving as a bit contact in the first interlayer insulating film in the memory cell region; and forming the first opening including the inside of the first opening. After forming a first conductive film on the entire surface of one interlayer insulating film, the first conductive film is formed into a bit line shape in the memory cell region.
Processing each of the peripheral circuit region into a predetermined wiring shape;
Forming a second opening serving as a storage contact in the first and second interlayer insulating films in the memory cell region, and forming the first and second holes in the peripheral circuit region. Forming at least a third opening serving as a contact hole for the first and second semiconductor elements in the second interlayer insulating film; and forming the second interlayer including the inside of the second and third openings. After forming a second conductive film on the entire surface of the insulating film, the second conductive film is formed in the shape of a lower electrode of a capacitor in the memory cell region, and the first and second conductive films are formed in the peripheral circuit region. Processing each of the semiconductor elements into a predetermined wiring shape including wirings for electrically connecting the semiconductor elements to each other. 9. At least in the memory cell region, after processing the second conductive film into a shape of a lower electrode of a capacitor, a capacitor dielectric film is formed thereon, and an upper electrode of the capacitor is further formed thereon. 9. The method according to claim 8, further comprising the step of: 10. The method of manufacturing a semiconductor memory device according to claim 8, wherein a film having a two-layer structure including a barrier metal layer is formed as the second conductive film.