JP3752795B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor memory device that is fine and has a large storage capacity.Manufacturing methodAbout. Dynamic random access memory (DRAM), especially suitable for high integrationManufacturing methodAbout.
[0002]
[Prior art]
The demand for dynamic random access memory (DRAM), which has improved integration at a pace of 4 times in 3 years, has been driven by the explosive sales of personal computers in recent years. Increasingly increasing. The 16-megabit mass production system is already in place, and currently development for mass production of 64-megabit using 0.35 μm, which is the next-generation fine processing technology, is in progress.
[0003]
In order to realize miniaturization of memory cells, the capacitor structure has been three-dimensional in order to secure a large capacitance value with a small area after the 4M generation. However, since the amount of accumulated charge required hardly changes even when the generation progresses, the height of the capacitor becomes higher and higher with the generation. As a result, particularly in the case of a COB cell (COB: Capacitor Over Bit-line) in which a capacitor is formed on the upper portion of the data line, a high step is generated between the memory cell portion and the peripheral circuit portion.
[0004]
Specifically, for example, in the case of 1 gigabit DRAM, which is a next generation DRAM, assuming that a tantalum oxide (silicon oxide film equivalent 3.3 nm) is used as a capacitor insulating film and a crown type capacitor is adopted, The height is about 1 micron. If such a level difference exists in the memory cell array portion and the peripheral circuit portion, photolithography and dry etching become extremely difficult in the subsequent metal wiring formation process. Regarding photolithography, since the resolution and the depth of focus are inversely proportional, when the fine pattern is formed with an increased resolution, the depth of focus becomes shallower. Therefore, if there is a high level difference, a resolution failure will occur. Of course, dry etching is a high step process, which causes problems such as etching residue and dimensional shift.
[0005]
As a means for solving such a problem, as shown in FIG. 2, a method has been proposed in which a step is provided on a Si substrate in advance and the substrate surface of the memory cell array portion is lowered to reduce the step (particularly). (Kaisho 63-266866). However, this technology is difficult to apply to 1 Giga DRAM with a minimum feature size of 0.15 microns. The reason is described below.
[0006]
In the technique disclosed in Japanese Patent Laid-Open No. 63-266866, first, a step is formed on the semiconductor substrate (wafer) as the starting material, so that the surface height of the element isolation region is also set to the memory array part and the peripheral circuit part. It will be different. Conventionally, a technology for selectively forming an oxide film (LOCOS: Local Oxidation of Silicon) has been generally used, and thus, such an element isolation region can be formed in a wafer having a high step. However, the element isolation dimension is 0.15 microns in the 1 Gbit DRAM. It is impossible to electrically isolate elements using LOCOS at this size, and shallow trench isolation (STI) technology is considered essential. However, STI embeds an oxide film locally by embedding a thick oxide film in a groove formed on the silicon surface and polishing the surface uniformly. Therefore, if there is a step in the substrate, the bottom of the step is filled with an oxide film, which cannot be applied to the technique disclosed in Japanese Patent Laid-Open No. 63-266866.
[0007]
[Problems to be solved by the invention]
  An object of the present invention is to provide a semiconductor memory device (specifically, DRAM) having an integration degree of 1 gigabit or more.Manufacturing methodTherefore, it is an object of the present invention to provide a technique for alleviating a high step between a memory cell array portion and a peripheral circuit portion, which is a serious problem.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
  Of the inventions disclosed in the present invention, the outline of typical ones will be briefly described as follows. That is, according to one aspect of the present invention, there is provided a memory cell array portion in which a plurality of memory cells each composed of a drive MISFET and a charge storage capacitor element are disposed on a main surface of a semiconductor substrate, and a plurality of memory cells around the memory cell array portion. Peripheral circuit section where peripheral circuits composed of MISFETs are arranged.A method for manufacturing a semiconductor device comprising:
A step of forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion; a step of forming a first interlayer insulating film covering the bit line and the first layer wiring; Forming a first plug connected to the first layer wiring in the first interlayer insulating film; removing the first interlayer insulating film on the memory cell array portion; and recessing the memory cell array portion. Forming a charge storage capacitor element on the bit line, and a second interlayer insulation so as to cover the charge storage capacitor element and the first interlayer insulating film. Forming a film; forming a second plug directly connected to the first plug on the second interlayer insulating film; and interconnecting the first layer via the first plug and the second plug. Forming the second layer wiring connected to A method of manufacturing a semiconductor memory device having a step.
[0010]
  Another aspect of the present invention provides a semiconductor substrate main surface,Manufacturing of a semiconductor device having a memory cell array portion in which a plurality of first transistors are arranged and a peripheral circuit portion in which a peripheral circuit composed of a plurality of second transistors is arranged around the memory cell array portion In the method, a bit line is formed in the memory cell array portion, a first layer wiring is formed in the peripheral circuit portion, and a first interlayer insulating film is formed to cover the bit line and the first layer wiring. Forming a first plug connected to the first layer wiring in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film; Removing the second interlayer insulating film so as to leave the second interlayer insulating film on the peripheral circuit portion and in the region where the charge storage capacitor element of the memory cell array portion is formed; and Said second on the cell array Forming a film to be the lower electrode of the charge storage capacitor element on the side wall of the interlayer insulating film; and removing the second interlayer insulating film on the memory cell array to form the lower electrode formed on the side wall Leaving the film;
Forming a capacitor insulating film covering the film to be the lower electrode; and thereafter, forming the upper electrode of the charge storage capacitor element from the memory cell array portion of the second interlayer insulating film on the peripheral circuit portion. A step of extending to the upper end, a step of forming a third interlayer insulating film so as to cover the charge storage capacitor element and the second interlayer insulating film, and a first connected directly to the first plug Forming two plugs through the laminated film of the second interlayer insulating film and the third interlayer insulating film, and connecting to the first layer wiring through the first plug and the second plug And forming a second layer wiring to be manufactured.
[0011]
  Another aspect of the present invention is:A method of manufacturing a semiconductor memory device comprising a memory cell array part and a peripheral circuit part, wherein the memory cell array part main surface and the peripheral circuit part main surface of the semiconductor substrate are respectively provided MISFETs Forming a bit line in the memory cell array section, forming a first layer wiring in the peripheral circuit section, and forming the first layer wiring on the memory cell array section in which the bit line is formed and the first layer wiring. Forming a first interlayer insulating film on the main surface of the formed peripheral circuit section; and connecting the first interlayer wiring to the first interlayer insulating film formed on the main surface of the peripheral circuit section. A step of forming a first plug; a step of forming a second interlayer insulating film on the first interlayer insulating film; and the first interlayer insulating film and the second interlayer on the peripheral circuit portion A step of removing the stacked film in a region where the charge storage capacitor element of the memory cell array portion is formed, and a film to be a lower electrode of the charge storage capacitor element on a side wall of the stack film And forming the charge storage capacitor on the film to be the lower electrode. Forming a capacitor insulating film of the element, then,
Forming an upper electrode of the charge storage capacitor element from the memory cell array portion to an upper end portion of the second interlayer insulating film on the peripheral circuit portion; and Forming a third interlayer insulating film so as to cover the interlayer insulating film;
Forming a second plug directly connected to the first plug through the laminated film of the second interlayer insulating film and the third interlayer insulating film; and the first plug and the second plug Forming a second-layer wiring connected to the first-layer wiring through the semiconductor memory device.
[0012]
  In addition, another aspect of the present invention provides a semiconductor substrate main surface,A semiconductor memory device having a memory cell array section in which a plurality of first transistors are arranged and a peripheral circuit section in which a peripheral circuit composed of a plurality of second transistors is arranged around the memory cell array section In the manufacturing method, a step of forming a bit line in the memory cell array section and a first layer wiring in the peripheral circuit section, and a first interlayer insulating film covering the bit line and the first layer wiring Forming a first plug connected to the first layer wiring in the first interlayer insulating film, and forming a cylindrical lower electrode of the charge storage capacitor element in the memory cell array portion. A step, a step of covering an upper surface of the outer side wall of the cylindrical lower electrode and an inner surface of the side wall with a capacitor insulating film, and then the upper electrode of the charge storage capacitor element is extended to the upper end portion of the first interlayer insulating film. Stretching and forming A step of forming a second interlayer insulating film so as to cover the charge storage capacitor element and the first interlayer insulating film, and a second plug directly connected to the first plug is connected to the second interlayer insulating film. A method of manufacturing a semiconductor memory device includes a step of forming a film, and a step of forming a second layer wiring connected to the first layer wiring through the first plug and the second plug.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0014]
Example 1
First, a DRAM according to an embodiment of the present invention will be described with reference to FIG. In the cross-sectional view shown in FIG. 1, the center left side is a memory array section in which a memory cell array is configured, and the center right side is a peripheral circuit section that constitutes a peripheral circuit. That is, FIG. 1 shows a partial cross-sectional view of a memory cell array device and a peripheral circuit device fabricated in a portion corresponding to the conventional semiconductor substrate shown in FIG.
[0015]
In FIG. 1, a so-called element isolation oxide film 2 is formed in a silicon (Si) semiconductor substrate (substrate) 1 for isolating a plurality of insulated gate field effect transistors (MISFETs). Has been. The inter-element isolation oxide film 2 is formed by a shallow trench element isolation (STI) technique, which will be described in detail later, and has substantially the same level difference from the surface of the semiconductor substrate. In the memory array portion, a gate oxide (SiO 2) film 3 is formed on the substrate surface, and a three-layer structure comprising polysilicon 4, titanium nitride (TiN) 5 and tungsten (W) 6 on the gate oxide film 3. Are formed, and a plurality of transfer MISFETs are formed. The gate electrode is covered with silicon nitride (SiN). Similarly, the MISFET in the peripheral circuit section is also formed with the same configuration as the transfer MISFET. A silicon oxide (SiO2) film 9 as an interlayer insulating film is formed on the entire main surface of the substrate 1 so as to cover these MISFETs. The silicon oxide film 9 has connection holes (contact holes) for making contact with semiconductor regions (source / drain) selectively provided in the substrate. That is, contact holes for bit lines and storage nodes are provided in this silicon oxide film 9. In the contact hole, titanium nitride (TiN) is embedded as a plug. On the silicon oxide film 9, a bit line 601A and an interconnect wiring 601B are formed. A silicon oxide film 901 as an interlayer insulating film is formed so as to cover the bit line 601A and the interconnect wiring 601B. Further, the silicon oxide film 901 is provided with a storage node contact hole that coincides with (may be slightly shifted from) the storage node contact hole of the silicon oxide film 9. A TiN plug 502 is formed in the contact hole for the storage node.
[0016]
The structure characterized by the present invention is composed of a charge storage capacitor element of a memory cell array portion and a wiring of a peripheral circuit portion formed on the silicon oxide film 901 described below.
[0017]
A lower electrode 12 of a charge storage capacitor element (capacitor) that contacts the TiN plug 502 is formed on the silicon oxide film 901 in the memory cell array portion. On the other hand, interlayer insulating films (first interlayer insulating films) 902 and 903 are selectively formed on the silicon oxide film 901 in the peripheral circuit portion. That is, an interlayer film that locally covers the peripheral circuit section is formed above the insulating film of the peripheral circuit section, and the memory cell array section is positioned as a recess by the local interlayer film.
[0018]
A lower electrode 12A is formed in a crown shape (cylindrical shape) on the lower electrode 12 of the memory cell array portion (recess portion), and the height of the lower electrode 12A increases the capacitance of the capacitor. The interlayer insulating film (first interlayer insulating film) 902, 903 covering the peripheral circuit has a height exceeding the surface. In other words, the upper surfaces of the interlayer films (first interlayer insulating films) 902 and 903 that locally cover the peripheral circuit section are located lower than the upper surfaces of the capacitors in the memory cell array section.
[0019]
An insulating film constituting the dielectric of the capacitor is thinly coated so as to cover the surface (inner wall surface and outer wall surface) of the lower electrode 12A. FIG. 1 does not show the insulating film. An upper electrode 14 constituting a common plate electrode is embedded and formed on the plurality of crown-type lower electrodes 12A of the memory cell array portion, and the surface of the upper electrode 14 is flattened. Further, a part of the upper electrode 14 is patterned so as to extend on an interlayer film (first interlayer insulating film) 902, 903 that locally covers. An interlayer insulating film (second interlayer insulating film) 905 is formed flat so as to cover the entire upper surface of the interlayer film (first interlayer insulating film) 902, 903 that locally covers the upper electrode 14 and the peripheral circuit portion. The interlayer insulating film (second interlayer insulating film) 905 includes a contact hole exposing a part of the upper electrode 14 and a W plug embedded in the contact holes of the interlayer films (first interlayer insulating films) 902 and 903. A contact hole exposing the top of 605 is formed with substantially the same aspect ratio. That is, the plurality of contact holes are processed at the same time. In the meantime, in the contact hole provided in the insulating film (second interlayer insulating film) 905, a plate electrode lead W plug 605A and a peripheral circuit wiring lead W plug 605 are embedded.
[0020]
On this interlayer insulating film (second interlayer insulating film) 905 having almost no step, a plurality of first wirings (titanium nitride / not connected to the plate electrode leading W plug 605A and the peripheral circuit wiring leading W plug 605) are provided. (Aluminum / titanium nitride laminate film) 5 is patterned. An interlayer insulating film (second interlayer insulating film) 906 is formed so as to cover the plurality of first wirings 5. A plate electrode lead W plug 606 is embedded in a contact hole provided in the interlayer insulating film (third interlayer insulating film) 906.
[0021]
A second wiring (titanium nitride / aluminum / titanium nitride laminated film) 1501 connected to the plate electrode lead W plug 606 is formed on the interlayer insulating film (third interlayer insulating film) 906 having almost no step. Is patterned.
[0022]
Next, an embodiment of the present invention will be described in detail by taking a DRAM having a data pair structure as an example and following the manufacturing process from FIGS.
[0023]
In this embodiment, the memory cell array unit is, for example, one transfer MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a charge storage capacitor element (capacitor) as one memory cell, and the memory cell is one semiconductor. This refers to the portion regularly arranged on the chip. The memory cell array section also includes a plurality of dummy cells and a sense amplifier. On the other hand, the peripheral circuit portion refers to a portion other than the memory cell array portion, for example, an address decoder and an input / output buffer. The same applies to other Examples 2 and 3 to be described later.
[0024]
First, a semiconductor substrate (1) is prepared, and a shallow trench isolation region (2) is formed as shown in FIG. The specific formation method isFirst, the depth to the substrate (1) 0.3 μ m ( A separation groove of about a micrometer) is formed by using a known dry etching method to remove damage caused by dry etching on the side wall and bottom of the groove. After that, well-known CVD (Chemical Vapor Deposition) Silicon oxide film using 0.4 μ m Oxide film that is deposited with a film thickness of about a portion that is not a groove is also known as CMP. (Chemical Mechanical Polishing) This was selectively polished by the method to leave only the oxide film (2) buried in the groove. Subsequently, on the surface of the substrate (1)Impurity ions are implanted to form the well and punch-through stopper regions. After forming a 5 nm gate oxide film (3), a 50 nm non-doped polysilicon (4) is deposited using a known CVD (Chemical Vapor Deposition) method. In order to form a bipolar gate, phosphorus ions are implanted into the N gate region under conditions of energy 5 keV and dose 2e15 cm-2, and boron ions are implanted into the P gate region under conditions of energy 2 keV and dose 2e15 cm-2. Of course, arsenic may be used instead of phosphorus, and BF2 may be used instead of boron. Subsequently, in order to reduce the word line resistance, 20 nm of TiN (5) and 80 nm of W (6) are sputtered. TiN (5) is for suppressing the silicidation reaction between polysilicon (4) and W (6), and WN can be used instead. Further, as a self-alignment contact, SiN (7) was deposited to a thickness of 100 nm using the CVD method, and the result shown in FIG. Subsequently, SiN / W / TiN / poly-Si is processed as shown in FIG. 5 by using a known dry etching method to form a gate electrode.
Next, to form a MOSFET diffusion layer, N-type MOSFETs have arsenic ions with an energy of 20 keV and a dose of 1e15 cm-2, while P-type MOSFETs have BF2 ions with an energy of 20 keV and a dose of 1e13 cm-2. Type in the conditions. Further, SiN (701) is deposited to a thickness of 50 nm by CVD, as shown in FIG. A 350 nm oxide film (9) is deposited using the CVD method and planarized, and 50 nm of SiN (702) is deposited as a contact hole processing mask as shown in FIG. Using resist as mask, SiN (702) with 0.15 diameter for bit line and storage nodeum (Micron meter)8 is opened and an oxide film is processed using this SiN as a mask to expose the underlying SiN (701) as shown in FIG. Since the gate electrode was completely covered with SiN, the gate electrode was not exposed during the oxide film processing. In addition, when processing the oxide film, the SiN used for the processing mask was cut by about 30 nm to the remaining 20 nm. In this way, a fine hole of 0.15um could be processed by using SiN instead of resist for oxide film processing. Subsequently, 50 nm SiN dry etching was performed to expose the surface of the diffusion layer formed on the substrate. Of course, the SiN (702) on the surface used for the mask by this etching is also removed at the same time. At this time, since an extra 100 nm of SiN was deposited on the gate of the peripheral circuit, the SiN directly above the gate was removed. For this purpose, as shown in FIG. 9, SiN dry etching is performed using a resist opened on the gate of the peripheral circuit as a mask. After removing the resist, impurity implantation for reducing the diffusion layer resistance and the contact resistance is performed. First, the P-type diffusion layer region is opened with a resist, and BF2 ions are implanted under the conditions of an energy of 20 keV and a dose of 1e15 cm-2. Subsequently, after removing the resist, the N-type diffusion layer region is opened with a resist, arsenic ions with an energy of 15 keV, a dose of 1e15 cm-2, and phosphorus ions with an energy of 25 keV for the purpose of electric field relaxation of the memory cell transistor, Type in a dose of 6e12cm-2. Next, a TiN plug is formed. After removing the resist for the impurity implantation mask, 100 nm of TiN (501) is deposited by CVD, as shown in FIG. A TiN etch back process is performed to form a TiN plug, and FIG. 11 is obtained. Subsequently, after depositing SiN (703) to a thickness of 20 nm by CVD, the bit line contact (10) of the memory cell array part and the peripheral circuit contact are opened as shown in FIG. Next, W (601) used for the bit line is sputtered by 50 nm. Further, SiN (704) is deposited to a thickness of 50 nm by CVD to obtain FIG. Similar to SiN (7) on the gate, this SiN (704) is for preventing a short circuit with the bit line in the subsequent memory contact formation. Subsequently, SiN (704) and W (601) are dry-etched using a resist as a mask to form bit lines in the memory cell array portion and interconnect wiring in the peripheral circuit portion as shown in FIG. Further, in order to prevent a short circuit, SiN (705) with a thickness of 50 nm is deposited, and an oxide film (901) is deposited with a thickness of 200 nm as an interlayer insulating film, which is flattened by an etch-back process as shown in FIG. Next, amorphous silicon (12) containing phosphorus at a concentration of 4e20 cm −3 is deposited to a thickness of 50 nm. This becomes a part of the capacitor lower electrode. Next is memory contact processing. A contact is opened in amorphous silicon (12) using the resist as a mask, and the resist is removed. Furthermore, dry etching of the oxide film and SiN is performed using amorphous silicon as a mask, as shown in FIG. At this time, since the bit line is completely covered with SiN, W is not exposed when the contact hole (1001) is formed. Subsequently, TiN (502) is deposited by CVD, as shown in FIG. A TiN plug is formed by TiN etch back, and the amorphous silicon (12) on the surface is processed so as to cover the entire memory cell array portion, thereby obtaining FIG. Next, recess formation is performed to reduce the level difference between the memory cell array portion and the peripheral circuit portion. For this purpose, an oxide film (902) is deposited to a thickness of 500 nm, and W (602) is sputtered to a thickness of 50 nm. Using the resist as a mask, W (602) is processed, and the oxide film and SiN are dry-etched using this W as a mask, as shown in FIG. Subsequently, W (603) is sputtered to 150 nm and etched back to obtain FIG. In order to prevent the reaction between W (603) and silicon deposited later, an oxide film (903) is deposited to a thickness of 50 nm, and the recess is processed by dry etching, as shown in FIG. At this time, amorphous silicon (12) serves as a stopper for oxide film etching. Next, polysilicon (1201) to be a capacitor lower electrode is deposited to 900 nm. Of course, this polysilicon is doped with phosphorus at a concentration of 4e20 cm @ -3. Next, the polysilicon is planarized. Further, as shown in FIG. 22, a resist (1101) having a thickness of 0.6 μm is applied to the bottom of the step (memory cell array portion). Again, a resist is applied to flatten the entire surface, and the resist and polysilicon are processed by an etch-back process to obtain FIG. Next is capacitor lower electrode processing. As shown in FIG. 24, the polysilicon is etched by 100 nm using the resist as a mask. Next, an oxide film (904) is deposited to a thickness of 50 nm and a sidewall film forming step is performed, resulting in FIG. Further, using this oxide film (904) as a mask, the polysilicon is dry-etched to obtain FIG. The oxide film (904) in the memory cell array portion is removed, tantalum oxide having an effective oxide thickness of 3.3 nm is deposited as a capacitor insulating film, and TiN (14) serving as the upper electrode is deposited to 100 nm. Further, TiN (14) is processed by dry etching to obtain FIG. Subsequently, an oxide film (905) is deposited as an interlayer insulating film to a thickness of 300 nm and planarized, and W (604) is sputtered to a thickness of 50 nm, resulting in FIG. 29 is obtained by processing W (604) using the resist as a mask and processing SiO2 using W as a mask. Subsequently, W (605) was deposited to 150 nm by CVD, and W was etched back by 200 nm, resulting in FIG. Finally, two layers of Al wiring were formed to obtain a desired semiconductor memory device as shown in FIG.
[0025]
Example 2
This embodiment is also a crown type DRAM in which the recess structure is provided to reduce the step between the memory cell array portion and the peripheral circuit portion. The method of forming the lower electrode is different from that of Example 1. The manufacturing process of the present embodiment is the same as the manufacturing process up to FIG. 15 described in the first embodiment. From the state of FIG. 15, 50 nm of SiN (706) is deposited by CVD, a contact is opened in SiN using a resist as a mask, an oxide film and SiN are dry-etched, and a TiN plug electrode is formed. It will be like 31. This SiN is used as an etch stopper for later capacitor processing. Subsequently, polysilicon (1202) containing phosphorus at a concentration of 4e20 cm −3 is deposited to a thickness of 100 nm, and the polysilicon and SiN are processed by dry etching to obtain FIG. Next, an oxide film (907) is deposited to 500 nm and tungsten is deposited to 50 nm. Next, tungsten is opened using the resist as a mask. After removing the resist, the oxide film and SiN are dry-etched. Further, as shown in FIG. 33, a W plug (607) is formed by an etch back process. Subsequently, an oxide film (908) having a thickness of 300 nm and SiN (707) having a thickness of 100 nm are deposited, and SiN is processed so as to cover the entire peripheral circuit, thereby obtaining FIG. Next, as shown in FIG. 35, SiN and the oxide film are dry-etched in the memory array portion to expose the underlying polysilicon (1202). Further, polysilicon (1203) having a thickness of 50 nm containing phosphorus at a high concentration is deposited by CVD, and then polysilicon (1203) is dry-etched by 150 nm to expose the underlying SiN (706) as shown in FIG. become. As a result, the upper part of the peripheral circuit part is covered with SiN (707) and the side part is covered with polysilicon (1203), and the oxide film (908) is exposed only in the memory cell array part. FIG. 37 is obtained by removing the oxide film in the memory cell array portion by wet etching. Tantalum oxide with an effective oxide thickness of 3.3 nm is deposited as a capacitor insulating film, and TiN (1401) with a thickness of 100 nm is further deposited as an upper electrode, and TiN (1401) and SiN (707) are processed by dry etching. It became like 38. Thereafter, two layers of aluminum wiring were applied in the same manner as in Example 1 to obtain a desired semiconductor memory device.
[0026]
Example 3
In this embodiment, a polysilicon film deposited on the inner wall of the oxide film trench is used as the lower electrode. The steps shown in FIG. 31 are the same as those described in the first and second embodiments.
[0027]
Now, from the state of FIG. 31, SiN (708) is processed so as to cover the memory cell array portion, and becomes as shown in FIG. Further, an oxide film (909) is deposited to 500 nm and tungsten (608) is deposited to 50 nm, tungsten is processed using a resist as a mask, and SiO2 and SiN are processed using tungsten as a mask to obtain FIG. As shown in FIG. 41, a W plug (609) is formed by an etch back process. Next, 300 nm of an oxide film (910) and 100 nm of SiN (709) are deposited, and SiN is processed so as to cover the peripheral circuit portion as shown in FIG. Next, as shown in FIG. 43, SiN and SiO 2 are processed to form a trench in the memory cell array portion. Further, polysilicon (1204) containing phosphorus at a concentration of 4e20 cm −3 is deposited to a thickness of 50 nm. The resist (1102) is buried in the trench by the etch back process, and FIG. 44 is obtained. Subsequently, the polysilicon (1204) exposed on the surface is removed by dry etching, and the resist is removed as shown in FIG. Further, tantalum oxide having an effective oxide thickness of 3.3 nm is deposited as a capacitor insulating film, TiN (1402) as an upper electrode is deposited to 100 nm, and TiN and SiN are processed by dry etching, as shown in FIG. Thereafter, similarly to Example 1, two layers of aluminum wiring were applied to obtain a desired semiconductor memory device.
[0028]
One embodiment of the planar layout of the DRAM chip in the present invention is shown in FIG. In FIG. 47, the peripheral circuit section (18) is arranged in a cross so as to surround the four memory cell array sections (16). In the peripheral circuit portion (18), an interlayer insulating film 17 (first interlayer insulating film) is formed so as to penetrate the memory cell array portion (16). Furthermore, a bonding pad BP is linearly provided on the main surface of the peripheral circuit portion (18) located at the center in the longitudinal direction of the chip (1).
[0029]
Next, another embodiment of the planar layout of the DRAM chip in the present invention is shown in FIG. The DRAM chip shown in FIG. 48 constitutes a large capacity DRAM of 1 giga or more. In FIG. 48, a plurality of memory cell array sections (16) are surrounded by a peripheral circuit section (18) on the outer periphery of the chip and peripheral circuit sections (18) in the X1, X2 and Y1, Y2 directions. In the peripheral circuit portion (18), an interlayer insulating film 17 (first interlayer insulating film) is formed so as to penetrate the memory cell array portion (16). Note that bonding pads (not shown) are linearly arranged in one row (X1 or X2) or two rows (X1 and X2) on the main surface of the peripheral circuit portion (18) located in the longitudinal direction X1, X2 direction of the chip (1). Provided. FIG. 49 shows a layer layout in the memory cell array portion in the present invention. In the present invention, a folded data line structure having excellent noise resistance is used. By making the element formation region (19) T-shaped, the data line (21) has a linear shape, and has a structure that can be easily resolved as lithography. Both the width and spacing of the data lines were 0.16 microns. The word line (20) was arranged with a width of 0.15 microns and a pitch of 0.32 microns. The storage node contact (22) and the bit line contact (23) were 0.15 micron square.
[0030]
Example 4
FIG. 50 shows a sectional view of this example. In this embodiment, the plug connection in the peripheral circuit is formed of a different material. The manufacturing process is the same as in Example 1. Since the lower plug 24 is formed before the capacitor process in the memory cell, heat resistance of about 800 ° C. is required. From this point of view, tungsten was used as the material for the lower plug 24. On the other hand, since the upper plug 2401 is formed after the capacitor process, heat resistance is not necessary. That is, a conductive material having a melting point equal to or lower than the above temperature is used. Therefore, aluminum having low resistance was used as a material. Of course, copper can be used as the upper plug 2401. Further, although aluminum is used as the connection plug 2402 between the wiring layers, since heat resistance is not required, copper or tungsten can also be used.
[0031]
Example 5
FIG. 51 shows a sectional view of this embodiment. Also in this embodiment, as a manufacturing process, first, the lower plug 24 in the peripheral circuit region, the memory cell capacitor, and then the upper plug 2401 in the peripheral circuit region are formed in this order. In this embodiment, the capacitor is formed in the trench of the oxide film deposited on the bit line. In this case, since only the inside of the cylindrical lower electrode is used, the capacitor surface area is about half that of the previous embodiments. As a result, the height of the capacitor for securing the necessary capacity is about 1.5 microns, but there is a feature not present in the previous embodiments that no step is generated between the peripheral circuit and the memory array. At this time, as shown in FIG. 51, since the capacitor upper electrode 14 exists at a position higher than the lower plug 24 in the peripheral circuit, power supply to the capacitor upper electrode 14 is taken not from the wiring 15 but from the wiring 1501. It was. Thus, as a result of the reduction in the number of contacts, there is a feature that there is a margin in the layout of the wiring 15.
[0032]
Example 6
FIG. 52 shows a cross-sectional view of this example. A feature of this embodiment is a capacitor. That is, only the inner side is used in the lower half of the cylindrical lower electrode, and both sides of the electrode are used as the opposing surface area of the capacitor in the upper half. As a result, the capacitor surface area can be increased as compared with the case of Example 5 (FIG. 51), so that the capacitor height can be reduced.
[0033]
Example 7
FIG. 53 shows a cross-sectional view when polysilicon is used as the plug material of the memory array portion. As a result, metal contamination was reduced and the leakage current in the memory array was reduced.
[0034]
Example 8
54 to 56 show an example in which unevenness is formed on the lower electrode. Each has a different method of forming a capacitor. As a result, the surface area of the capacitor increased and the height could be reduced from 2/3 to 1/2. In this embodiment, rugged polysilicon etching back is used for forming the irregularities, but it can also be formed by HSG (Hemispherical Grain).
[0035]
Example 9
FIG. 57 shows a cross-sectional view of this embodiment using a high dielectric film such as BST or PZT as the capacitor insulating film. In the case of such a film, platinum (Pt) or ruthenium oxide (RuO) is used as the lower electrode. However, since the CVD process is difficult, there is a problem that it is difficult to form a three-dimensional electrode. The present embodiment solves this problem. That is, the lower electrode 25 made of ruthenium oxide can be processed into a three-dimensional shape by using a ring-shaped oxide film hard mask as shown in FIGS. I was able to secure it. Of course, it is possible to use platinum as the lower electrode. In this embodiment, Al / TiN is used as the capacitor upper electrode 1403. Of course, ruthenium or ruthenium oxide can also be used.
[0036]
【The invention's effect】
The present invention has an effect of relaxing a high step between the memory cell array portion and the peripheral circuit portion, which becomes a serious problem as the degree of integration increases, and facilitates the subsequent wiring process. Further, since the step is relaxed after the bit line is formed, shallow trench isolation can be applied. Furthermore, since a plurality of plugs pulled up from the peripheral circuit are connected, the aspect ratio of the contact hole can be reduced and the process reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor memory device of the present invention.
FIG. 2 is a cross-sectional view of the prior art.
FIG. 3 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 4 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 5 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 6 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 7 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 8 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 9 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 10 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 11 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 12 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 13 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 14 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 15 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 16 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 17 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 18 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 19 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 20 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 21 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 22 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 23 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 24 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 25 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 26 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 27 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 28 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 29 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 30 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 31 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 32 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 33 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 34 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 35 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 36 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 37 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 38 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 39 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 40 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
41 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention; FIG.
FIG. 42 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
43 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention. FIG.
44 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention; FIG.
45 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention; FIG.
46 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention; FIG.
47 is a plan view showing a semiconductor memory device (chip layout) according to an embodiment of the present invention; FIG.
FIG. 48 is a plan view showing a semiconductor memory device (chip layout) according to another embodiment of the present invention.
FIG. 49 is a plan view showing a mask layout of the semiconductor memory device of the present invention.
FIG. 50 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the invention.
FIG. 51 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 52 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the invention.
FIG. 53 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 54 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 55 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention.
FIG. 56 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
FIG. 57 is a cross-sectional view in one manufacturing process of the semiconductor memory device of the present invention;
[Explanation of symbols]
1-semiconductor substrate 2-element isolation oxide film 3-gate oxide film 4-polysilicon 5, 501, 502 ... titanium nitride 6, 601 to 606 ... tungsten 7, 701 to 709 ... silicon nitride 8, 801, 802 ... impurity diffusion layers 9, 901 to 910 ... silicon oxide films 10, 1001 to 1003 ... contact holes 11, 1101, 1102 ... resists 12, 1201 to 1203 ... polysilicon 13 ... capacitor insulating films 14, 1401, 1402, 1403 ... capacitors Upper electrodes 15 and 1501... Titanium nitride / aluminum / titanium nitride laminated film 16... Memory cell array portion 17. Recess formation region 18. 19: Cell transistor formation region. 20: Word line. 21: Bit line. 22: Storage node contact. 23: Bit line contact. 24, 2401, 4022 ... Plug electrode 25 ... Ruthenium oxide.

Claims (16)

A memory cell array section in which a plurality of memory cells each composed of a drive MISFET and a charge storage capacitor element are arranged on the main surface of the semiconductor substrate, and a peripheral circuit composed of a plurality of MISFETs around the memory cell array section a method of manufacturing a semiconductor device which have a and arranged peripheral circuit portion,
Forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion;
Forming a first interlayer insulating film covering the bit line and the first layer wiring;
Forming a first plug connected to the first layer wiring in the first interlayer insulating film;
Removing the first interlayer insulating film on the memory cell array portion and forming a recess in the memory cell array portion;
Forming a charge storage capacitor element on the bit line in the memory cell array unit;
Forming a second interlayer insulating film so as to cover the charge storage capacitor element and the first interlayer insulating film;
Forming a second plug directly connected to the first plug in the second interlayer insulating film;
Forming a second layer wiring connected to the first layer wiring through the first plug and the second plug. 2. A method of manufacturing a semiconductor memory device, comprising: 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the upper electrode of the charge storage capacitor element is formed to extend from the memory cell array portion to an upper end portion of the first interlayer insulating film. . 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein a shallow trench isolation film is formed on a surface of the semiconductor substrate in a boundary region between the memory cell array portion and the peripheral circuit portion. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the charge storage capacitor element of the memory cell array unit is formed higher than the first interlayer insulating film. 5. . 3. The upper electrode of the charge storage capacitor element is connected to a third plug formed on the first interlayer insulating film and on the second interlayer insulating film. Manufacturing method of semiconductor memory device. 6. The method of manufacturing a semiconductor memory device according to claim 1, wherein the charge storage capacitor element has a crown structure. The first plug and the second plug are formed of different materials, and the first plug is a material having a melting point higher than that of the second plug. A manufacturing method of the semiconductor memory device according to the above. 6. The third plug is disposed on an upper portion of a shallow trench isolation film formed on the surface of the semiconductor substrate in a boundary region between the memory cell array portion and the peripheral circuit portion. Manufacturing method of the semiconductor memory device of FIG. A memory cell array section in which a plurality of first transistors are disposed on a main surface of a semiconductor substrate; and a peripheral circuit section in which a peripheral circuit composed of a plurality of second transistors is disposed around the memory cell array section; a method of manufacturing a semiconductor device which have a,
Forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion;
Forming a first interlayer insulating film covering the bit line and the first layer wiring;
Forming a first plug connected to the first layer wiring in the first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film;
Removing the second interlayer insulating film so as to leave the second interlayer insulating film on the peripheral circuit portion and in the region where the charge storage capacitor element of the memory cell array portion is formed;
Forming a film to be a lower electrode of the charge storage capacitor element on a side wall of the second interlayer insulating film on the memory cell array;
Removing the second interlayer insulating film on the memory cell array, leaving a film to be the lower electrode formed on the sidewall;
Forming a capacitive insulating film covering the lower electrode film, and then
Extending the upper electrode of the charge storage capacitor element from the memory cell array portion to the upper end portion of the second interlayer insulating film on the peripheral circuit portion; and
Forming a third interlayer insulating film so as to cover the charge storage capacitor element and the second interlayer insulating film;
Forming a second plug directly connected to the first plug through the laminated film of the second interlayer insulating film and the third interlayer insulating film;
Forming a second layer wiring connected to the first layer wiring through the first plug and the second plug. 2. A method of manufacturing a semiconductor memory device, comprising: 10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the charge storage capacitor element of the memory cell array portion is formed higher than the second interlayer insulating film. 11. The upper electrode of the charge storage capacitor element is connected to a third plug formed on the second interlayer insulating film and on the third interlayer insulating film. A manufacturing method of the semiconductor memory device according to the above. A method of manufacturing a semiconductor memory device comprising a memory cell array part and a peripheral circuit part, the step of forming MISFETs on the main surface of the memory cell array part and the peripheral circuit part of the semiconductor substrate,
Forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion;
Forming a first interlayer insulating film on the memory cell array section in which the bit lines are formed and on the main surface of the peripheral circuit section in which the first layer wiring is formed ;
Forming a first plug connected to the first layer wiring with the first interlayer insulating film formed on the peripheral circuit portion on a main surface,
Forming a second interlayer insulating film on the first interlayer insulating film;
A step of removing the stacked film in a region where the charge storage capacitor element of the memory cell array section is formed, leaving the stacked film of the first interlayer insulating film and the second interlayer insulating film on the peripheral circuit section; When,
Forming a film to be a lower electrode of the charge storage capacitor element on the side wall of the laminated film;
Forming a capacitive insulating film of the charge storage capacitive element on the film to be the lower electrode;
Extending the upper electrode of the charge storage capacitor element from the memory cell array portion to the upper end portion of the second interlayer insulating film on the peripheral circuit portion; and
Forming a third interlayer insulating film so as to cover the charge storage capacitor element and the second interlayer insulating film;
Forming a second plug directly connected to the first plug through the laminated film of the second interlayer insulating film and the third interlayer insulating film;
Forming a second layer wiring connected to the first layer wiring through the first plug and the second plug. 2. A method of manufacturing a semiconductor memory device, comprising: 13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the peripheral circuit portion has a cross-shaped planar layout. A memory cell array section in which a plurality of first transistors are disposed on a main surface of a semiconductor substrate; and a peripheral circuit section in which a peripheral circuit composed of a plurality of second transistors is disposed around the memory cell array section; A method of manufacturing a semiconductor memory device having
Forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion;
Forming a first interlayer insulating film covering the bit line and the first layer wiring;
Forming a first plug connected to the first layer wiring in the first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film;
A step of removing the stacked film in a region where the charge storage capacitor element of the memory cell array section is formed, leaving the stacked film of the first interlayer insulating film and the second interlayer insulating film on the peripheral circuit section; When,
Forming a film to be a lower electrode of the charge storage capacitor element on the side wall of the laminated film;
Forming a capacitive insulating film of the charge storage capacitive element on the inner surface of the side wall of the film to be the lower electrode;
Extending the upper electrode of the charge storage capacitor element to the upper end of the second interlayer insulating film; and
Forming a third interlayer insulating film so as to cover the charge storage capacitor element and the second interlayer insulating film;
Forming a second plug directly connected to the first plug through the laminated film of the second interlayer insulating film and the third interlayer insulating film;
Forming a second layer wiring connected to the first layer wiring through the first plug and the second plug;
Forming a fourth interlayer insulating film covering the second layer wiring and the third interlayer insulating film;
Forming a third plug connected to the upper electrode of the charge storage capacitor element over the second interlayer insulating film. A memory cell array section in which a plurality of first transistors are disposed on a main surface of a semiconductor substrate; and a peripheral circuit section in which a peripheral circuit composed of a plurality of second transistors is disposed around the memory cell array section; A method of manufacturing a semiconductor memory device having
Forming a bit line in the memory cell array portion and a first layer wiring in the peripheral circuit portion;
Forming a first interlayer insulating film covering the bit line and the first layer wiring;
Forming a first plug connected to the first layer wiring in the first interlayer insulating film;
Forming a cylindrical lower electrode of a charge storage capacitor element in the memory cell array portion; covering an upper portion of the outer side wall of the cylindrical lower electrode and an inner surface of the side wall with a capacitive insulating film;
A step of extending the upper electrode of the charge storage capacitor element to the upper end of the first interlayer insulating film;
Forming a second interlayer insulating film so as to cover the charge storage capacitor element and the first interlayer insulating film;
Forming a second plug directly connected to the first plug in the second interlayer insulating film;
Forming a second layer wiring connected to the first layer wiring through the first plug and the second plug. 2. A method of manufacturing a semiconductor memory device, comprising: The first plug and the second plug are formed of different materials, and the first plug is a material having a melting point higher than that of the second plug. A manufacturing method of the semiconductor memory device according to the above.

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