JPH1093066A - Solid-state imaging device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device which can simplify a cell structure and have a large photodiode open area ratio by reducing the number of transistors used in the cells of the imaging device. SOLUTION: A unit cell is made up of a photodiode 21, a read transistor 22, an amplifying transistor 23 and a reset transistor 24. A read transistor 26 connected to a source line 25 is connected to the amplifying transistor 23 through a signal line 27. A vertical register 27 has a read line 29 connected to a gate of the read transistor 22, a drain line 30 connected to drains of amplifying and reset transistors 23 and 24, and a reset address line 31 connected to a gate of the reset transistor 24. The signal line 27 is connected to a storage capacitor 34 through a sample/hold transistor 33. Signal charge causes a read pulse to be applied from a horizontal register 35 to the horizontal transistor 36 and then output to a signal output line 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using an amplifying MOS sensor, and more particularly to a solid-state imaging device capable of simplifying a cell configuration and obtaining high resolution and a driving method thereof. is there.

[0002]

2. Description of the Related Art In recent years, a solid-state imaging device having an amplifying function inside a pixel by modulating a potential of a signal charge accumulating section with a signal charge generated by photoelectric conversion and modulating an amplifying transistor inside the pixel by the potential. Is being developed. This device is called an amplification type solid-state imaging device, and is expected as a solid-state imaging device suitable for reducing the pixel size by increasing the number of pixels and reducing the image size.

FIG. 14 is a diagram showing a configuration of a conventional solid-state imaging device. In FIG. 14, the unit cells are a photodiode 1, a read transistor 2, an amplifying transistor 3, a reset transistor 4, and an address transistor 5.
The load transistor 7 connected to the source line 6 forms a source follower circuit with the amplification transistor 3 through the signal line 8. The amplification transistor 3 and the address transistor 5 are connected to a source / drain (S / D) unit 9.
Connected by

[0004] From the vertical register 10, the address line 1
1, a read line 12, a drain line 13 are wired, the address line 11 is connected to the gate of the address transistor, the read line 12 is connected to the gate of the read transistor 2,
The drain line 13 is connected to the drains of the address transistor 5 and the reset transistor 4. The signal line 8 is connected to a storage capacitor 16 via a sample / hold transistor (SHTr) 15 to which a sample / hold line 14 is connected. The signal charge is output to the signal output line 19 by applying a read pulse from the horizontal register 17 to the horizontal transistor 18.

FIG. 15 is a timing chart for driving such a conventional solid-state imaging device. The horizontal blanking HBLK will be described by dividing it into t ₁ to t ₁₁ . First, the selected address line 11 'is high (Hi).
Level (t ₂ ), the read line 12 ′ is set to Hi, and the reset transistor 4 and the read transistor 2 are turned on, so that the pixel column B one line before is reset, and at the same time, the pixel line B is selected at the same time. The signal of the present pixel column A is read (t ₃ ).

Thereafter, when the sample hold line 14 is turned on (t ₇ ), the signal is stored in the storage capacitor 16. Then, a read pulse is applied from the horizontal register 17 to the horizontal transistor 18 during the signal valid period, so that a signal is output to the signal output line 19.

FIG. 16 is a diagram showing a cross section of a cell portion in which the read transistor 7, the amplification transistor 3, and the address transistor 5 are formed in one cross section. Charge is injected from the source line 6, passes through the read transistor 7, the signal line 8, the amplifying transistor 3, and is further discharged to the drain line 13 through the S / D unit 9 and the address transistor 5.
Incidentally, reference numeral 20 denotes a substrate.

[0008]

FIGS. 17A and 17B are potential distribution diagrams of the cross-sectional portion of FIG. 16, and FIGS. 17A and 17B are diagrams showing a case where a cell is selected and a case where a cell is not selected, respectively. FIG.
As shown in (a), when a cell is selected, charge is injected from the source line 6, passes through the read transistor 7, the signal line 8, the amplifying transistor 3 and further S /
D section 9, drain line 1 through address transistor 5
It is discharged to 3. At this time, since a signal voltage is applied to the amplification transistor 3, an output corresponding to the voltage is output on the signal line 8.

On the other hand, as shown in FIG. 17B, when the cell is not selected, the charge is injected from the source line 6 because the address transistor 5 is turned off, and the read transistor 7 and the signal line 8 However, the signal line 8, the amplification transistor 3, and the S / D section 9 are floating. For this reason, the potential of this portion changes depending on the signal potential of another selected cell.

As described above, in the conventional cell structure, since the address transistor is used, there is a problem that a large aperture ratio of the photodiode cannot be obtained. Therefore, the present invention has been made in view of the above situation, and provides a solid-state imaging device capable of reducing the number of transistors used in a cell, simplifying the cell configuration, and increasing the aperture ratio of the photoelectric conversion unit. Aim.

[0011]

That is, the present invention provides an image pickup area in which unit cells having at least a photodiode, a reset transistor, an amplification transistor, and a signal charge readout transistor are arranged in a matrix two-dimensionally on a semiconductor substrate. Vertical selection means for selecting a readout row of the imaging region; a plurality of vertical signal lines arranged in a column direction for reading out the detection signal of the photodiode corresponding to the selected row; and a row from the vertical signal line. In a driving method of a solid-state imaging device having horizontal transistors for sequentially reading out detection signals to horizontal signal lines arranged in different directions, in order to select the unit cell, all the cells in a certain selected row are selected. Then, a reset transistor is turned on, a voltage is externally applied, and the amplification transistor is set to an operating point.

Also, the present invention provides a plurality of photoelectric conversion storage units arranged in a matrix two-dimensionally on a semiconductor substrate, and a vertical selection means for selecting a readout row of the plurality of photoelectric conversion storage units.
A plurality of vertical signal lines arranged in a column direction from which a detection signal of the selected photoelectric conversion storage unit is read, and a detection signal read from the photoelectric conversion storage unit is input to output a detection signal to the vertical signal line. A plurality of output circuits; a read-out MOS transistor for selectively reading out a detection signal from the photoelectric conversion storage section to the output circuit; and a detection signal from a plurality of vertical signal lines to a horizontal signal line arranged in a row direction. In a solid-state imaging device having horizontal selection means for sequentially reading
The read transistor is characterized in that the channel width on the photoelectric conversion storage section side is set smaller than the channel width on the output circuit side.

Further, the present invention provides a photoelectric conversion means for performing photoelectric conversion, a signal charge storage means for storing signal charges by the photoelectric conversion, a discharge means for resetting and discharging the stored signal charges, In a solid-state imaging device including an amplifying transistor modulated by electric charges and a reading means for reading a signal current from the amplifying transistor, a first wiring forming the reading means and a second wiring forming the discharging means are provided. Are characterized by being formed so as to overlap with each other.

In the method for driving a solid-state imaging device according to the present invention, selection and non-selection of a cell are performed via a reset transistor. Further, according to the present invention, the channel width of the read transistor is larger on the amplifier circuit side than on the photodiode side.
The channel potential below the gate of the read transistor becomes higher on the amplifier circuit side. Therefore, the signal charge passing through the channel of the read transistor also moves due to this potential difference, so that the read time is shorter than when the signal charge flows only by diffusion.

Further, according to the present invention, the aperture ratio of the photodiode is limited only by the width of one of the wiring for reading out the signal current and the wiring for discharging the signal charge. It is also possible to increase the aperture ratio of the photodiode. In a similar stacked image sensor, even if the device is miniaturized, a drain line and a signal line can be wired.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention.

In FIG. 1, a unit cell comprises a photodiode 21, a read transistor 22, an amplifying transistor 23, and a reset transistor 24. A read transistor 26 connected to a source line 25 is amplified through a signal line 27. A transistor 23 and a source follower circuit are configured.

From the vertical register 28, read lines 29,
A drain line 30 and a reset address line 31 are wired. A read line 29 is connected to the gate of the read transistor 22, a drain line 30 is connected to the drains of the amplification transistor 23 and the reset transistor 24, and a reset address line 31 is connected to the reset transistor 24. Connected to the gate. The signal line 27 is connected to a sample / hold transistor (S
The storage capacitor 34 is connected via an (HTr) 33. The signal charge is transferred from the horizontal register 35 to the horizontal transistor 36.
The read pulse is applied to the signal output line 3
7 is output.

Next, the operation when driving the device according to the first embodiment will be described with reference to the timing chart shown in FIG. Horizontal blanking HBLK
Dividing the inner into t ₂₁ ~t _31. First, the drain line 30 of the pixel columns A to select 'is the Hi (t _22), then the reset address line 31' is turned off (t _23). Then, the read line 29 'is in the Hi (t _24). At this time, the unselected pixel column B has the reset address line 31 set to H level.
i, and the drain line 30 is set to the low level.

Thereafter, when the sample / hold line 32 is turned on (t ₂₆ ), the signal is stored in the storage capacitor 34. Then, a read pulse is applied from the horizontal register 35 to the horizontal transistor 36 during the signal valid period, so that a signal is output to the signal output line 37.

FIG. 3 is a diagram showing a cross section of the cell portion in which the read transistor 26 and the amplification transistor 23 are formed in one cross section. The charge is injected from the source line 25, passes through the read transistor 26, the signal line 27, and the amplifying transistor 23, and is discharged to the drain line 30.

FIG. 4 is a potential distribution diagram of the cross section of FIG.
(A) and (b) are the figures shown at the time of cell selection and at the time of non-selection, respectively. As shown in FIG.
When a cell is selected, charge is injected from the source line 25 and discharged to the drain line 30 through the read transistor 26, the signal line 27, and the amplification transistor 23. At this time, since a signal voltage is applied to the amplification transistor 23, an output corresponding to the voltage is output on the signal line 27.

On the other hand, as shown in FIG. 4B, when the cell is not selected, the charge is injected from the source line 25 because the amplifying transistor 23 is off, and the read transistor 26 and the signal line 27 , But does not flow to the drain line 30 and the signal line 27 is floating. For this reason, the potential of this portion changes depending on the signal potential of another selected cell.

As described above, according to the first embodiment,
Since an address transistor is not required in the cell, a large aperture ratio can be obtained. Here, a pattern example of a basic solid-state imaging device is shown in FIG. 5, and FIG.
FIG. 6 is a circuit configuration diagram of a unit cell of the solid-state imaging device shown in FIG. 5.

In FIG. 6, the signal charge is read out from the photodiode 40 via the readout transistor 41 to the gate of the amplification transistor 42, and when the vertical selection signal Y is selected by the vertical selection signal Y, the amplified signal is amplified. Is read. The signal charge read from the photodiode 40 is discarded to the drain via the charge / discharge transistor 44 before the signal charge of the next field is read.

This will be described below with reference to the plane pattern shown in FIG. That is, a horizontal address line 45 wired in the horizontal direction from the vertical shift register is connected to the gate of the vertical selection transistor 43 and selects a line from which a signal is read. Similarly, a reset line 46 and a read line 47 that are wired from the vertical shift register in the horizontal direction are connected to the gate of the reset transistor 44 and the gate of the read transistor 41, respectively. The drain of the amplification transistor 42 is connected to a vertical signal line arranged in the vertical direction via an interlayer contact 48.

The signal charge stored in the photodiode 40 is read out to the drain when the read transistor 41 is turned on. This drain is the interlayer contact 4
9, the potential of the gate 50 changes because it is electrically connected to the gate 50 of the amplification transistor 42. When the vertical selection transistor 43 is turned on, the amplified signal is read out to the vertical signal line via the interlayer contact 48.

The signal charge modulating the gate of the amplification transistor 42 read from the photodiode 40 is discarded to the drain via the charge / discharge transistor 44 before the signal charge of the next field is read. The drain of the charge / discharge transistor 44 is common to the drain of the amplification transistor of the adjacent unit cell, and is connected to the power supply line via the interlayer contact 51.

In FIG. 5, for simplicity, only the element forming region, the gate polysilicon and the pattern of the interlayer contact are shown, but actually, the second layer polysilicon and the aluminum wiring are also present.

At this time, looking at the channel width of the read transistor 41, the channel width on the photodiode 40 side is the same as the channel width on the drain side. As described above, in the basic solid-state imaging device, regarding the MOS-type read transistor between the photodiode and the amplifier circuit,
The channel potential of the read transistor was constant in the channel direction. For this reason, the signal charges traveling in the channel move only by diffusion, and it takes time until reading is completed, which is one of the factors that hinder the increase in the number of pixels of the element. Therefore, in order to shorten the time for reading signal charges from the photodiode using the read transistor, it is conceivable to increase the channel width of the read transistor on the amplifier circuit side than on the photodiode side.

FIG. 7 is a plan view of a solid-state imaging device according to a second embodiment of the present invention. Since the configuration diagram of the unit cell of the solid-state imaging device shown in FIG. 7 is the same as that of FIG. 6, the description is omitted here.

In FIG. 7, a horizontal address line 45 wired in the horizontal direction from the vertical shift register is connected to the gate of the vertical selection transistor 43 and selects a line from which a signal is read. Similarly, a reset line 46 and a read line 47 that are wired in the horizontal direction from the vertical shift register
Each is connected to the gate of the reset transistor 44 and the gate of the read transistor 41 '. The drain of the amplification transistor 42 is connected to a vertical signal line arranged in the vertical direction via an interlayer contact 48.

The signal charge stored in the photodiode 40 is read to the drain when the read transistor 41 'is turned on. This drain is connected to the interlayer contact 49.
, The potential of the gate 50 changes because it is electrically connected to the gate 50 of the amplification transistor 42.

When the vertical selection transistor 43 is turned on, the amplified signal is read out to the vertical signal line via the interlayer contact 49. The signal charge modulating the gate 50 of the amplification transistor 42 read from the photodiode 40 is discarded to the drain via the charge / discharge transistor 44 before the signal charge of the next field is read.

The drain of the charge / discharge transistor 44 is common to the drain of the amplifying transistor 42 of the adjacent unit cell, and is connected to the power supply line via the interlayer contact 51. In FIG. 7, for simplicity, only the pattern of the element forming region, the gate polysilicon, and the interlayer contact are shown, but actually, the second layer polysilicon and the aluminum wiring are also present.

At this time, looking at the channel width of the read transistor 41 ', the channel width on the drain side is formed wider than the channel width on the photodiode 40 side.

FIGS. 8A and 8B briefly explain the effect of the second embodiment. FIG. 8A is a plan view showing a pattern of a read transistor 41 ', and FIG. FIG. 3C is a cross-sectional view taken along a line, and FIG.

In FIGS. 8A and 8B, the photodiode 40 is the source, and the first layer polysilicon is the gate electrode 53. The signal charge generated in the photodiode 40 is read out to the drain 54 when the transistor is turned on. Reference numeral 55 denotes a contact for connecting the drain of the read transistor to an upper wiring (not shown), 56 denotes a P-type substrate, 57 denotes an N-type impurity diffusion layer, 58 denotes a gate oxide film, and 59 denotes a LOCOS region.

In FIG. 8C, below the gate electrode 53, the channel width increases from I to I '(W ₁ <W ₂ ). Therefore, the channel potential decreases due to the narrow channel effect (see FIG. 8).
(In (c), it becomes the upper part.) As a result, the signal charges passing through the channel are accelerated in the drain direction due to the potential difference. Therefore, it is possible to shorten the read time as compared with the conventional example that flows only by diffusion.

As described above, according to the second embodiment,
Since the channel width of the read transistor is larger on the amplifier circuit side than on the photodiode side, the channel potential below the gate of the read transistor is higher on the amplifier circuit side as a result of the narrow channel effect. Therefore, the signal charge passing through the channel of the read transistor also moves due to the potential difference, so that the read time is shorter than when the signal charge flows only by diffusion.

By the way, in order to increase the aperture ratio of the photodiode, the signal line and the drain line may be overlapped. That is, the basic configuration of the pixel in the amplification type solid-state imaging device includes a photodiode, a reset transistor, an amplification transistor, a line selection transistor,
Alternatively, it is a capacitive coupling, and a wiring connecting the photodiode and the amplification transistor gate.

To temporarily store the photoelectrically converted signal charge, a storage diode is provided in a region different from the photodiode, and a transfer gate is provided between the photodiode and the storage diode.

Further, a signal line for reading out the signal amplified by the amplification transistor and a drain line for resetting and discharging the signal charge are provided. Normally, two signal lines and two drain lines are independently provided.

In a solid-state imaging device having a structure in which the element is miniaturized and a photoelectric conversion unit is accumulated above a transistor, a signal line, and a drain line, in order to obtain electrical conduction between the pixel electrode and the accumulation unit, The layer forming the signal line and the layer forming the drain line must form the same layer of metal cap. For this reason, when forming the signal line and the drain line, there is a restriction that the metal line should not be in electrical contact with the metal cap.

In such an amplification type solid-state imaging device, the signal line and the drain line are independently wired. However, in the case of a structure in which the wiring is independent, in miniaturizing the element, the aperture ratio of the photodiode portion is limited by the two wirings of the signal line and the drain line.

In the image pickup apparatus having a structure in which the photoelectric conversion unit is stacked on the uppermost part, there is a problem that there is no space for wiring the signal line and the drain line independently so as not to overlap. That is, when forming a fine element, it becomes impossible to wire without overlapping the signal line and the drain line.

For this reason, in the embodiment described below,
An example in which the aperture ratio of a photodiode is increased by a configuration in which a signal line and a drain line are overlapped will be described. FIG. 9 shows a third embodiment of the present invention. For one pixel of an amplifying solid-state imaging device, a wiring (signal line) for reading out an amplified signal current and a signal charge are discharged. FIG. 2 is a diagram showing an arrangement of wiring (drain lines) for the above. FIG. 10 is a diagram showing a half-surface arrangement of the wiring of the amplification type solid-state imaging device in FIG. FIG. 11 is an equivalent circuit diagram of the amplification type solid-state imaging device.

In this amplification type solid-state imaging device, ap ⁺ layer (element isolation region) 62 and a p ⁺⁺ layer (photodiode) 63 are formed on a surface layer of a p-type silicon semiconductor substrate 61. In the photodiode 63, signal charges are generated. Then, after a contact hole for electrical contact with the photodiode 63 is formed, the contact hole is formed to obtain electrical contact with the photodiode 63 and the gate of the amplification transistor 64. At this time, the amplification transistor 6
An n-layer is formed in a region where a reset transistor 4 for discharging signal charges 4 and signal charges is formed.

Then, a source and a drain are formed, and a contact hole for making electrical contact is formed. Thereafter, polysilicon is deposited to form a gate of the transistor, and processed into a desired shape to form an amplification transistor 64 and a reset transistor 65. Further, a capacitor 66 is formed of polysilicon and SiO ₂ / SiN / SiO ₂ (insulating layer) in order to store signal charges.

Thus, the element portion of the amplification type solid-state imaging device is formed. Next, after the element portion of the amplification type solid-state imaging device is formed, a signal line 67 as a wiring for reading out a signal current and a drain line 68 as a wiring for discharging a signal charge are wired. At this time, since the drain line 68 is formed, for example, aluminum (Al)
A thin film is formed by sputtering. The drain line 68 is formed into a desired shape by patterning, RIE (reactive ion etching), or the like.

Next, a silicon oxide film 69 is laminated.
This silicon oxide film 69 serves as an insulating layer
8 has a role to protect and prevent electrical contact with other parts. Then, in order to form the signal line 67, for example, an Al thin film is deposited by a sputtering method or the like. Thereafter, the resist is patterned so as to overlap the drain line 68 formed earlier, and the signal line 67 is processed by RIE.

Thus, as shown in FIG. 10, the signal line 67 is formed so as to overlap the drain line 68. Incidentally, 70 is an address line, and 71 is a reset line.

When patterning the resist,
It is also preferable that the patterning is performed so that the width of the signal line 67 is smaller than the width of the drain line 68. The reason for this is
When patterning the resist covering the signal line 67, the signal line 67 is changed to the drain line 68 due to misalignment.
This is because it is possible to eliminate the occurrence of a step due to protruding outside of the device and causing electrical conduction failure.

In this manner, as shown in FIG. 9, the wiring for reading the signal current (signal line 67) and the wiring for discharging the signal charge (drain line 68) are stacked. By arranging, the wiring width for limiting the aperture ratio of the photodiode 63 can be reduced to one line width. As a result, the aperture ratio of the photodiode 68 can be improved, and the sensitivity can be increased.

In the third embodiment, Al (aluminum) is used as the wiring material. However, other materials such as tungsten (W), molybdenum (Mo),
A metal such as titanium (Ti) or at least one such metal
Compounds such as metal alloys and silicide compounds containing more than one kind can also be used.

Next, a fourth embodiment of the present invention will be described. 12 and 13 illustrate an amplification type solid-state imaging device having a structure in which photoelectric conversion units are stacked. FIG. 12 illustrates an arrangement configuration of signal lines and drain lines for one pixel of the amplification type solid-state imaging device. FIG. 13 is a diagram showing a half-surface layout of the wiring arrangement of the amplification type solid-state imaging device of FIG.

As in the third embodiment described above, first, an element portion is formed. Note that, at this time, a part of the charge can be stored even in the portion that becomes the photoelectric conversion unit in the third embodiment.

Then, in order to carry the signal charges to the storage section 73, a hole is formed in the insulating layer 74 using RIE or the like, and a metal column (plug) 75 is formed by tungsten CVD or the like. Thereafter, an Al (aluminum) film is deposited, for example, to a thickness of 400 nm by a sputtering method or the like, and is formed into a desired shape by resist patterning, RIE, or the like. As a result, the drain line 76 and the metal cap 77 are formed at the same time.

Thereafter, a silicon oxide film 74 is deposited,
The patterning of the resist, the RIE, the deposition of the metal film, and the like are repeated again to form the signal line 79 and the metal cap 80 on the metal plug 78. At this time, since the metal cap 80 is formed in the same layer as the signal line 79, the signal line 79 is formed.
And the metal cap 80 should not be in electrical contact. Therefore, the signal line 79 and the metal cap 8
Between 0, the risk of electrical contact is maintained with an interval of 0.6 μm or more.

For this reason, as can be seen from FIG. 12, the signal line 79 cannot be wired so as not to overlap the drain line 76. That is, the signal line 79 and the drain line 76 must have an overlapping structure.

After the formation up to the signal lines, the silicon oxide film 74 is deposited again, and the processing by RIE and the deposition processing of the metal film are performed to form the metal plug 81. After that, for example, a metal such as Ti is deposited, and shape processing by RIE or the like is performed to form the pixel electrode 82.

Finally, as the photoelectric conversion layer 83, for example, an amorphous Si film is deposited, and the transparent electrode 8 made of, for example, ITO or the like is formed on the photoelectric conversion layer 83, that is, on the uppermost part.
4 are deposited.

Reference numeral 85 denotes an amplifying transistor, 86 denotes an address line, and 87 denotes a reset line. in this way,
According to the fourth embodiment, the aperture ratio is not limited because the photoelectric conversion unit is disposed above the wiring such as the signal line and the drain line.

[0064]

As described above, according to the present invention, it is possible to provide a solid-state imaging device capable of simplifying the cell configuration by reducing the number of transistors used in the cell and increasing the aperture ratio of the photoelectric conversion unit. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation when driving the device according to the first embodiment.

FIG. 3 shows a read transistor 26 and an amplification transistor 2
FIG. 3 is a diagram showing a cell section cross-sectional shape in which 3 is formed into one cross section.

FIGS. 4A and 4B are potential distribution diagrams of a cross-sectional portion of FIG. 3, wherein FIGS. 4A and 4B are diagrams showing a case where a cell is selected and a case where a cell is not selected, respectively.

FIG. 5 is a diagram illustrating a pattern example of a basic solid-state imaging device.

6 is a circuit configuration diagram of a unit cell of the solid-state imaging device shown in FIG.

FIG. 7 is a plan view of a solid-state imaging device according to a second embodiment of the present invention.

FIGS. 8A and 8B are views for briefly explaining the effect of the second embodiment, in which FIG. 8A is a plan view showing a pattern of a read transistor 41 ′, and FIG. 8B is a view along the line II in FIG. FIG. 3C is a view showing the channel potential.

FIG. 9 shows a third embodiment of the present invention, wherein a wiring (signal line) for reading out an amplified signal current and a signal charge are discharged for one pixel of an amplification type solid-state imaging device. FIG. 2 is a diagram showing an arrangement of wiring (drain lines) for the above.

FIG. 10 is a diagram showing a half-plane layout of a wiring arrangement of the amplification type solid-state imaging device in FIG. 9;

FIG. 11 is an equivalent circuit diagram of the amplification type solid-state imaging device.

FIG. 12 is a diagram showing an arrangement configuration of signal lines and drain lines for one pixel of an amplification type solid-state imaging device having a structure in which photoelectric conversion units are stacked.

13 is a diagram illustrating an amplifying solid-state imaging device having a structure in which photoelectric conversion units are stacked, and is a diagram illustrating a half-surface arrangement of wiring of the amplifying solid-state imaging device in FIG.

FIG. 14 is a diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 15 is a timing chart when driving a solid-state imaging device having a conventional structure.

FIG. 16 is a diagram showing a cross-sectional shape of a cell portion in which a read transistor 7, an amplification transistor 3, and an address transistor 5 are formed in one cross section.

17A and 17B are potential distribution diagrams of the cross-sectional portion of FIG. 16, wherein FIGS. 17A and 17B are diagrams illustrating a case where a cell is selected and a case where a cell is not selected, respectively.

[Explanation of symbols]

 21, 40 photodiode, 22 read transistor, 23, 42 amplifying transistor, 24 reset transistor, 25 source line, 26, 41, 41 'read transistor, 27 signal line, 28 vertical register, 29, 47 read line, 30 drain line , 31 reset address lines, 32 sample / hold lines, 33 sample / hold transistors, 34 storage capacitors, 35 horizontal registers, 36 horizontal transistors, 37 signal output lines, 43 vertical selection transistors, 44 charge / discharge transistors, 45 horizontal address lines, 46 reset line, 48, 49, 51 interlayer contact, 50 gate.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yoshinori Iida 1 Tokoba, Komukai Toshiba-cho, Saisaki-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Hidetoshi Nozaki Toshiba Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa No. 1 in the Toshiba R & D Center (72) Inventor Keiji Mabuchi 1 in Komukai Toshiba, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture In-Toshiba R & D Center (72) Inventor Shinji Osawa Kawasaki-shi, Kanagawa 1, Komukai Toshiba-cho, Ward Inside Toshiba R & D Center

Claims (5)

[Claims] 1. An imaging region in which unit cells having at least a photodiode, a reset transistor, an amplification transistor, and a signal charge reading transistor are arranged in a matrix two-dimensionally on a semiconductor substrate, and a readout row of the imaging region is selected. Vertical selection means, a plurality of vertical signal lines arranged in the column direction for reading out the detection signal of the photodiode corresponding to the selected row, and a horizontal signal line arranged in the row direction from the vertical signal line. In a driving method of a solid-state imaging device having a horizontal transistor for sequentially reading out detection signals, in order to select the unit cell, in all cells of a selected row only, a reset transistor is turned on and an external transistor is turned on. A method for driving a solid-state imaging device, comprising applying more voltage and setting the amplification transistor to an operating point. 2. The non-selection of the unit cell includes turning on the reset transistor, applying a voltage from outside, and turning off the amplifying transistor in all cells of a selected row only. 2. The method for driving a solid-state imaging device according to claim 1, wherein: 3. A plurality of photoelectric conversion storage units arranged in a two-dimensional matrix on a semiconductor substrate, a vertical selection unit for selecting a readout row of the plurality of photoelectric conversion storage units, and a selected photoelectric conversion storage unit A plurality of vertical signal lines arranged in a column direction for reading out the detection signal, a plurality of output circuits for receiving the detection signal read from the photoelectric conversion storage unit and outputting a detection signal to the vertical signal line, A read MOS transistor for selectively reading a detection signal from the photoelectric conversion storage unit to the output circuit; and a horizontal transistor for sequentially reading the detection signal from the plurality of vertical signal lines to a horizontal signal line arranged in a row direction. A solid-state imaging device comprising a selection means, wherein the readout transistor has a channel width set on the photoelectric conversion storage section side smaller than a channel width on the output circuit side. Image apparatus. 4. A photoelectric conversion means for performing photoelectric conversion, a signal charge accumulating means for accumulating signal charges by the photoelectric conversion,
Discharging means for resetting and discharging the accumulated signal charges;
In a solid-state imaging device including an amplification transistor modulated by the accumulated signal charge and a reading unit for reading a signal current from the amplification transistor, the first wiring and the discharging unit constituting the reading unit are provided. The solid-state imaging device according to claim 1, wherein the constituent second wirings are arranged so as to overlap with each other. 5. The solid according to claim 4, wherein the width of the first wiring and the second wiring is not larger than the width of the wiring wired in the lower part. Imaging device.