JP5440056B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  In the solid-state imaging device disclosed in Patent Literature 1 below, a pixel block is formed for each predetermined number of pixels, and the predetermined number of pixels belonging to the pixel block share one amplification transistor for each pixel block. . For this reason, the number of transistors per pixel can be reduced, and the aperture ratio can be increased. When the aperture ratio is large, a lot of charges are handled, and the SN ratio is improved.

  In the solid-state imaging device disclosed in Patent Document 1 below, each pixel block is provided with a photoelectric conversion unit and a transfer transistor for each pixel. The output part of each transfer transistor is connected to the input part of the amplification transistor for each pixel block by wiring. As a result, a fixed-value floating capacitor is formed at the input portion of the amplification transistor of each pixel block by the predetermined number of floating diffusion regions and the wiring that form the output portions of the predetermined number of transfer transistors of the pixel block. ing. The floating capacitor converts the charge transferred from the photoelectric conversion unit by the transfer transistor into a voltage, and the amplification transistor outputs a signal corresponding to the voltage.

JP 2006-73733 A

  However, in the conventional solid-state imaging device, as described above, a fixed number of floating capacitors are formed by a predetermined number of floating diffusion regions forming the output portions of a predetermined number of transfer transistors and the wirings. Even if it is attempted to reduce the capacitance value of the floating diffusion region itself, there is a limit in bringing charge transfer by the transfer transistor closer to so-called complete transfer. In addition, the wiring becomes long. Therefore, the capacitance value of this floating capacitor must be increased. On the other hand, the saturation charge amount of the floating capacitor is proportional to the capacitance value of the floating capacitor, and the charge-voltage conversion gain of the floating capacitor is inversely proportional to the capacitance value.

  For this reason, in the conventional solid-state imaging device, although the saturation charge amount of the floating capacitor is increased, the charge-voltage conversion gain of the floating capacitor is decreased. Therefore, although the conventional solid-state imaging device can increase the dynamic range at the time of low sensitivity, it is possible to increase the S / N at the time of high sensitivity as a compensation for increasing the aperture ratio. could not.

  The present invention has been made in view of such circumstances, and in spite of the fact that the aperture ratio can be increased, the expansion of the dynamic range at the time of low sensitivity and the high S / N at the time of high sensitivity are compatible. It is an object of the present invention to provide a solid-state imaging device that can be used.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes M (M is an integer of 3 or more) photoelectric conversion units, an amplification unit provided in common to the M photoelectric conversion units, and the M photoelectric units. M transfer transistors that are provided one-to-one with respect to the conversion unit and transfer charges from the M photoelectric conversion units to the amplification unit, and N transfer transistors (N is greater than M) And an N number of switches provided between the transfer transistor belonging to the group and the amplifying unit, one for each group. It is.

  In the solid-state imaging device according to the second aspect, in the first aspect, the output portion of each transfer transistor is a floating diffusion region.

  In the solid-state imaging device according to the third aspect, the number of the transfer transistors belonging to each group is the same in the first or second aspect.

  According to the present invention, it is possible to provide a solid-state imaging device capable of achieving both expansion of a dynamic range at low sensitivity and high S / N at high sensitivity, although the aperture ratio can be increased. Can do.

It is a schematic block diagram which shows the solid-state image sensor by one embodiment of this invention. FIG. 2 is a circuit diagram illustrating a pixel block in FIG. 1. FIG. 2 is a schematic plan view schematically showing a pixel block in FIG. 1. 3 is a timing chart showing each operation mode of the solid-state imaging device shown in FIG. 1.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram showing a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the pixel block 10 in FIG. The solid-state imaging device according to the present embodiment is configured as a CMOS solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device according to the present embodiment includes a plurality of pixels 1 arranged two-dimensionally, a vertical scanning circuit 2, a horizontal scanning circuit 3, a readout circuit 4, and an output amplifier 5. And a vertical signal line 7 provided for each column of the pixels 1 and supplied with the output of the pixel 1 for each column. The electrical signal photoelectrically converted by the photodiode PD of each pixel 1 is taken out by the vertical scanning circuit 2 to the readout circuit 4 via the vertical signal line 7 in units of rows, and the electrical signal taken out to the readout circuit 4 is horizontal. The scanning circuit 3 sequentially outputs to the output terminal 6 via the output amplifier 5 in units of columns. 1 and 2, VDD is a power supply voltage.

  In the drawing, the four pixels 1 of the pixel block 10 to be described later are distinguished from each other with reference numerals 1-1 to 1-4 in order from the lower side in FIGS. 1 and 2, but these are not distinguished. In the following description, reference numeral 1 may be attached to the description. Also, in the drawings, the photodiodes of the pixels 1-1 to 1-4 are distinguished from each other as PD1 to PD4, respectively. However, when they are described without distinguishing them, both are denoted by reference numeral PD. There is a case. Similarly, the transfer transistors of the pixels 1-1 to 1-4 are distinguished from each other as TX1 to TX4. However, when the description is made without distinguishing these, the description may be given with the reference TX. .

  In the present embodiment, the plurality of pixels 1 form a pixel block 10 for each of M pixels 1 in which photodiodes PD as photoelectric conversion units are sequentially arranged in the column direction. In the present embodiment, M = 4, but in the present invention, M may be 3 or more. As shown in FIG. 2, for each pixel block 10, four pixels 1 (1-1 to 1-4) belonging to the pixel block 10 include one set of floating capacitor unit 20, amplification transistor AMP, and reset transistor. The RST and the selection transistor SEL are shared. Therefore, the number of transistors per pixel can be reduced and the aperture ratio can be increased. The floating capacitor unit 20 has a variable capacitance value, and constitutes a charge-voltage converter that converts the transferred charge into a voltage. The configuration of the floating capacitor unit 20 will be described later.

  The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to its own input unit (gate) potential (the potential of the floating capacitor unit 20). The reset transistor RST constitutes a reset unit that resets the potential of the floating capacitor unit 20. The selection transistor SEL constitutes a selection unit for selecting the pixel block 10. The photodiode PD and the transfer transistor TX are provided for each pixel 1 without being shared by the four pixels 1 (1-1 to 1-4). As a result, the transfer transistors TX are provided one-to-one with respect to the photodiode PD. Each transfer transistor TX transfers the charge of the corresponding photodiode PD to the output section (diffusion regions 21 to 24 described later) side. In FIG. 1 and FIG. 2, n indicates a row of the pixel block 10. For example, a pixel block 10 in the first row is constituted by the pixels 1 in the first row to the fourth row, and a pixel block 10 in the second row is constituted by the pixels 1 in the fifth row to the eighth row.

  In this embodiment, in each pixel block 10, M transfer transistors TX are divided into N groups (N is an integer of 2 or more smaller than M), and N switches FDX are provided for each group. Are provided so as to turn on and off between the output part of the transfer transistor TX belonging to the group and the input part of the amplification transistor AMP. In this embodiment, M = 4 and N = 2, and the number of transfer transistors TX in each group is the same two. In FIG. 2, the two switches FDX are distinguished from each other and denoted by reference numerals FDX1 and FDX2, respectively. A specific connection relationship between the switches FDX1 and FDX2 will be described later. The floating capacitor unit 20 includes the above-described switches FDX1 and FDX2, capacitors formed by floating diffusion regions 21 to 29 described later, and capacitors formed by related wirings.

  FIG. 3 is a schematic plan view schematically showing two pixel blocks 10 in FIG. 1 arranged in the row direction. In practice, a color filter, a microlens, and the like are disposed above the photodiode PD, but are omitted here. In FIG. 3, the layout of the ground line is omitted.

  In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel portion such as a photodiode PD is arranged in the P-type well. . In FIG. 3, reference numerals 21 to 32 denote N-type impurity diffusion regions which are part of the above-described transistors. Reference numerals 41 to 49 denote gate electrodes of the respective transistors made of polysilicon. The diffusion region 30 is a power supply diffusion portion to which the power supply voltage VDD is applied. Reference numerals 21 to 29 denote diffusion regions constituting the floating capacitor unit 20.

  The photodiodes PD1 to PD4 are embedded by an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) disposed on the surface side thereof. Type photodiode. The photodiodes PD1 to PD4 photoelectrically convert incident light and store the generated charges in the charge storage layer.

  The transfer transistor TX1 is an nMOS transistor in which the charge storage layer of the photodiode PD1 is a source, the diffusion region 21 is a drain (output unit), and the gate electrode 41 is a gate. The transfer transistor TX2 is an nMOS transistor having the charge storage layer of the photodiode PD2 as a source, the diffusion region 22 as a drain, and the gate electrode 42 as a gate. The transfer transistor TX3 is an nMOS transistor having the charge storage layer of the photodiode PD3 as a source, the diffusion region 23 as a drain, and the gate electrode 43 as a gate. The transfer transistor TX4 is an nMOS transistor having the charge storage layer of the photodiode PD4 as a source, the diffusion region 24 as a drain, and the gate electrode 44 as a gate.

  The gate electrode 41 of the transfer transistor TX1 is connected to a control line that guides the control signal φTX1 from the vertical scanning circuit 2 for each pixel row. The gate electrode 42 of the transfer transistor TX2 is connected to a control line that guides the control signal φTX2 from the vertical scanning circuit 2 for each pixel row. The gate electrode 43 of the transfer transistor TX3 is connected to a control line that guides the control signal φTX3 from the vertical scanning circuit 2 for each pixel row. The gate electrode 44 of the transfer transistor TX4 is connected to a control line that guides the control signal φTX4 from the vertical scanning circuit 2 for each pixel row.

  The switch FDX1 is an nMOS transistor having the diffusion region 25 as a source, the diffusion region 26 as a drain, and the gate electrode 45 as a gate. The switch FDX2 is an nMOS transistor having the diffusion region 27 as a source, the diffusion region 28 as a drain, and the gate electrode 46 as a gate. The diffusion regions 21, 22, 25 are connected by wiring 51. The diffusion regions 23, 24 and 27 are connected by a wiring 52. The gate electrode 45 of the switch FDX1 is connected to a control line that guides the control signal φFDX1 from the vertical scanning circuit 2 for each pixel block row. The gate electrode 46 of the switch FDX2 is connected to a control line that guides the control signal φFDX2 from the vertical scanning circuit 2 for each pixel block row.

  The reset transistor RST is an nMOS transistor having the power source diffusion region 30 as a drain, the diffusion region 29 as a source, and the gate electrode 47 as a gate. The amplification transistor AMP is an nMOS transistor having the power source diffusion region 30 as a drain, the diffusion region 31 as a source, and the gate electrode 48 as a gate (input portion). The diffusion regions 26, 28, 29 and the gate electrode 48 are connected by wirings 53, 54. The gate electrode 47 of the reset transistor RST is connected to a control line that guides the control signal φRST from the vertical scanning circuit 2 for each pixel block row.

  The selection transistor SEL is an nMOS transistor having the diffusion region 31 as a drain, the diffusion region 32 as a source, and the gate electrode 49 as a gate. The diffusion region 32 is connected to the vertical signal line 7. The gate electrode 49 of the selection transistor SEL is connected to a control line that guides a control signal φSEL from the vertical scanning circuit 2 for each pixel block row.

  The transistors TX1 to TX4, RST, and SEL and the switches FDX1 and FDX2 are turned on when the corresponding control signals φTX1 to φTX4, φRST, φSEL, φFDX1, and φFDX2 are at the high level “H”, and are at the low level “L”. Turn off.

  The floating capacitor unit 20 enters the following first to third states by the control signals φFDX1 and φFDX2 supplied to the gates of the switches FDX1 and FDX2.

  The first state is a state in which both φFDX1 and φFDX2 are “H” and both the switches FDX1 and FDX2 are on. In this state, the capacitance of the diffusion regions 21 to 29, the gate capacitance of the amplification transistor AMP, and the capacitance of the wiring connecting them contribute to the input portion (gate) of the amplification transistor AMP. Therefore, since the capacitance value of the floating capacitance unit 20 with respect to the gate of the amplification transistor AMP is increased, an output signal with a high saturation charge amount can be obtained.

  The second state is when φFDX1 is “H”, φFDX2 is “L”, switch FDX1 is on, and switch FDX2 is off. In this state, the capacitance of the diffusion regions 21, 22, 25, 26, 28, and 29, the gate capacitance of the amplification transistor AMP, and the capacitance of the wiring connecting them contribute to the input portion (gate) of the amplification transistor AMP. However, the capacitance of the diffusion regions 23, 24, 27 and the wiring connecting them does not contribute. Therefore, the capacitance value of the floating capacitor unit 20 with respect to the gate of the amplification transistor AMP in the second state is approximately half that of the first state. For this reason, in the second state, the charge-voltage conversion gain of the floating capacitor 20 becomes high, and a highly sensitive output signal is obtained.

  The third state is when φFDX2 is “H”, φFDX1 is “L”, switch FDX2 is on, and switch FDX1 is off. In this state, the capacitance of the diffusion regions 23, 24, 27, 26, 28, 29, the gate capacitance of the amplification transistor AMP, and the capacitance of the wiring connecting them contribute to the input portion (gate) of the amplification transistor AMP. However, the capacitance of the diffusion regions 21, 22, 25 and the wiring connecting them does not contribute. Therefore, the capacitance value of the floating capacitor unit 20 with respect to the gate of the amplification transistor AMP in the second state is approximately half that of the first state. For this reason, in the third state, the charge-voltage conversion gain of the floating capacitor unit 20 is increased, and an output signal with high S / N and high sensitivity can be obtained.

  FIG. 4A is a timing chart showing a first operation mode of the solid-state imaging device according to the present embodiment. This first operation mode is an operation mode in the case where an output signal having a large saturation charge amount (a wide dynamic range) is obtained using the first state. (N) indicates a signal of the pixel block 10 in the nth row.

  In this embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layers of the photodiodes PD1 to PD4 of each pixel block 10, the pixel block 10 is moved to one row. These are sequentially selected one by one, and the same operation is sequentially performed for each row. FIG. 4A shows an operation when the pixel block 10 in the n-th row is selected. Since the operations of the readout circuit 4 and the horizontal scanning circuit 3 after the signal is output to the vertical signal line 7 are known, the description thereof will be omitted below. These points also apply to FIG. 4B described later.

  In the first operation mode, the control signals φFDX1 and φFDX2 are both fixed at “H”.

  When the pixel block 10 in the n-th row is selected, the control signal φSEL (n) is set to “H” to connect the pixel block 10 in the n-th row to the vertical signal line 7.

  Then, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and the dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX1 (n) is set to “H”, the signal charge stored in the photodiode PD1 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and a dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX2 (n) is set to “H”, the signal charge accumulated in the photodiode PD2 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and a dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX3 (n) is set to “H”, the signal charge accumulated in the photodiode PD3 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and a dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. The control signal φTX4 (n) is set to “H”, the signal charge accumulated in the photodiode PD4 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Thereafter, the control signal φSEL (n) is set to “L” to disconnect the pixel block 10 from the vertical signal line 7. This completes the reading of the four pixel rows of the pixel block 10 in the nth row. The readout of the pixel blocks 10 in other rows is performed in the same manner.

  FIG. 4B is a timing chart showing a second operation mode of the solid-state imaging device according to the present embodiment. The second operation mode is an operation mode in the case where a highly sensitive output signal is obtained using the second and third states.

  In the first operation mode, when the pixel block 10 in the n-th row is selected, the control signal φSEL (n) is set to “H” to connect the pixel block 10 in the n-th row to the vertical signal line 7. To do.

  First, the control signal φFDX1 is set to “H”, and the control signal φFDX2 is set to “L”.

  Then, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and the dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX1 (n) is set to “H”, the signal charge stored in the photodiode PD1 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and a dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX2 (n) is set to “H”, the signal charge accumulated in the photodiode PD2 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φFDX1 (n) is set to “L”, and the control signal φFDX2 (n) is set to “H”.

  Then, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and the dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX3 (n) is set to “H”, the signal charge accumulated in the photodiode PD3 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Next, the control signal φRST (n) is set to “H” to reset the potential of the floating capacitor 20, and a dark level voltage is amplified by the amplification transistor AMP and output to the vertical signal line 7. Next, the control signal φTX4 (n) is set to “H”, the signal charge accumulated in the photodiode PD4 is converted into a voltage by the floating capacitor unit 20, amplified by the amplification transistor AMP, and output to the vertical signal line 7.

  Thereafter, the control signal φSEL (n) is set to “L” to disconnect the pixel block 10 from the vertical signal line 7. This completes the reading of the four pixel rows of the pixel block 10 in the nth row. The readout of the pixel blocks 10 in other rows is performed in the same manner.

  In the present embodiment, the vertical scanning circuit 2 is described above so that the first operation mode and the second operation mode are selectively performed in response to the operation mode selection signal φMS from the outside. Each control signal is transmitted. For example, the operation mode selection signal φMS is supplied from the outside so that the first operation mode is performed at the time of low-sensitivity imaging and the second operation mode is performed at the time of high-sensitivity imaging.

  Therefore, according to the present embodiment, imaging is performed in the first operation mode for obtaining an output signal having a large saturation charge amount and a wide dynamic range, and by the second operation mode for obtaining an output signal with high S / N and high sensitivity. Imaging can be performed selectively, and both expansion of the dynamic range at low sensitivity and high S / N at high sensitivity can be achieved.

  Here, a solid-state imaging device according to a comparative example compared with the solid-state imaging device according to the present embodiment will be described. This comparative example is different from the present embodiment only in the configuration of the floating capacitor 20 of each pixel block 10. In this comparative example, the switches FDX1 and FDX2 (and therefore the diffusion regions 25 to 28) are removed from the floating capacitor unit 20, and the drain diffusion regions 21 to 24 of the transfer transistors TX1 to TX4 are connected to the gates of the amplification transistors AMP by wiring. Connected to. This comparative example corresponds to a conventional solid-state imaging device.

  In this comparative example, the floating capacitance unit 20 has the capacitance of the diffusion regions 21 to 24 and 29, the gate capacitance of the amplification transistor AMP, and the capacitance of the wiring connecting them to the input portion (gate) of the amplification transistor AMP. Always contribute. When this is compared with the second state of the present embodiment, the capacitance contributing to the input portion (gate) of the amplification transistor AMP is the diffusion region 25 in the second state as compared with this comparative example. , 26, and 28 increase in capacity, but the capacity of the diffusion regions 23 and 24 and the amount of wiring that contributes to the short is reduced. Further, the capacitance contributing to the input portion (gate) of the amplification transistor AMP is larger in the third state than the comparative example, but the capacitance of the diffusion regions 27, 26, and 28 is increased. The capacity of 21 and 22 and the contribution of short contributing wiring are reduced. The capacitances of the diffusion regions 21 to 24 must be considerably large in order to achieve complete transfer of charges from the photodiode PD, whereas the diffusion regions 25 to 28 constitute a mere switch and thus are considerably small. I'll do it. Therefore, the capacitance that contributes to the input portion (gate) of the amplification transistor AMP can be considerably reduced in total in the second and third states compared to the comparative example. Therefore, in the second and third states, the charge-voltage conversion gain of the floating capacitor unit 20 is considerably higher than that in the comparative example, and an output signal with higher S / N and higher sensitivity can be obtained.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this embodiment.

  For example, when M (M is an integer of 3 or more) transfer transistors TX are divided into N groups (N is an integer of 2 or more smaller than M), in the embodiment, M = 4 and N = 2. The number of transfer transistors TX in each group is the same two. However, the present invention is not limited to this. For example, the number of transfer transistors TX in each group may be different. As a specific example, M = 3 and N = 2, and the transfer transistor TX is divided into one group (first group) and the transfer transistor TX is divided into two groups (second group). On the other hand, the switch FDX1 may be provided, and the switch FDX2 may be provided for the second group. In this case, when only the pixel rows related to the transfer transistor TX of the first group are thinned and read, an output signal having a large saturation charge amount and a wide dynamic range can be obtained in an operation mode in which both the switches FDX1 and FDX2 are turned on. In addition, an output signal with high sensitivity can be obtained in an operation mode in which the switch FDX1 is turned on and the FDX2 is turned off. When all the pixel rows are read without performing the thinning-out reading, an output signal having a large saturation charge amount and a wide dynamic range may be obtained in an operation mode in which both the switches FDX1 and FDX2 are turned on.

1 (1-1 to 1-4) Pixel 10 Pixel block 20 Floating capacitor 21 to 29 Floating diffusion region PD1 to PD4 Photodiode AMP Amplifying transistor RST Reset transistor TX1 to TX4 Transfer transistor SEL Select transistor FDX1, FDX2 Switch

Claims (3)

M photoelectric conversion units (M is an integer of 3 or more);
An amplifying unit provided in common for the M photoelectric conversion units;
M transfer transistors that are provided one-to-one with respect to the M photoelectric conversion units and transfer charges from the M photoelectric conversion units to the amplification unit, respectively.
The M transfer transistors are divided into N groups (N is an integer of 2 or more smaller than M), one for each group, between the transfer transistors belonging to the group and the amplification unit. N switches provided in the
Equipped with a,
In the first operation mode, the operation of selectively turning on one of the M transfer transistors is performed on the condition that the one transfer transistor is connected to the amplifying unit. This is done with the above turned on,
In the second operation mode, an operation of selectively turning on one of the M transfer transistors is one of the N switches on condition that the one transfer transistor is connected to the amplification unit. Only done with the on,
A solid-state imaging device. Solid-state imaging device according to claim 1, wherein the output of each transfer transistor is in the floating diffusion region.   The solid-state imaging device according to claim 1, wherein the number of the transfer transistors belonging to each group is the same.

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