JPH1041240A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the leakage current caused by a secondary defect so as to make a p-n junction shallower by injecting a dopant into the main surface of a silicon substrate at a range longer than that of an impurity containing an element having such a property that prevents the solid-phase growth of silicon after the impurity is injected into the main surface of the substrate until an amorphous layer is formed. SOLUTION: An amorphous layer 1a is formed on the surface of a silicon single-crystal substrate 1 by implanting ions of an element, such as N<+> , C<+> , O<+> , Kr<+> , Ar<+> , He<+> , etc., having such a property that prevents the solid-phase grown of silicon into the substrate 1. Then a mask 5 is formed on the surface of the substrate 1 and an n- or p-type dopant is injected into the substrate 1 for forming a heavily doped active layer. The injecting energy of the dopant is set so that the range of the dopant can become longer than that of the injected impurity. Thereafter, the amorphous layer 1a is recrystallized through heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of devices, MOS (Meta
l Oxide Semiconductor) It is necessary to reduce the dimension in the depth direction and the lateral direction of the high concentration active layer such as the source / drain region of the transistor based on the design rule. In conventional junction formation by a combination of ion implantation and heat treatment, lowering the energy of implantation and lowering the temperature of heat treatment are required to form a shallow junction. However, in this junction formation, there is a limit in forming a shallow junction, and a sufficient effect cannot be obtained.

[0003] In order to form a shallower junction, a technique called pre-amorphization implantation has been adopted. Hereinafter, this pre-amorphization implantation will be described as a conventional method for manufacturing a semiconductor device.

FIGS. 15 to 17 are schematic sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps. First, referring to FIG. 15, an n-type or p-type silicon single crystal substrate 1
Silicon ions (Si ⁺ ) or germanium ions (Ge ⁺ ) are implanted.

Referring to FIG. 16, the surface of silicon single crystal substrate 1 is made amorphous (pre-amorphized) by this ion implantation, and amorphous layer 1a is formed on the surface of silicon single crystal substrate 1. You.

Referring to FIG. 17, silicon single crystal substrate 1
A mask 5 having a predetermined shape is formed such that a predetermined surface of the mask 5 is exposed. With the mask 5 formed, a p-type dopant such as boron (B) or an n-type dopant such as arsenic (As) or phosphorus (P) is ion-implanted into the surface of the silicon single crystal substrate 1. Thereby, the amorphous layer 1a
A p-type or n-type impurity diffusion region 3 is formed on the surface of silicon single crystal substrate 1 in the inside. Thereafter, a heat treatment is performed to recrystallize the amorphous layer 1a.

According to this pre-amorphization implantation, as shown in FIG. 17, a dopant is implanted in a state where the amorphous layer 1a is formed. For this reason, the injection energy can be reduced to reduce the injection range Rp and suppress channeling. Therefore, a shallow junction can be formed.

FIG. 18 shows the concentration distribution of the dopant implanted by this conventional manufacturing method from the substrate surface. Referring to FIG. 18, the dopant concentration distribution curve (dotted line) immediately after the implantation is a curve having a concentration peak at a predetermined depth position from the substrate surface. When heat treatment is performed from this state, the dopant diffuses. As a result, the concentration distribution curve (solid line) of the dopant after the heat treatment becomes a gentler curve than that immediately after the implantation. That is, in the dopant concentration distribution curve after the heat treatment, the concentration is lower at the concentration peak than immediately after the implantation, and is higher at the tail (region T) than immediately after the implantation.

[0009]

SUMMARY OF THE INVENTION In the conventional manufacturing method,
In order to sufficiently suppress channeling and diffusion, it is necessary to form the amorphous layer 1a (hatched region) so as to sufficiently cover the range of the dopant as shown in FIG. Therefore, the impurity implantation energy for forming the amorphous layer 1a increases.

When the amorphous layer 1a is recrystallized by a heat treatment, as shown in FIG.
In the vicinity of the interface (dotted line) between b and the crystallized region 1 of the substrate, a secondary defect (crystal defect) 7 is generated due to the effect of mixing the impurities injected for forming the amorphous layer 1a. In the conventional manufacturing method, as described above, the amorphous layer 1a is formed so as to cover the range of the dopant.
Is located immediately below the pn junction between the impurity diffusion region 3 and the silicon substrate 1.

The p between the impurity diffusion region 3 and the silicon substrate 1
A depletion layer is formed at the n-junction. Since the impurity concentration of the silicon substrate 1 is considerably lower than the impurity concentration of the impurity diffusion region 3, this depletion layer spreads greatly toward the silicon substrate 1. Therefore, as shown in FIG. 21, the secondary defect 7 located immediately below the impurity diffusion region 3 is easily taken into the depletion layer 3a during operation of the device. Thus 2
When the secondary defect 7 is taken into the depletion layer 3a, there is a problem that a leakage current is generated from the secondary defect 7.

Further, since the secondary defect 7 is generated immediately below the impurity diffusion region 3, so-called accelerated diffusion occurs. That is, due to the secondary defect 7, S
There are many regions where i atoms are missing, and impurities (dopants) are easily diffused by passing through the portions where the Si atoms are missing. As a result, the tail (T portion) of the dopant concentration distribution curve shown in FIG. 18 is deep, that is, shifted in the arrow direction in the figure. Therefore, there is also a problem that the junction depth becomes deep and a shallow junction cannot be obtained.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of suppressing a leak current due to a secondary defect and obtaining a shallow pn junction and a method of manufacturing the same.

[0014]

According to a method of manufacturing a semiconductor device of the present invention, a dopant and an impurity are implanted into a main surface of a silicon substrate in different steps, and an impurity diffusion region is formed on the main surface of the silicon substrate by implanting the dopant. A method of manufacturing a semiconductor device to be formed, which has the following features.

The impurity includes an element having a property of preventing solid phase growth of silicon, and the impurity is implanted until an amorphous layer is formed on the silicon substrate. The impurity and the dopant are implanted such that the range of the impurity in the silicon substrate is smaller than the range of the dopant.

In the method of manufacturing a semiconductor device according to the present invention, the range of the impurity for forming the amorphous layer is smaller than the range of the dopant. Therefore, a secondary defect occurs at a position shallower than the depth of the pn junction formed by the impurity diffusion region formed by the implantation of the dopant and the first conductivity type region of the silicon substrate. Since the secondary defect (crystal defect) has an effect of gettering the dopant, the dopant located deeper than the secondary defect is drawn to the secondary defect side. In the secondary defect portion, the dopant concentration is increased due to the attraction of the dopant. Thus, an impurity diffusion region having a small diffusion depth and a high dopant concentration can be formed.

In addition, as an impurity for forming an amorphous layer, an impurity having a property of preventing solid phase growth of silicon is used. For this reason, at the time of solid phase growth for recrystallization of the amorphous layer, an effect of decreasing the speed of the solid phase growth is added, thereby producing secondary defects having a high density and a large diameter. Therefore, the effect of gettering due to the secondary defect can be more effectively obtained as described above.

The semiconductor device of the present invention includes a semiconductor substrate of the first conductivity type, an impurity diffusion region of the second conductivity type, and an impurity having a property of preventing solid phase growth of silicon.
The semiconductor substrate has a main surface. The impurity diffusion region is formed on the main surface of the semiconductor substrate. First of semiconductor substrate
A pn junction between the conductivity type region and the impurity diffusion region extends from the main surface to a first depth position. The semiconductor substrate has a plurality of crystal defects distributed along a second depth position shallower from the main surface than the first depth position. The impurity having the property of hindering the solid phase growth of silicon is introduced at a position shallower from the main surface than at the first depth position.

In the semiconductor device of the present invention, since the secondary defect (crystal defect) is formed at a desired depth position, it is possible to form an impurity diffusion region having a small diffusion depth and a high dopant concentration. it can.

As an impurity for forming an amorphous layer, an impurity having a property of preventing solid phase growth of silicon is used. Therefore, the effect of gettering due to the secondary defect can be more effectively obtained.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[0022]Embodiment 1 1 to 4 show a semiconductor device according to a first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the device in the order of steps. Figure 1
For reference, solid phase growth of silicon on silicon single crystal substrate 1
Elements having properties that hinder the reaction, for example, N⁺, N
_Two ⁺, C⁺, O ⁺, O_Two ⁺, Kr⁺, Ar⁺, He⁺,
Ne⁺, Xe⁺, F⁺(Hereinafter referred to as impurities)
It is introduced by an ion implantation method. Here, the silicon solid
Elements that have the property of hindering phase growth include silicon
At a temperature of 800 ° C. by introduction
It means that the recrystallization speed of the film is set to 100 ° / min or less.
This is the first of Kenji Gamo's “semiconductor ion implantation technology”.
It is shown on page 48.

Referring to FIG. 2, the introduction of the impurity forms an amorphous layer 1a on the surface of silicon single crystal substrate 1.

Referring to FIG. 3, a mask 5 is formed on the surface of silicon single crystal substrate 1. This mask 5 may have, for example, a laminated structure of a gate insulating layer and a gate electrode layer, or may have a resist pattern.

With the mask 5 applied, an n-type or p-type dopant for forming a high concentration active layer on the silicon substrate 1 is introduced. This dopant is, for example, As ⁺ and P ⁺ in the case of n-type, and is, for example, B ⁺ and BF ₂ ⁺ in the case of p-type.

The implantation energy of the dopant is set such that the range of the dopant is longer than the range of the impurity implanted in FIG. As a result, the diffusion depth of impurity diffusion region 3, which is a high concentration active layer formed on the surface of silicon single crystal substrate 1, becomes deeper than the depth of amorphous layer 1a.

Thereafter, a heat treatment for recrystallization of the amorphous layer 1a is performed. Referring to FIG. 4, at the time of this recrystallization, due to the effect of mixing of impurities, 2
Secondary defects (crystal defects) occur.

In the manufacturing method of the present embodiment, the amorphous layer 1
The range of the impurity for forming a is smaller than the range of the dopant. Therefore, as shown in FIG. 5, the formation depth of the amorphous layer 1a is smaller than the diffusion depth of the dopant from the substrate surface. Therefore, as shown in FIG.
Secondary defects 7 generated by recrystallization of a are distributed at a position shallower than the pn junction between impurity diffusion region 3 and silicon substrate 1.

Since the impurity concentration of the impurity diffusion region 3 is higher than that of the silicon substrate 1, the vacancy layer 3 a of the pn junction spreads greatly toward the silicon substrate 1.
Does not spread much to the side. Therefore, when the secondary defect 7 is formed at a position shallower than the pn junction as in the present embodiment, the secondary defect 7 is less likely to be taken into the vacant layer 3a than in the conventional example. . Therefore, the secondary defect 7
Can be suppressed from being generated by the incorporation into the void layer 3a.

Further, since the secondary defect 7 has an effect of gettering the dopant, the dopant is drawn toward the secondary defect 7 as shown in FIG. As a result, after the heat treatment for recrystallization, the dopant concentration in the vicinity of the secondary defect 7 becomes equal to or higher than that before the heat treatment (after implantation). Also, the diffusion depth of the dopant is not so different after the heat treatment as after the implantation. Therefore, FIG.
As shown in FIG. 5, when comparing the dopant concentration distribution after heat treatment between the present embodiment and the conventional example, the dopant concentration in the impurity diffusion region 3 of the present embodiment is higher at the concentration peak than the conventional example, and the dopant concentration is higher. Diffusion depth becomes shallower.

In the manufacturing method of the present embodiment, impurities having a property of preventing solid phase growth of silicon are used as impurities for forming the amorphous layer 1a. For this reason, FIG.
In addition to the secondary defects 7 generated at the time of recrystallization shown in (1), an effect of lowering the speed of the solid phase growth of the amorphous layer 1a due to mixing of impurities is added. As a result, a secondary defect 7 having a high density and a large diameter is generated. For this reason, the gettering ability can be improved as compared with the conventional example in which impurities such as silicon and germanium which do not hinder recrystallization are used as impurities.

In the present embodiment, the effect of gettering secondary defects can be obtained, for example, with respect to the dopant existing in the well or channel region of the MOS transistor. Hereinafter, this will be described.

FIG. 8 is a schematic sectional view showing the structure of a MOS transistor manufactured based on the method of the first embodiment of the present invention. Referring to FIG. 8, MOS transistor 10 has a pair of source / drain regions 3, 3, a gate insulating layer 5a, and a gate electrode layer 5b. 1
The paired source / drain regions 3 are formed on the surface of silicon single crystal substrate 1 at a distance from each other. The gate electrode layer 5b is formed on a region between the pair of source / drain regions 3, 3 with the gate insulating layer 5a interposed.

The MOS transistor 10 has the same structure as that of the mask 5 shown in FIGS.
Is formed in a laminated structure of a gate insulating layer and a gate electrode layer. In addition, since the secondary defects 7 are formed by the manufacturing method of the present embodiment, the secondary defects 7 are distributed at positions shallower than the pn junction between the source / drain region 3 and the silicon substrate 1.

As is clear from FIG.
Exists not only in the source / drain region 3 but also in the well region or the channel region of the silicon single crystal substrate 1. Therefore, this silicon single crystal substrate 1
Of the well region or the channel region is also attracted to the secondary defect 7 side. Thus, as shown in FIG. 9, the dopant concentration in the well and channel regions near the secondary defect (solid line) is higher than the dopant concentration in the case where there is no defect (dotted line).

Therefore, the pair of source / drain regions 3, 3 are separated by a well region (or channel region) of the opposite conductivity type and high concentration. Therefore, occurrence of a short channel effect such as punch-through between the pair of source / drain regions 3 can be controlled.

Second Embodiment In the first embodiment, the dopant is implanted after the impurity is implanted to make it amorphous. However, the amorphous may be made after the dopant is implanted. Hereinafter, the method will be described as a second embodiment.

FIGS. 10 to 12 show Embodiment 2 of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device in Step order. First, referring to FIG.
Is formed on the surface of the substrate. This mask 5 may have a laminated structure of a gate insulating layer and a gate electrode layer or a resist pattern as described above. With the mask 5 applied, a dopant is implanted into the surface of the silicon single crystal substrate 1. Thereby, impurity diffusion region 3 is formed on the surface of silicon single crystal substrate 1 exposed from mask 5.

Referring to FIG. 9, while the mask 5 is left, an impurity made of an element having a property that hinders solid phase growth is implanted into the silicon single crystal substrate 1. The impurity implantation energy is set such that the range of the impurity is longer than the range of the dopant in the substrate 1.

Referring to FIG. 10, by the implantation of the impurity, an amorphous layer 1b is formed on the surface of silicon single crystal substrate 1 exposed from mask 5. The amorphous layer 1b is formed at a position shallower than a pn junction between the impurity diffusion region 3 and the silicon substrate 1.

Thereafter, similarly to the first embodiment, the amorphous layer 1
Heat treatment for recrystallization of b is performed.

In this embodiment, as in the first embodiment, the range of the impurity for forming the amorphous layer 1b is smaller than the range of the dopant. For this reason,
A secondary defect (not shown) occurs at a position shallower than the depth of the pn junction formed by the impurity diffusion region 3 formed by the implantation of the dopant and the silicon substrate 1. Since this secondary defect has an effect of gettering the dopant,
The impurity diffusion region 3 having a small diffusion depth and a high dopant concentration can be formed.

As an impurity for forming the amorphous layer 1b, an impurity having a property of preventing solid phase growth of silicon is used. Therefore, as in the first embodiment, the effect of gettering due to the secondary defect can be more effectively obtained.

In this embodiment, the impurity is implanted with the mask 5 left as shown in FIG.
As shown in FIG. 13, impurities may be implanted after removing mask 5. In this case, an amorphous layer 1c is formed on the entire surface of the silicon single crystal substrate 1 as shown in FIG.

The thus formed amorphous layer 1c
Is formed shallower than the pn junction between impurity diffusion region 3 and silicon substrate 1.

The amorphous layer 1 according to the first and second embodiments
The heat treatment for recrystallizing a is preferably performed in an oxidizing atmosphere. By performing the heat treatment in this atmosphere, more secondary defects can be generated. Therefore, the ability to getter the dopant is increased, and a shallower junction can be formed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0048]

According to the method of manufacturing a semiconductor device of the present invention, the range of an impurity for forming an amorphous layer is smaller than the range of a dopant. Therefore, a secondary defect occurs at a position shallower than the depth of the pn junction formed by the impurity diffusion region formed by the implantation of the dopant and the first conductivity type region of the silicon substrate. Since the secondary defect (crystal defect) has an effect of gettering the dopant, the dopant located deeper than the secondary defect is drawn to the secondary defect side. In the secondary defect portion, the dopant concentration is increased due to the attraction of the dopant. Thus, an impurity diffusion region having a small diffusion depth and a high dopant concentration can be formed.

As an impurity for forming an amorphous layer, an impurity having a property of preventing solid phase growth of silicon is used.
Therefore, during the solid phase growth for recrystallization of the amorphous layer,
The effect of decreasing the rate of solid phase growth is added, which results in secondary defects with high density and large diameter. Therefore, it is possible to more effectively obtain the effect such as gettering due to the secondary defect as described above.

In the semiconductor device of the present invention, since the secondary defect is formed at a desired depth position, the diffusion depth is small,
In addition, an impurity diffusion region having a high dopant concentration can be formed.

As an impurity for forming an amorphous layer, an impurity having a property of preventing solid phase growth of silicon is used. Therefore, the effect of gettering due to the secondary defect can be more effectively obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device in the first embodiment of the present invention.

FIG. 5 is a graph showing the distribution of dopant and impurity concentrations in the depth direction of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a graph showing the distribution of the dopant concentration in the depth direction after the ion implantation and after the heat treatment of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a graph showing a comparison of the distribution of the dopant concentration in the depth direction between the first embodiment of the present invention and the conventional example.

FIG. 8 is a schematic cross-sectional view showing a state where secondary defects are distributed in a well region or a channel region of a MOS transistor in the first embodiment of the present invention.

FIG. 9 is a graph showing a distribution of a dopant concentration in a depth direction in a case where a secondary defect is present in a well region or a channel region of a MOS transistor;

FIG. 10 is a schematic cross-sectional view showing a first step of a method for manufacturing a semiconductor device in Embodiment 2 of the present invention.

FIG. 11 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 13 is a first process chart in a case where the mask is removed in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 14 is a second process chart in a case where the mask is removed in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a schematic sectional view showing a first step of a method of manufacturing a semiconductor device in a conventional example.

FIG. 16 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device in the conventional example.

FIG. 17 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device in the conventional example.

FIG. 18 is a graph showing the distribution of the dopant concentration in the impurity diffusion region in the depth direction in the conventional example.

FIG. 19 is a graph showing a distribution relationship between an impurity diffusion region and an amorphous layer in a conventional example.

FIG. 20 is a schematic cross-sectional view showing a position where a secondary defect occurs when a method of manufacturing a semiconductor device in a conventional example is used.

FIG. 21 is a schematic cross-sectional view showing a state where a depletion layer is widened in a conventional example.

[Explanation of symbols]

1 Silicon single crystal substrate, 1a amorphous layer, 3 impurity diffusion region, 5 mask, 7 secondary defects.

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: implanting a dopant and an impurity into a main surface of a silicon substrate in different steps; and forming an impurity diffusion region on the surface of the silicon substrate by implanting the dopant. Contains an element having the property of hindering the solid phase growth of silicon, and the impurity is implanted until the silicon substrate becomes amorphous, and the range of the impurity in the silicon substrate is reduced by the distance of the dopant. The method for manufacturing a semiconductor device, wherein the impurity and the dopant are implanted so as to be smaller than the distance. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said impurity causes a recrystallization rate of silicon to be 100 ° C./min or less at a temperature of substantially 800 ° C. 3. The method according to claim 1, wherein said impurities are N ⁺ , N ₂ ⁺ , C ⁺ ,
O ⁺ , O ₂ ⁺ , Kr ⁺ , Ar ⁺ , He ⁺ , Ne ⁺ , Xe
^At least one selected from the group of ⁺ and F ⁺
A method for manufacturing a semiconductor device according to claim 2. 4. The method according to claim 1, further comprising the step of subjecting the semiconductor substrate to a heat treatment, wherein the heat treatment crystallizes an amorphous layer, and the recrystallized region in which the amorphous layer is crystallized and a crystal region of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a crystal defect is generated near an interface with the semiconductor device. 5. The semiconductor device according to claim 4, wherein said crystal defects getter said dopant in said impurity region to reduce a diffusion depth of said impurity diffusion region from a main surface of said semiconductor substrate. Production method. 6. A semiconductor substrate of a first conductivity type having a main surface, an impurity diffusion region of a second conductivity type different from the first conductivity type formed on the main surface of the semiconductor substrate, and the semiconductor substrate A pn junction between the first conductivity type region and the impurity diffusion region extends from the main surface to a first depth position, and the semiconductor substrate is located at a position higher than the first depth position. It has a plurality of crystal defects distributed along a second depth position shallow from the main surface, and further has a silicon defect introduced at a position shallower from the main surface than the first depth position. A semiconductor device including an impurity having a property of preventing solid phase growth. 7. The semiconductor device according to claim 6, wherein said impurity makes a recrystallization rate of silicon 100 ° / min or less at a temperature of substantially 800 ° C. 8. The method according to claim 1, wherein the impurities are N ⁺ , N ₂ ⁺ , C ⁺ , O
⁺ , O ₂ ⁺ , Kr ⁺ , Ar ⁺ , He ⁺ , Ne ⁺ , Xe ⁺
The semiconductor device according to claim 7, wherein the semiconductor device is at least one selected from the group ^consisting of F and F ⁺ .