JP3063834B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having trench isolation, and more particularly, to a MOSFET (Metal Oxide Semiconductor Field).
The present invention relates to a method for manufacturing a semiconductor device capable of reducing an inverse narrow channel effect in which a threshold voltage decreases as a channel width of a transistor decreases in an integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor device manufacturing method, first, as shown in FIG. 9A, a trench 103 is formed in a single crystal silicon substrate 101, and then the trench 103 is formed.
Is oxidized by chemical vapor deposition (CVD) to pile up silicon oxide 105.

[0003] Next, as shown in FIG. 9 (B), the surface of the silicon oxide 10 is removed by a chemical mechanical polishing (CMP) method.
5 is polished and flattened, so that trenches 10 are formed.
3 is buried with silicon oxide 105, and the surface is covered with a gate insulating film 111 provided between the gate electrode 110 and the gate electrode 110 formed on the surface side.

Here, in the state shown in FIG. 9B in which the silicon oxide 105 filling the trench 103 is lower than the surface of the single crystal silicon substrate 101, as shown in FIG.
As shown in the characteristic diagram (C), when the channel width of the MOSFET is reduced from 10 μm to 0.2 μm, the MO
There is a problem that the threshold voltage of the SFET is reduced by about 0.15V.

[0005] The reason is, for example, that the 1981 IED
As described in M (International Electron Device Meeting) Technical Digest (pages 380 to 383), the electric field V and the surface in the direction from the gate electrode 110 to the inside of the single crystal silicon substrate 101 near the trench shoulder 112. This is because there is concentration of the electric field H in a direction parallel to the above, and the threshold voltage decreases at the trench shoulder 112.

That is, when the channel width of the MOSFET is reduced, the ratio of the lowered threshold voltage to the entire channel increases, and the threshold voltage of the MOSFET as a whole also decreases.

To solve this problem, there is a method of increasing the threshold voltage at the end of the semiconductor element by ion-implanting impurities from the side wall of the trench.

However, since the impurity concentration becomes higher near the interface between the single crystal silicon substrate 101 and the oxide film filling the trench 103 than in the single crystal silicon substrate 101, the junction capacitance and the junction leakage current increase.

In order to avoid this problem, for example, as described in JP-A-6-177239, a semiconductor in an element isolation region is etched to form a tapered trench. There is a method of suppressing the electric field concentration by not forming a shoulder shape at the end or chamfering the shoulder shape portion.

[0010]

In the conventional method of manufacturing a semiconductor device described above, a method of suppressing the electric field concentration by not forming a shoulder at the end of the semiconductor element or chamfering the shoulder is used. In addition, when the channel width of the transistor is small, there is a problem that a phenomenon occurs due to an inverse narrow channel effect in which the threshold voltage decreases.

The reason is that the boron contained in the channel diffuses outward because it piles up on the silicon oxide side at the interface between the silicon of the substrate and the silicon oxide filling the trench by thermal diffusion, and the vicinity of the interface between the trench and the substrate. This forms a region in which the concentration of boron contained in the channel is reduced. This diffusion of boron occurs even at about 800 degrees Celsius due to the presence of interstitial silicon generated by ion implantation or the like.

On the other hand, this phenomenon does not occur because the impurity phosphorus or arsenic forming the n-well is piled up on the silicon side of the substrate and does not diffuse outward from the channel.

An object of the present invention is to solve the above problems and to provide a method of manufacturing a semiconductor device in which the threshold voltage does not decrease even when the channel width of the transistor decreases.

[0014]

A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having trench isolation over a p-well and an n-well. Subsequent to the forming step, there is provided a step of simultaneously implanting boron ions into the entire surface of the main surface including both side surfaces of the trench.

Further, as a constituent requirement, in the step of ion implantation for forming an n-well, it is added that silicon is implanted into the n-well region. Further, in the step of implanting boron ions, boron and phosphorus ions are sequentially implanted,
Ion implantation of boron and arsenic sequentially, or
The ion implantation of boron, phosphorus, and arsenic in sequence may be mentioned. In addition, the step of implanting boron ions after the n-well region is covered with the photoresist can be added as a constituent feature.

According to this structure, by implanting boron only in the substrate near the interface between the silicon of the substrate and the silicon oxide filling the trench, an amount that compensates for the decrease in concentration does not increase the junction capacitance or the junction leakage. . Further, it is unnecessary to increase the number of photoresist steps by implanting boron into the entire surface.

Further, in the n-well region in which boron is implanted and the threshold voltage on the side surface is reduced, piled-up phosphorus or arsenic cancels the function of boron, so that the threshold voltage does not decrease.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. In the method for manufacturing a semiconductor device shown in FIG. 1, a trench 3 is formed as shown in FIG. 1A after a step of forming a silicon oxide 2 on the surface of a first conductivity type single crystal silicon substrate 1. It shall have been done.

In the next step, as shown in FIG. 1B, boron 4 is ion-implanted obliquely over the entire surface including the side surfaces of the trench 3 using the silicon oxide 2 as a mask. For example, it is assumed that boron 4 is ion-implanted into the side wall surface of the trench 3 at a dose of 5E12 cm ⁻² . By this ion implantation, a boron implanted layer 5 is formed. The implantation depth may be such that the peak of the impurity distribution is about 50 nm from the surface.
When tilted by about 30 keV, about 30 KeV may be applied.

The above conditions do not limit the present invention. When the implantation angle is different, or when a mask such as silicon oxide is formed on the trench surface, the conditions can be changed depending on the respective conditions.

Next, as shown in FIG. 1C, the trench 3 is filled with silicon oxide 6 and the single crystal silicon substrate 1 in a region other than the silicon oxide 6 is exposed by a process such as surface polishing to form a p-well 7. After ion implantation of impurities for forming the n well 8 and the n well 8, respectively, the source / drain 11 is formed by annealing. During this step, boron is acceleratedly diffused and the concentration is reduced mainly by silicon between lattices generated in the ion implantation step. However, only boron corresponding to the amount initially implanted over the entire surface is formed in the trench 3. Since the boron is diffused outward into the buried oxide film, the boron concentration does not drop below a predetermined concentration in the p-well 7 near the interface between the single crystal silicon substrate 1 and the trench 3, and the reverse narrow channel effect does not occur.

FIG. 1C shows a state in which a gate electrode patterning step for forming a gate insulating film 9 and a gate electrode 10 and a source / drain region forming step for forming a source / drain 11 region have been completed. I have.

FIG. 2 is a characteristic diagram showing the channel width dependence of the threshold voltage of the MOSFET based on the process described with reference to FIG. As shown, even if the channel width changes, the threshold voltage hardly changes.

Next, a second embodiment different from FIG. 1 will be described with reference to FIG.

In FIG. 1C, it is desirable that boron in the n-well 8 region is diffused outward in the direction of the silicon oxide 6 in the trench as much as possible. For this reason,
As shown in FIG. 3, at the time of ion implantation into the n-well 8, silicon 13 is additionally implanted using the photoresist 12 as a mask to increase the amount of silicon between lattices. In this case, the dose is desired to be 1E14 cm ⁻² or more.

Next, a third embodiment having the characteristics shown in FIG. 4 will be described.

FIG. 4 is a characteristic diagram in the case where boron ions are additionally implanted into the entire surface in FIG. 1B. Phosphorus is ion-implanted at an energy of a depth similar to that of boron and at a dose equal to or twice that of boron. In this method, the inverse narrow channel effect remains, but the channel width is 10 μm.
Threshold voltage is 0.08 V
This is a degree of reduction, and a significant improvement was confirmed as compared with the conventional characteristics shown in FIG. 9 (C).

This effect is the same even when arsenic is used instead of phosphorus, and the same applies when phosphorus and arsenic are combined. The improved effect is the same regardless of whether the injection timing is before or after the boron injection step.

As shown in FIG. 5, it is also effective to selectively implant boron ions only in the p-well 7. In this case, as shown, after the step of forming the trench 3, only the n-well 8 is covered with the photoresist 14.
And boron ions may be implanted. However, in the case where the separation width is small in this step, if boron is implanted by inclining boron, a situation arises in which implantation is impossible due to the shadow of the photoresist 14.

FIGS. 6A and 6B are explanatory views of the fourth and fifth embodiments illustrating the shapes of the photoresists 15 and 16 used for avoiding the problem occurring in FIG.

In FIG. 6A, the photoresist 1 shown in FIG.
After the formation of the photoresist 4, the photoresist 15 having a rounded shoulder is formed by annealing at a temperature at which the photoresist 14 flows, for example. As a result, there is less shadow behind ion implantation.

In FIG. 6B, after the photoresist 14 of FIG. 5 is formed, the photoresist 14 is anisotropically etched to form a sidewall by the photoresist 16 on the side wall of the trench. The effect is obtained.

The steps described above are incorporated into other steps, and the steps described above can be freely replaced or changed simultaneously, as long as the above functions are satisfied, and the above description limits the present invention. Not something.

Next, referring to FIG. 7 and FIG.
A sixth embodiment will be described.

As described in the description of the second embodiment, in FIG. 1C, boron in the n-well 8 region is diffused outward in the direction of the silicon oxide 6 in the trench as much as possible. Is desirable. On the other hand, the region of the p-well 7 is 0.25 from the interface of the gate insulating film 9.
The concentration of boron in the region up to the micrometer depth and up to the single crystal silicon substrate 1 does not affect the threshold voltage of the MOSFET. However, conversely, as the concentration of boron in this region increases, the junction capacitance or junction leakage increases, so that boron in this region also diffuses outward in the direction of silicon oxide 6 in the trench as much as possible, as described above. desirable.

For this reason, in the sixth embodiment, as shown in FIG. 7, in the step after the formation of the p-well 7 region and the n-well 8 region, silicon is implanted into the entire surface to remove silicon between lattices. Keep increasing. In this case, the peak depth of the silicon implantation is the same as the depth of the trench, and the dose is 1E14c.
m- ² or more is desired.

As described in the sixth embodiment,
In the p-well 7 region, the boron concentration in the region from the interface of the gate insulating film 9 to the single crystal silicon substrate 1 at a depth of 0.25 μm or more does not affect the threshold voltage of the MOSFET, but on the contrary. Since the junction capacitance or the junction leakage increases as the boron concentration in this region increases, it is desirable that boron in this region is also diffused outward in the direction of silicon oxide 6 in the trench as much as possible.

However, the gate electrode 10 in the p-well 7 region
If the concentration of boron underneath is too low,
This causes a problem that a current due to punch-through flows between them. To solve this problem, the following processing, that is, the seventh embodiment can be taken.

Next, a seventh embodiment will be described with reference to FIG. 8 and FIG.

As shown in the figure, in the step after patterning the gate electrode 10, silicon is implanted into the entire surface to increase the amount of silicon between lattices. In a subsequent step, before forming the source / drain 11 region, a heat treatment at 800 ° C. or more is performed to accelerate and diffuse boron. With this method, the concentration of boron in the region below the gate electrode 10 does not decrease.

[0042]

As described above, according to the present invention, the effect of reducing the inverse narrow channel effect of a semiconductor device using trench isolation can be obtained.

The reason is that, after the trench is formed, boron is ion-implanted into the entire surface, so that the boron ion-implantation outwardly diffuses toward the silicon oxide filling the trench by thermal diffusion, resulting in a decrease in concentration. This is because boron can be compensated.

The present invention is particularly effective against the reverse narrow channel effect of the nMOSFET, and according to the embodiment, the standby current of the semiconductor integrated circuit device can be reduced by 30%.

[Brief description of the drawings]

FIG. 1 is an explanatory sectional view showing an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing an example of channel width dependence of a threshold voltage in FIG.

FIG. 3 is an explanatory sectional view showing a second embodiment of the present invention.

FIG. 4 is a characteristic diagram showing an example of channel width dependence of a threshold voltage according to a third embodiment of the present invention.

FIG. 5 is an explanatory cross-sectional view showing one mode of an intermediate step of the present invention.

FIG. 6 is an explanatory sectional view showing a fourth embodiment (A) and a fifth embodiment (B) of the present invention.

FIG. 7 is an explanatory sectional view showing a sixth embodiment of the present invention.

FIG. 8 is an explanatory sectional view showing a seventh embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional explanatory views showing an example of the related art.
FIG. 7C is a characteristic diagram (C) showing an example of channel width dependence of threshold voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2, 6 Silicon oxide 3 Trench 4 Boron 5 Boron injection layer 7 P well 8 N well 12, 14, 15, 16 Photoresist 13, 17, 18 Silicon

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/76

Claims (10)

(57) [Claims] 1. A method of manufacturing a semiconductor device including a straddle trench isolation on the p-well and n-well, next to the step of forming a trench in the main surface of the semiconductor substrate, said containing both sides of the trench A method for manufacturing a semiconductor device, comprising the step of simultaneously implanting boron ions over the entire main surface . 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of ion implantation for forming the n-well, silicon is implanted in an n-well region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of implanting boron, one of boron and phosphorus is implanted, and then the other is implanted. Production method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of implanting boron, one of boron and arsenic is implanted, and then the other is implanted. Production method. 5. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of implanting boron, one of boron and phosphorus and arsenic is first implanted, and then the other is implanted. And then ion-implanting the remaining one. 6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, the semiconductor substrate of the semiconductor device which is a single crystal silicon substrate of a first conductivity type Production method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein after the p-well and the n-well are formed, silicon is implanted over the entire surface. 8. The method of manufacturing a semiconductor device according to claim 7 , wherein a peak depth of the silicon implantation is substantially equal to a depth of the trench isolation. 9. The method of manufacturing a semiconductor device according to claim 1, wherein silicon is implanted into the entire surface after patterning the gate electrode and before forming the source / drain regions. 10. The method of manufacturing a semiconductor device according to claim 9 , wherein a heat treatment at about 800 ° C. or more is performed after the entire surface of the silicon is implanted and before a source / drain region is formed. Production method.