JPH10209170A - Semiconductor wafer, its manufacture, semiconductor integrated circuit device, and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer for MIS devices at a low cost which has an improved gettering power and gate oxide film characteristics (GOI). SOLUTION: An epitaxial wafer having an epitaxial layer grown on a main surface of a single crystal Si wafer made by the Czochralski method has a microdefect density of 1×10<6> to 1×10<9> defects/cm<3> as an epitaxially grown single crystal Si wafer. The epitaxial layer is 0.3-3μm thick, and contains an impurity boron of the same conductivity type less than 3×10<16> atoms/cm<3> as that of the single crystal Si wafer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor wafer and a method of manufacturing the same, and a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, the present invention relates to a method for manufacturing a semiconductor device comprising an epitaxial layer grown on a main surface of a single crystal silicon (Si) wafer. Metal I
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device that forms an integrated circuit composed of nsulator semiconductor field effect transistors.

[0002]

2. Description of the Related Art In recent years, in the field of MIS devices in which an integrated circuit is composed of MISFETs, CZ is required to improve the breakdown voltage of a gate oxide film and to reduce the leakage current of a pn junction.
The introduction of a semiconductor wafer (epitaxial wafer) in which an epitaxial layer is grown on the main surface of a single crystal silicon wafer (CZ wafer) manufactured by the (Czochralski) method is in progress.

Conventionally, characteristics of a gate oxide film from a crystal point of view
As a factor influencing (Gate Oxide integrity; GOI), the existence of oxygen precipitates due to grow-in defects is known. Oxygen precipitates are formed by the presence of supersaturated oxygen using vacancies and minute transition loops and impurities associated with interstitial silicon as precipitation nuclei, which act as so-called weak spots on the gate oxide film or leak by collecting contaminant metals. It is thought to cause an increase in current. In addition, COP (Crystal Originated Pit), which is one of the glow-in defects, causes an abnormal shape of the oxide film such as, for example, locally reducing the film thickness or degrading the withstand voltage of the film. Therefore, when forming a gate oxide film of a MISFET by thermally oxidizing the surface of a silicon wafer, it is necessary to reduce the above-described glow-in defects and oxygen precipitates in order to obtain a highly reliable gate oxide film.

In the case of an epitaxial wafer, an epitaxial layer formed on a silicon wafer (CZ wafer) does not take in impurity oxygen during the growth process unlike a silicon wafer, and a large number (up to 20 ppma ( (Equivalent to JEIDA)) Since there are very few glow-in defects in the epitaxial layer,
It is expected that a high quality gate oxide film will be obtained. That is, since the epitaxial wafer forms the gate oxide film of the MISFET by thermally oxidizing the surface of the epitaxial layer, the characteristics of the gate oxide film (Gate Oxide integrity; GO)
I) can be improved.

In the following description, JEIDA is mainly used.
Use the converted ppma unit.
Units may be used. The ppma unit in ASTM conversion is
The following equation: 1 ppma (Old ASTM conversion) = 1.605 ppma (JE
Can be converted to JEIDA-converted ppma according to (IDA conversion).

[0006]

According to the studies made by the present inventors, the epitaxial layer formed on the silicon wafer has a nucleus that captures contaminants such as heavy metals due to the small amount of glow-in defects and oxygen precipitates. Since the number of defects is small, there is a problem that the gettering ability is lower than that of a silicon wafer. Further, when an epitaxial layer is formed on a silicon wafer, hydrogen annealing at 950 ° C. to 1100 ° C. and several tens of minutes is performed before the epitaxial layer is formed in order to remove a natural oxide film on the surface of the silicon wafer. As a result of this heat treatment, glow-in defects in the silicon wafer disappear and oxygen precipitation is suppressed, so that the gettering ability of the silicon wafer itself also decreases.

As a method of adding gettering ability to an epitaxial wafer, a method of introducing an impurity serving as a gettering site into a silicon wafer is known.

For example, Japanese Patent Application Laid-Open No. 1-260832 discloses that
A method is disclosed in which impurities are ion-implanted into a main surface of a silicon wafer, nucleation heat treatment is performed, and then an epitaxial layer is grown. Also, JP-A-8-162
No. 406 discloses that a high-density laser scatterer (infrared laser is incident on a wafer) in single-crystal silicon by increasing the pulling speed or the number of rotations of a crucible (crucible) when single-crystal silicon is pulled by the CZ method. The method discloses a method of forming a defect (detected by scattered light generated at the time) and then growing an epitaxial layer on a silicon wafer.

As described above, an epitaxial wafer for a MIS device has a low resistance (for example, a specific resistance of 0.0) doped with a high concentration of impurities for the purpose of improving the gettering ability.
A silicon wafer of 1 to 0.001 Ωcm) is used. In particular, the addition of boron (B) at a high concentration is considered effective for improving the gettering ability for heavy metals such as iron (Fe). In addition, the use of an epitaxial wafer (p epitaxial layer / p ⁺ silicon wafer) in which an epitaxial layer is grown on a low-resistance silicon wafer improves the latch-up resistance and α-ray resistance of the MIS device. Can also be expected.

However, when an epitaxial layer is formed on a silicon wafer to which impurities are added at a high concentration, impurities in the silicon wafer are diffused outward from the back surface by heat treatment during epitaxial growth (or during a manufacturing process).
As a result, the impurity concentration profile of the element formation region fluctuates due to doping (auto-doping) of the epitaxial layer as a result of the doping (auto-doping) of the epitaxial layer, or the rise of impurities from the main surface of the silicon wafer to the epitaxial layer. MISF, etc.)
ET characteristics may be degraded.

In order to avoid such adverse effects, the MIS
An epitaxial wafer for a device may be formed by growing an epitaxial layer thickly (for example, about 8 to 10 μm) to reduce the influence of impurities flowing up from the silicon wafer, or to form an epitaxial layer on the back surface (and side surface) of the silicon wafer before forming the epitaxial layer. It is necessary to form an insulating film (for example, a silicon oxide film) for preventing outward diffusion of impurities. That is, in order to prevent doping of the epitaxial layer with impurities due to outward diffusion, a step of covering only the back surface (and the side surface) of the silicon wafer with the insulating film is required, so that the manufacturing cost is increased. Further, low resistance (for example, specific resistance 0.01 to 0.00) in which impurities are added at a high concentration.
The production cost of a silicon wafer of about 1 Ωcm is higher than that of a normal silicon wafer having a specific resistance of about 10 Ωcm.

For these reasons, in manufacturing a MIS device using an epitaxial wafer,
It is necessary to take measures so that the effect of reducing the manufacturing cost of the MIS device obtained by improving the reliability and the manufacturing yield by introducing the epitaxial wafer is not offset by the increase in the manufacturing cost of the epitaxial wafer.

An object of the present invention is to provide an epitaxial wafer for a MIS device having improved gettering ability.

Another object of the present invention is to provide an epitaxial wafer for a MIS device having improved gate oxide film characteristics (GOI).

Another object of the present invention is to provide a technique capable of inexpensively manufacturing an epitaxial wafer for a MIS device having improved gettering ability and gate oxide film characteristics (GOI).

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor wafer of the present invention is an epitaxial wafer in which an epitaxial layer is grown on the main surface of a single crystal silicon wafer manufactured by the Czochralski (CZ) method, and the single crystal silicon wafer after the epitaxial growth. Has a micro defect density (BMP density) of 1 ×
It is 10 < ⁶ > to 1 * 10 < ⁹ > pieces / cm < ³ >.

(2) In the semiconductor wafer of the present invention, the thickness of the epitaxial layer is 0.3 to 5 μm, preferably 0.3 to 5 μm.
3 μm.

(3) In the semiconductor wafer of the present invention, the single crystal silicon wafer has an impurity concentration of 1 × 10 ¹⁵ atoms / cm ^3.
As described above, it is less than 3 × 10 ¹⁶ atoms / cm ³ .

(4) In the semiconductor wafer of the present invention, the epitaxial layer contains 1 × 10 ¹⁶ atoms / cm ³ of impurities (boron or phosphorus) of the same conductivity type as the single crystal silicon wafer.
Less than is added.

(5) In the semiconductor wafer of the present invention, the diameter of the single crystal silicon wafer is 12 inches.

(6) The semiconductor wafer of the present invention is an epitaxial wafer in which an epitaxial layer is grown on the main surface of a single crystal silicon wafer manufactured by the Czochralski method, wherein the single crystal silicon wafer after the epitaxial growth is formed by OSDA. The microscopic defect density measured by the apparatus is 6 × 10 ⁶ to 2 × 10 ⁸ / cm ³ .

(7) The method of manufacturing a semiconductor wafer according to the present invention includes the following steps.

(A) The initial oxygen concentration is 17 to 21 ppma (J
A step of preparing a single-crystal silicon wafer having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b) (b) the single-crystal silicon on the single-crystal silicon wafer 1 × 10 ¹⁶ at with same conductivity type as wafer
Impurity less than oms / cm ³ , thickness is 0.3-5μ
m, preferably a step of growing an epitaxial layer of 0.3 to 3 μm.

(8) The method of manufacturing a semiconductor wafer according to the present invention includes the following steps.

(A) The initial oxygen concentration is 14 to 21 ppma (J
A step of preparing a single crystal silicon wafer having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b); And a step of erasing oxygen donors in the single crystal silicon wafer by annealing for at least 30 minutes or more, and (c) 1 × 10 5 on the single crystal silicon wafer having the same conductivity type as the single crystal silicon wafer. A step of growing an epitaxial layer having a thickness of 0.3 to 5 μm, preferably 0.3 to ³ μm, to which an impurity of less than ¹⁶ atoms / cm ³ is added.

(9) In the method of manufacturing a semiconductor wafer according to the present invention, the single crystal silicon wafer after the step (b) has a minute defect density (BMP density) of 1 × 10 ⁶ to 1 × 10 ^9.
Pcs / cm ³ .

(10) In the method of manufacturing a semiconductor wafer according to the present invention, the single crystal silicon wafer after the step (b) has a small defect density of 6 as measured by an OSDA apparatus.
× 10 ^{6 to} 2 × 10 ⁸ pieces / cm ³ .

(11) The semiconductor integrated circuit device of the present invention
The semiconductor wafer has a gate oxide film of the MISFET formed by thermally oxidizing the surface of the epitaxial layer.

(12) The semiconductor integrated circuit device of the present invention
When the impurity concentration of the epitaxial layer is MISFE
It is lower than the impurity concentration of the T channel region.

(13) The semiconductor integrated circuit device of the present invention
A second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer, and a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. Have been.

(14) The semiconductor integrated circuit device of the present invention
A second conductivity type MISFET forming a memory cell of a DRAM is formed in a part of the first conductivity type well, and another part of the first conductivity type well and the second conductivity type well are formed in the MISFET.
Complementary MISFET constituting peripheral circuit of the DRAM
Are formed.

(15) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET forming a memory cell of the nonvolatile memory is formed in a part of the first conductivity type well;
A complementary MISFET forming a peripheral circuit of the nonvolatile memory is formed in another part of the first conductivity type well and the second conductivity type well.

(16) The semiconductor integrated circuit device according to the present invention
The first conductivity type well and the second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the impurity concentration on the surface.

(17) The semiconductor integrated circuit device according to the present invention
The first conductivity type well and the second conductivity type well are separated from each other by an element isolation groove formed in the epitaxial layer.

(18) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) The initial oxygen concentration is 17 to 21 ppma (J
A step of preparing a single-crystal silicon wafer having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b) (b) the single-crystal silicon on the single-crystal silicon wafer 1 × 10 ¹⁶ at with same conductivity type as wafer
Impurity less than oms / cm ³ , thickness is 0.3-5μ
(c) a step of forming a gate oxide film of a MISFET by thermally oxidizing the surface of the epitaxial layer.

(19) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the single crystal silicon wafer after the step (b) has a micro defect density (BMP density) of 1 × 10 ⁶ to 1 ×.
It is 10 ⁹ pieces / cm ³ .

(20) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the single crystal silicon wafer after the step (b) has a micro defect density measured by an OSDA apparatus of 6 × 10 ⁶ to 2 ×. It is 10 ⁸ pieces / cm ³ .

(21) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) The initial oxygen concentration is 14 to 21 ppma (J
A step of preparing a single crystal silicon wafer having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b); And a step of erasing oxygen donors in the single crystal silicon wafer by annealing for at least 30 minutes or more, and (c) 1 × 10 5 on the single crystal silicon wafer having the same conductivity type as the single crystal silicon wafer. Growing an epitaxial layer having a thickness of 0.3 to 5 μm, preferably 0.3 to ³ μm, to which an impurity of less than ¹⁶ atoms / cm ³ is added, and (d) thermally oxidizing the surface of the epitaxial layer. Forming a gate oxide film of the MISFET;

(22) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) The initial oxygen concentration is 14 to 21 ppma (J
A step of preparing a single-crystal silicon wafer having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b) (b) the single-crystal silicon on the single-crystal silicon wafer 1 × 10 ¹⁶ at with same conductivity type as wafer
Impurity less than oms / cm ³ , thickness is 0.3-5μ
m, a step of forming a gate oxide film of a MISFET by thermally oxidizing the surface of the epitaxial layer, and (d) a step of forming a MISFET on the epitaxial layer. Performing a process of erasing oxygen donors in the single-crystal silicon wafer by annealing the single-crystal silicon wafer at least at 600 ° C. for at least 30 minutes.

(23) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the single crystal silicon wafer after the step (b) has a micro defect density (BMP density) of 1 × 10 ⁶ to 1 ×.
It is 10 ⁹ pieces / cm ³ .

(24) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the single crystal silicon wafer after the step (b) has a micro defect density measured by an OSDA apparatus of 6 × 10 ⁶ to 2 ×. It is 10 ⁸ pieces / cm ³ .

[0047]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) An epitaxial wafer (semiconductor wafer) according to the present embodiment will be described with reference to FIGS.
Will be described.

First, as shown in FIG. 1A, an ingot 100 of single crystal silicon is manufactured by using the Czochralski (CZ) method. At this time, the pulling condition is adjusted so that the initial oxygen concentration of the ingot 100 becomes 17 ppma (JEIDA conversion) or more. However, if oxygen is excessive, the crystal strength is reduced, and the wafer is likely to be warped by heat treatment during the process. Therefore, the upper limit of the oxygen concentration is 21 ppma.
(JEIDA conversion). The setting of the oxygen concentration is performed by controlling, for example, the amount of dissolution from the quartz crucible, the convection of the molten silicon, and the amount of evaporation from the surface.

Further, by adding, for example, boron (B) as a dopant at the time of pulling, the impurity (boron) concentration of the ingot 100 is reduced to about 1.5 × 10 ¹⁵ atom.
s / cm ³ (specific resistance = about 10 Ωcm). Ingot 100
The impurity (boron) concentration of may be higher than the above concentration as long as the impurity concentration profile of the element formation region of the epitaxial layer does not fluctuate due to impurities diffused out of the wafer during the later formation of the epitaxial layer.
In order to eliminate the need for a step of forming an oxide film for preventing out-diffusion of impurities on the back surface of the epitaxial wafer, a concentration not exceeding 10 ¹⁵ atoms / cm ³ is appropriate.

That is, the impurity (boron) concentration is determined by the channel concentration (for example, 1 × 10 ¹⁷ at) of the MISFET described later.
oms / cm ³ ) which is lower than 3 × 10 ¹⁶ atoms / cm ³ (specific resistance = approximately 0.5 Ωcm) which is lower by about one digit than MISFET
Any range may be used as long as it does not affect the impurity concentration (for example, about 6 × 10 ¹⁷ atoms / cm ³ ) of the well which determines the device characteristics of the above.

Next, as shown in FIG. 3B, a part of the ingot 100 is cut off, leaving only the ingot 100 in a region where the oxygen concentration and the impurity concentration are within the above-mentioned ranges.

Next, as shown in FIG. 4C, after the outer periphery is ground and the orientation flat (or orientation notch) is formed on the ingot 100, the ingot 100 is thinned as shown in FIG. The silicon wafer 1 is formed by slicing, and then the outer peripheral portion of the silicon wafer 1 is chamfered to prevent chipping.

Next, as shown in FIG. 5E, after lapping both surfaces of the silicon wafer 1 to adjust the thickness and flatness, an acid or an acid is removed to remove mechanical strain caused by the lapping. The both surfaces of the silicon wafer 1 are etched using an alkaline solution.

Next, as shown in FIG. 2F, the silicon wafer 1 is annealed in a nitrogen atmosphere, for example, at about 600 ° C. for about 30 minutes, so that an oxygen donor generated by oxygen mixed in during the lifting of the ingot 100 is formed. Is performed. This is due to the
This is because oxygen is converted into a donor at about 50 ° C., and the resistivity in the wafer surface greatly changes, so that a heat treatment for erasing the oxygen donor is required to obtain a desired resistivity.

Next, as shown in FIG. 7G, the surface of the silicon wafer 1 on which the epitaxial layer is formed is mirror-polished to obtain a p ^- type single crystal silicon wafer (CZ) having a (100) orientation plane. Wafer) 1 is obtained. Note that if an n-type impurity (for example, phosphorus (P)) is added as a dopant when the ingot 100 is pulled up, an n ⁻ -type single crystal silicon wafer (CZ wafer) can be obtained.

Next, as shown in FIG. 2, the same conductivity type (p-type) as the silicon wafer 1 is formed on the surface of the silicon wafer 1.
Is grown to obtain an epitaxial wafer (p ⁻ / p ⁻ epitaxial wafer) 2EW.
In order to form the epitaxial layer 2, for example, first, the silicon wafer 1 is put into an epitaxial growth furnace, and about 950
After annealing for about 10 minutes in a hydrogen atmosphere at ~ 1100 ° C to remove the natural oxide film on the surface, the temperature in the furnace is lowered to a temperature lower than the annealing temperature (about 900 to 1000).
Set in ° C.), then conducting the epitaxial growth by flowing monosilane + B ₂ H ₆ to about 10 minutes. Thereafter, the epitaxial layer 2 is thermally oxidized to form a gate oxide film of the MISFET. A process for forming the MISFET will be described later in detail.

FIG. 3 is a graph showing the relationship between the initial oxygen concentration Oi of a silicon wafer (CZ wafer) and the gate oxide film defect density. The horizontal axis is the initial oxygen concentration (ppma (JE
The vertical axis indicates the gate oxide film defect density (relative value). Assuming that the gate oxide film defect density at an initial oxygen concentration of 18 ppma (in JEIDA) is 1, the gate oxide film defect density decreases as the oxygen concentration decreases. Therefore, in order to reduce the gate oxide film defect density in the silicon wafer (CZ wafer) 1, the initial oxygen concentration needs to be 17 ppma (JEIDA conversion) or less.

FIG. 4 is a graph showing the relationship between the thickness of the epitaxial layer 2 and the defect density of the gate oxide film. The horizontal axis shows the thickness of the epitaxial layer (μm), and the vertical axis shows the gate oxide film defect density (relative value to the CZ wafer). The initial oxygen concentration of the epitaxial layer 2 is 15, 16.5, 19,
It is 20 ppma (JEIDA conversion).

From this graph, it can be seen that the defect density of the gate oxide film does not depend on the initial oxygen concentration, and decreases as the thickness of the epitaxial layer increases. When the film thickness becomes 0.3 μm or more, it becomes about 30 times smaller than that of the CZ wafer. It turns out that it becomes. That is, in the case of an epitaxial wafer, the present inventors have found that the gate oxide film defect density does not increase even if the initial oxygen concentration is higher than 17 ppma (JEIDA conversion).

Therefore, the thickness of the epitaxial layer 2 is at least 0.3 μm or more. The upper and lower limits of the thickness of the epitaxial layer 2 may be determined in consideration of the amount of shaving due to thermal oxidation up to the formation of the gate oxide film, the heat treatment conditions, and the like. The upper limit is particularly set from the viewpoint of reducing the manufacturing cost of the epitaxial wafer. , 5 μm or less, preferably 3 μm
It is appropriate to:

From the above, in the epitaxial wafer, the initial oxygen concentration of the silicon wafer was 17 ppma.
Even if it is higher than (JEIDA conversion) or more, the breakdown voltage of the gate oxide film on the surface of the epitaxial layer does not deteriorate due to the release of impurities from the silicon wafer due to the heat treatment.

Next, the relationship between the thickness of silicon consumed by the sacrificial oxidation and the gate oxide film characteristics (GOI) was examined. FIG. 5 shows that the thickness of the epitaxial layer is constant (1 μm).
Then, the epitaxial layer is intentionally scraped from the surface by sacrificial oxidation, and the remaining thickness of the epitaxial layer is reduced to 0.1 μm.
It shows the relationship between the breakdown voltage and the cumulative failure rate when the thickness is set to 0 μm (marked in the figure) and 0 μm (marked in the figure). In addition, data for an epitaxial layer having a thickness of 1 μm is also shown (indicated by a circle in the figure).

From this graph, when the epitaxial layer disappears due to oxidation (marked with □ in the figure), the gate oxide film characteristic (GOI) is smaller than that of the epitaxial layer having a film thickness of 1 μm (marked with ○ in the figure). It was found to deteriorate. Further, even when the remaining film thickness of the epitaxial layer is 0.1 μm (indicated by a mark in the figure), it deteriorates as compared with the epitaxial layer having a film thickness of 1 μm. This result shows that when the thickness of the epitaxial layer becomes 0.3 μm or more, the gate oxide film characteristic (GOI)
(If the thickness of the epitaxial layer is 0.3 μm or more, the epitaxial layer remains until the gate oxide film forming step).

Epitaxial wafer 2E of the present embodiment
W is the same as the impurity concentration of the epitaxial layer 2 (about 1.5 × 10 ¹⁵ atoms / cm ³ ) or less than that of the silicon wafer 1, but the channel concentration of the MISFET (for example, 1 × 10 ¹⁷ atoms / cm ³ ) If it is lower than ³ ) by about an order of magnitude, that is, 3 × 10 ¹⁶ atoms / cm ³ or less, there is no problem.

FIG. 6 shows a micro defect density (BMD; Bulk) in the silicon wafer 1 of the epitaxial wafer 2EW.
9 is a graph showing the relationship between Micro Defect) and the initial oxygen concentration. The horizontal axis indicates the initial oxygen concentration (ppma (JEIDA conversion)), and the vertical axis indicates the BMD concentration (pieces / cm ³ ). For comparison, a silicon wafer (CZ wafer) having the same oxygen concentration as the epitaxial wafer 2EW (black circle in the figure)
(Open circles in the figure) are also shown.

Observation of the minute defect density was carried out using JEIDA-24.
"Standard Specification for Visual Inspection of Silicon Mirror Wafer"
(Established in March 1974). In order to increase the observation accuracy, the wafer (epitaxial wafer and comparative silicon wafer) is subjected to oxygen deposition annealing (800 ° C., 4 hours + 1000 ° C., 16 hours in a nitrogen atmosphere) for 16 hours, and then the wafer is cleaved and the cleavage plane With an etching solution (K ₂ C
r ₂ O ₇ 11 g + HF 500 ml + H ₂ O ₂ 50 ml)
The substrate was immersed for 1 minute and etched. Thereafter, the vicinity of about 250 μm in the depth direction of the wafer was observed with a microscope to measure the minute defect density.

In the case of a process contamination level in a normal production line, when the BMD concentration is less than 1 × 10 ⁶ / cm ³ ,
If the gate breakdown voltage is degraded due to a decrease in gettering ability, on the other hand, if it exceeds 1 × 10 ⁹ / cm ³ , the wafer tends to warp in the heat treatment step due to a decrease in crystal strength.

In the case of a CZ wafer, the gate breakdown voltage deteriorates as the BMD concentration increases (that is, as shown in FIG. 3, the initial oxygen concentration of the CZ wafer is 14 ppma (J
The gate breakdown voltage is reduced by EIDA conversion), but in the case of a p / p epitaxial wafer, the BM of the epitaxial layer
The D concentration does not increase, and the BMD concentration range focusing on the gettering ability of the CZ wafer as the supporting substrate is 1 × 10 ⁶ to
It can be said that 1 × 10 ⁹ pieces / cm ³ is desirable. That is, in the epitaxial wafer, even in this BMD concentration range, as shown in FIG. 4, the gate breakdown voltage does not deteriorate, and the gate oxide film characteristic (GOI) improves. Thereby, the gate oxide film characteristics (GOI) and the gettering ability can be improved.

FIG. 7 shows an OSDA apparatus (Optical Shallow Defect Analyz) that can observe the density of microdefects having a size of 20 nm or more as an integrated density up to 5 μm in the depth direction of a wafer.
5 is a graph showing the relationship between the density of micro defects and the initial oxygen concentration observed using er). The horizontal axis is the initial oxygen concentration (ppma
(JEIDA conversion)), the vertical axis is the micro defect density (pieces / cm ³ )
It is. Hereinafter, a micro defect density observed using an OSDA apparatus is referred to as an OSDA defect, and the density is referred to as an OSDA defect density.

In the case of a process contamination level in a normal production line, the OS is not sufficient for a p / p epitaxial wafer.
If the DA defect density is 6 × 10 ⁶ / cm ³ or more, the gate breakdown voltage does not deteriorate due to contamination (that is, the gettering ability is improved), but the upper limit is defined by the warpage of the wafer.

Thus, the OSDA defect density range of the p / p epitaxial wafer is from 6 × 10 ⁶ to 2 × 10 ⁸
It can be said that / cm ³ is desirable. That is, in the epitaxial wafer, even in this OSDA defect density range, as shown in FIG. 4, the gate breakdown voltage does not deteriorate, and the gate oxide film characteristic (GOI) improves. Thereby, the gate oxide film characteristics (GOI) and the gettering ability can be improved.

FIG. 8 shows the outline of the OSDA device.
This will be briefly described with reference to FIG.

As shown in the figure, the OSDA apparatus sequentially irradiates each region with laser light of two different wavelengths (532 nm and 810 nm) while rotating the wafer, and analyzes how light is scattered. The light is scattered only at the defective portion, and is attenuated and absorbed by the wafer in the other defect-free portions. The scattered light is detected by two types of detectors, one for 532 nm and the other for 810 nm, and by analyzing those data, the plane distribution, depth and size of the defect can be identified. As a result, minute defects (OSDA defects) having a size of 20 nm or more can be observed up to 5 μm in the depth direction of the wafer.

The inventor of the present invention examined OSDA defects of a silicon wafer (CZ wafer) and an epitaxial wafer by using this OSDA apparatus. As shown in FIG.
It was found that there were few SDA defects.

As for the OSDA device, for example, "E
xtended Abstract of the 1996 International Confere
nce on Solid State Devices and Material, 1996, "p1
51.

FIG. 9 is a graph showing the relationship between the initial oxygen concentration and the amount of precipitated oxygen. The sample wafers are a silicon wafer (CZ wafer) 1 and an epitaxial wafer 2EW. To promote oxygen precipitation, annealing for oxygen precipitation (800 ° C. for 4 hours at + 1000 ° C. for 16 hours in a nitrogen atmosphere)
Time). The amount of oxygen precipitation was determined by a Fourier transform infrared spectrophotometer as the difference between the oxygen concentrations before and after the heat treatment. As shown in the drawing, the amount of precipitated oxygen increases with an increase in the initial oxygen concentration in the silicon wafer 1, but slightly in the epitaxial wafer 2EW.

This graph also shows the amount of oxygen deposited on the silicon wafer that has been subjected to the heat treatment up to the preheating (preheating for removing the natural oxide film) in the epitaxial growth step. It can be seen that oxygen precipitation is suppressed by heat treatment up to preheating. This is presumably because the high-temperature heat treatment up to the preheating dissolves and eliminates glow-in defects in the silicon wafer, thereby suppressing oxygen precipitation.

FIG. 10 shows that the oxygen concentration in the wafer is 1000
SIMS (Secondary Ion M
4 is a graph showing the results of analysis (ass Spectroscopy).
The thickness of the epitaxial wafer used here is 1 μm. For comparison, a single crystal silicon wafer (CZ wafer) having the same oxygen concentration as the epitaxial wafer is also shown.

As shown, before the heat treatment, the oxygen concentration of the epitaxial wafer is lower than that of the silicon wafer.
The difference in the oxygen concentration distribution between the epitaxial wafer and the silicon wafer is eliminated only by performing the heat treatment at 1000 ° C. for 30 minutes. Therefore, it can be seen that oxygen flows from the silicon wafer to the epitaxial wafer due to the heat treatment during the manufacturing process, but the presence of oxygen in the epitaxial wafer itself does not deteriorate the gate oxide film breakdown voltage.

As described above, the wafer according to the present embodiment is an epitaxial wafer 2EW in which the epitaxial layer 2 is grown on the main surface of the single crystal silicon wafer 1 manufactured by the Czochralski (CZ) method. The single crystal silicon wafer 1 has a micro defect density (BMP density) of 1 × 10 ⁶ to 1 × 10 ⁹ / cm ³ .

The wafer according to the present embodiment is an epitaxial wafer 2EW in which an epitaxial layer 2 is grown on a main surface of a single crystal silicon wafer 1 manufactured by the Czochralski method, and the single crystal silicon wafer after the epitaxial growth. 1, OSDA defect density is 6 × 10
^{It is 6 to} 2 × 10 ⁸ particles / cm ³ .

The method of manufacturing a wafer according to the present embodiment includes the following steps.

(A) The initial oxygen concentration is 17 to 21 ppma (J
A step of preparing a single-crystal silicon wafer 1 having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b);
1 × 1 of the same conductivity type as the single crystal silicon wafer 1
Impurity less than 0 ¹⁶ atoms / cm ³ is added, and the film thickness is 0.3
A step of growing an epitaxial layer 2 having a thickness of 5 to 5 μm, preferably 0.3 to 3 μm.

According to the present embodiment, the silicon wafer 1
Since minute defects serving as gettering sites are formed therein at a high concentration, an epitaxial wafer 2EW with improved gettering ability with respect to contaminants such as heavy metals can be realized.

Further, according to the present embodiment, by increasing the initial oxygen concentration of silicon wafer 1, minute defects are formed at a high concentration in epitaxial wafer 2 </ b> EW. 2EW can be realized.

FIG. 11 is a sectional view of a principal part of a semiconductor integrated circuit device in which a complementary MISFET (CMOSFET) is formed on the main surface of the epitaxial layer 2.

In the epitaxial layer 2, an n-type well 3n and a p-type well 3p are formed. Although not particularly limited, each of the n-type well 3n and the p-type well 3p is
In order to improve the latch-up resistance of the CMOS, it has a retrograde structure in which the internal impurity concentration is higher than the surface impurity concentration, and is separated from each other via an element isolation groove 4 formed in the epitaxial layer 2. I have.

A p-channel MISFET Qp is formed in the n-type well 3n formed in the epitaxial layer 2,
An n-channel MISFET Qn is formed in the p-type well 3p. The p-channel type MISFET Qp mainly includes a pair of p-type semiconductor regions (source and drain regions) 6 and 6 formed in an n-type well 3n and an n-type well 3
A gate oxide film 7 formed on the surface of n and a gate electrode 8 formed on the gate oxide film 7 are formed. The n-channel MISFET Qn mainly includes a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed in the p-type well 3p, a gate oxide film 7 formed on the surface of the p-type well 3p, A gate electrode 8 formed on the gate oxide film 7. The gate electrode 8 is composed of, for example, a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film. For example, a silicon oxide film 10 is formed on the gate electrode 8, and a sidewall spacer 11 made of a silicon oxide film is formed on a side wall. The silicon oxide film 10 and the sidewall spacer 11
The gate electrode 8 and the wirings (13a-1
3d).

The first-layer wirings 13 a to 13 d are formed above the p-channel MISFET Qp and the n-channel MISFET Qn via the silicon oxide film 12. The wiring 13a is connected to a p-channel MISFE through a connection hole 14a formed in the silicon oxide film 12.
Electrically connected to one p-type semiconductor region 6 of TQp,
The wiring 13b is connected to the p-channel type MI through the connection hole 14b.
It is electrically connected to the other p-type semiconductor region 6 of the SFET Qp. The wiring 13c is electrically connected to one n-type semiconductor region 9 of the n-channel MISFET Qn through the connection hole 14c, and the wiring 13d is connected to the connection hole 14d.
And is electrically connected to the other n-type semiconductor region 9 of the n-channel type MISFET Qn. Wirings 13a-1
3d is made of, for example, an Al (aluminum) alloy to which Si (silicon) and Cu (copper) are added.

Second-layer wirings 16a and 16b are formed above the first-layer wirings 13a to 13d via an interlayer insulating film 15 made of a silicon oxide film or the like. The wiring 16a has a connection hole 17a formed in the interlayer insulating film 15.
The wiring 16b is electrically connected to the first layer wiring 13b through the connection hole 17b.
c and is electrically connected. The wirings 16a and 16b are
For example, it is composed of an Al alloy to which Si and Cu are added.

A passivation film 18 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the wirings 16a and 16b.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG. 12, an epitaxial wafer (see FIG. 2) having ap ⁻ type epitaxial layer 2 formed on a silicon wafer 1 made of p ⁻ type single crystal silicon is prepared.

Next, as shown in FIG. 13, a silicon oxide film 22 and a silicon nitride film 23 are deposited on the epitaxial layer 2 by a CVD (chemical vapor deposition) method. After patterning the film 23, the silicon oxide film 22 and the epitaxial layer 2 are sequentially etched using the silicon nitride film 23 as a mask to form a groove 4a. Followed by 900
A silicon oxide film (not shown) is formed on the inner wall of the groove 4a by performing a thermal oxidation process at about 1150.degree.

Next, as shown in FIG. 14, a silicon oxide film 24 deposited by CVD on the epitaxial layer 2 is formed.
Is flattened by etch back or chemical mechanical polishing, and is left inside the groove 4a to form the element isolation groove 4. Subsequently, a heat treatment of about 1000 ° C.
Is densified. These heat treatments and thermal oxidation treatments belong to the highest temperature heat treatment in the manufacturing process of the first embodiment.

Next, as shown in FIG. 15, an n-type impurity (eg, P) is ion-implanted into a part of the epitaxial layer 2 and a p-type impurity (eg, B) is ion-implanted into the other part. These impurities are thermally diffused into epitaxial layer 2 to form n-type well 3n and p-type well 3p. The impurity concentration of the n-type well 3n and the p-type well 3p is, for example, 6 × 10 ¹⁶ atoms / cm ³ . At this time, the n-type impurity and the p-type impurity are ion-implanted at a high accelerating voltage to thereby form the n-type well 3n and the p-type well 3n.
p and p may have a retrograde structure.

Next, as shown in FIG. 16, after forming a gate oxide film 7 in the active region of the epitaxial layer 2, a gate electrode 8 is formed on the gate oxide film 7. The gate electrode 8 is formed on the epitaxial layer 2 on which the gate oxide film 7 is formed.
An n-type polycrystalline silicon film, a W (tungsten) silicide film, and a silicon oxide film 10 are sequentially deposited on the upper surface by CVD, and these films are patterned and formed by dry etching using a photoresist as a mask. The gate electrode 8 is composed of a polycide film in which a W silicide film is laminated on an n-type polycrystalline silicon film. The gate electrode 8 may be formed of a single-layer film of n-type polycrystalline silicon or an n-type polycrystalline silicon film, a three-layer film in which a TiN (titanium nitride film), a W film is laminated, or the like.

Next, as shown in FIG.
N-type impurities (for example, P) are ion-implanted into the p-type wells 3p on both sides of the n-type well to form n-type semiconductor regions 9 and 9.
Forming the n-type MISFET Qn and the p-channel MISFET Q
Form p. After that, C
The silicon oxide film deposited by the VD method is processed by anisotropic etching to form a sidewall spacer 11 on the side wall of the gate electrode 8.

Next, as shown in FIG. 18, an n-channel MISFET Qn and a p-channel MISFET Qp
A silicon oxide film 12 is deposited on the epitaxial layer 2 on which the silicon oxide film 12 is formed by CVD, and a part of the silicon oxide film 12 is opened by dry etching using a photoresist as a mask, thereby forming a p-type MISFET Qp. Connection holes 14a and 14b are formed above the type semiconductor regions 6 and 6, and connection holes 14c and 14d are formed above the n-type semiconductor regions 9 and 9 of the n-channel MISFET Qn.

Next, as shown in FIG.
After depositing an Al alloy film on the silicon oxide film 12 on which the layers .about.14d have been formed by, for example, a sputtering method, the Al alloy film is patterned by dry etching using a photoresist as a mask, thereby forming a p-channel type MISFE.
Wirings 13a and 13b electrically connected to p-type semiconductor regions 6 and 6 of TQp, and n-channel MISFET Q
Wiring 1 electrically connected to n n-type semiconductor regions 9
3c and 13d are formed.

Next, as shown in FIG.
A silicon oxide film or the like is deposited on the upper part of 13d by a CVD method to form an interlayer insulating film 15, and a part of the interlayer insulating film 15 is opened by dry etching using a photoresist as a mask, thereby forming the wiring 13b. A connection hole 17a is formed in the upper part, and a connection hole 17b is formed in the upper part of the wiring 13c.
Subsequently, after an Al alloy film was deposited on the interlayer insulating film 15 by, for example, a sputtering method, the Al alloy film was patterned by dry etching using a photoresist as a mask, thereby being electrically connected to the wiring 13b. A wiring 16b electrically connected to the wiring 16a and the wiring 13c is formed.

Thereafter, the CV is applied to the upper portions of the wirings 16a and 16b.
By depositing a silicon oxide film and a silicon nitride film by the method D to form the passivation film 18, the semiconductor integrated circuit device having the complementary MISFET of the first embodiment is completed.

As described above, the method of manufacturing a semiconductor integrated circuit device according to the present embodiment includes the following steps.

(A) The initial oxygen concentration is 17 to 21 ppma (J
A step of preparing a single-crystal silicon wafer 1 having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b);
1 × 1 of the same conductivity type as the single crystal silicon wafer 1
Impurity less than 0 ¹⁶ atoms / cm ³ is added, and the film thickness is 0.3
A step of growing the epitaxial layer 2 having a thickness of 5 to 5 μm, preferably 0.3 to 3 μm; and (c) a step of thermally oxidizing the surface of the epitaxial layer 2 to form a gate oxide film 7 of the MISFET.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the fine defect density (BMP density) of the silicon wafer 1 after the step (b) is 1 × 10 ⁶ to 1 ×.
It is 10 ⁹ pieces / cm ³ .

In the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the OSDA defect density of the silicon wafer 1 after the step (b) is 6 × 10 ⁶ to 2 × 10 ⁸ / c.
m is ^3.

According to the present embodiment, by using an epitaxial wafer capable of improving the breakdown voltage and film quality of gate oxide film 7 and improving the gettering ability,
The reliability and manufacturing yield of a semiconductor integrated circuit device having a complementary MISFET can be improved.

According to the present embodiment, the epitaxial wafer can be realized at low cost.
The manufacturing cost of a semiconductor integrated circuit device having an ISFET can be reduced.

[0110] In the present embodiment, p ^- p on the surface of the type silicon wafer ^- p grown -type epitaxial layer
^- / p ^- was used epitaxial wafer, n ^- n on the surface of -type silicon wafers ^- n were grown -type epitaxial layer ^- / n ^- can of course may be an epitaxial wafer.

(Embodiment 2) FIG. 21 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of Embodiment 2 of the present invention.

The semiconductor integrated circuit device according to the second embodiment is
An epitaxial wafer composed of a silicon wafer 1 and an epitaxial layer 2 grown on its main surface is provided with a DRAM (D
Dynamic Random Access Memory).
As in the first embodiment, the silicon wafer 1 has a p ^- type with a minute defect density of 1 × 10 ⁶ to 1 × 10 ⁹ / cm ³ and a boron concentration of about 1.5 × 10 ¹⁵ atoms / cm ^3. The epitaxial layer 2 is made of single crystal silicon, and has a boron concentration substantially equal to that of the silicon wafer 1 and a thickness of 0.3 to 3 μm.
^- are composed of type epitaxial layer.

A part of the p-type well 3p formed in the epitaxial layer 2 has an n constituting a DRAM memory cell.
A channel type MISFET Qt for selecting a memory cell is formed, and an n-channel type MI
The SFET Qn is formed. A p-channel MISFET Qp of a peripheral circuit is formed in the n-type well 3n formed in the epitaxial layer 2. MISFET Qt for memory cell selection, n channel type MISFET Q
The n- and p-channel MISFETs Qp are provided on the surface of the epitaxial layer 2 with LOCOS (Local Oxidation of Silicon).
are separated from each other by a field oxide film 28 formed by the (con) method.

The memory cell selecting MISFET Qt and the n-channel MISFET Qn are mainly composed of a p-type well 3p
A gate oxide film 7 formed on the surface of the p-type well 3p, and a gate electrode formed on the gate oxide film 7. 8. p-channel type MI
The SFET Qp mainly includes a pair of p-type semiconductor regions (source region and drain region) formed in the n-type well 3n.
6, a gate oxide film 7 formed on the surface of the n-type well 3n, and a gate electrode 8 formed on the gate oxide film 7. The gate electrode 8 is composed of a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film.

The bit lines BL ₁ and BL ₂ are formed above the memory cell selecting MISFET Qt, and the p-channel MISFET Qp and the n-channel MI
The first layer wiring 13 is provided on each of the SFETs Qn.
e, 13f are formed. Bit lines BL ₁ , BL ₂
The lower electrode 25, the capacitor insulating film 26 and the upper electrode 2
7 is formed, and further thereon, second layer wirings 16c to 16f are formed.

According to the present embodiment, by using an epitaxial wafer capable of improving the breakdown voltage and film quality of gate oxide film 7 and improving the gettering ability,
The reliability and manufacturing yield of the DRAM can be improved.

According to the present embodiment, the above-mentioned epitaxial wafer can be realized at low cost.
Manufacturing cost can be reduced.

(Embodiment 3) FIG. 22 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of Embodiment 3 of the present invention.

The semiconductor integrated circuit device of the third embodiment is
A flash memory is formed on an epitaxial wafer composed of a silicon wafer 1 and an epitaxial layer 2 grown on its main surface. As in the first embodiment, the silicon wafer 1 has a minute defect density of 1 × 10 ⁶ or less.
1 × 10 ⁹ / cm ³ , boron concentration about 1.5 × 10 ¹⁵ atom
consists type single crystal silicon, the epitaxial layer 2 is approximately the same value boron concentration and the silicon wafer 1, thickness p of 0.3~3μm ^{- -} s / cm ³ of p is composed of type epitaxial layer I have.

A part of the p-type well 3p formed in the epitaxial layer 2 includes an n-channel MISFET Qm constituting a memory cell of a flash memory and a transfer MISFET Qm.
An n-channel type MISFET Qtr constituting the ET is formed, and another part is an n-channel type MISFET Qtr of the peripheral circuit.
ISFET Qn is formed. Memory cell is AND
And its drain region is a transfer MISFE.
It is electrically connected to the data line 13i through the source and drain paths of T (n-channel type MISFETQtr).

Further, the n formed in the epitaxial layer 2
In the well 3n, a p-channel MISFET of a peripheral circuit is provided.
Qp is formed. n-channel type MISFETQ
The m and n channel MISFET Qn and the p channel MISFET Qp
They are separated from each other by a field oxide film 28 formed by the COS method.

Memory cell n-channel MISFET Q
m is a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed mainly in the p-type well 3p;
A gate oxide film 7 formed on the surface of the mold well 3p; a gate electrode (floating gate) 8 formed on the gate oxide film 7; a second gate oxide film 29 formed on the gate electrode 8; And a control gate 30 formed on a two-gate oxide film 29. The n-channel MISFET Qn of the peripheral circuit mainly includes a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed in the p-type well 3p and a gate oxide film 7 formed on the surface of the p-type well 3p. And a gate electrode 8 formed on the gate oxide film 7. The p-channel MISFET Qp mainly includes a pair of p-type semiconductor regions (source and drain regions) 6 and 6 formed in an n-type well 3n, a gate oxide film 7 formed on the surface of the n-type well 3n, A gate electrode 8 formed on the gate oxide film 7.

Memory cell n-channel MISFET Q
Above m, first-layer wirings 13g to 13i are formed, and further thereon, a second-layer wiring 16g is formed. Peripheral circuit p-channel MISFET
A first layer wiring 13j is formed above each of the Qp and the n-channel MISFET Qn, and a second layer wiring 16h is further formed thereon.

According to the present embodiment, by using an epitaxial wafer capable of improving the breakdown voltage and film quality of gate oxide film 7 and improving the gettering ability,
The reliability and manufacturing yield of the flash memory can be improved.

According to the present embodiment, the above-mentioned epitaxial wafer can be realized at low cost, so that the manufacturing cost of the flash memory can be reduced.

(Embodiment 4) FIG. 23 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of Embodiment 4 of the present invention.

The semiconductor integrated circuit device of the fourth embodiment is
An epitaxial wafer composed of a silicon wafer 1 and an epitaxial layer 2 grown on the main surface thereof has an SRAM (S
tatic Random Access Memory).
As in the first embodiment, the silicon wafer 1 has a p ^- type with a minute defect density of 1 × 10 ⁶ to 1 × 10 ⁹ / cm ³ and a boron concentration of about 1.5 × 10 ¹⁵ atoms / cm ^3. The epitaxial layer 2 is made of single crystal silicon, and has a boron concentration substantially equal to that of the silicon wafer 1 and a thickness of 0.3 to 3 μm.
^- are composed of type epitaxial layer.

The memory cell of the SRAM is formed in an active region surrounded by a field insulating film 28 on the main surface of the epitaxial layer 2. Of the six MISFETs constituting the memory cell, a pair of n-channel driving MISFETs and a pair of transfer MISFETs are formed in the active region of the p-type well 3p and have a pair of p-channel types. The load MISFET is a drive MISFET
Is formed at the top.

The pair of transfer MISFETs includes an n + type semiconductor region 38 and an n ⁻ type semiconductor region 45 (source region, drain region) formed in the active region of the p-type well 3n.
And a gate oxide film 41 formed of a silicon oxide film formed on the surface of the active region, and a gate electrode 42 formed of polycide formed on the gate oxide film 41. The gate electrode 42 of the transfer MISFET is
It is formed integrally with the word line WL.

The pair of driving MISFETs includes an n + -type semiconductor region 38 and an n ^-- type semiconductor region 37 (source region, drain region) formed in the active region of the p-type well 3n.
And a gate oxide film 35 formed on the surface of the active region.
And a gate electrode 36 made of polycrystalline silicon formed on the gate oxide film 35.

The pair of load MISFETs includes a driving MI
A gate electrode 47 made of polycrystalline silicon formed on the SFET; a gate oxide film 46 formed on the gate electrode 47; and a p-type made of polycrystalline silicon formed on the gate oxide film 46 Semiconductor region 48
(Source region, drain region).

Reference numeral 34 denotes a p-type channel stopper layer, Vcc denotes a power supply line, Vss denotes a GND line, DL denotes a data line,
49 to 51 are first-layer metal wirings.

According to the present embodiment, gate oxide film 3
By using an epitaxial wafer capable of improving the breakdown voltage and film quality of the semiconductor devices 5 and 41 and improving the gettering ability, it is possible to reduce the data retention failure of the SRAM and improve the reliability and the production yield.

According to the present embodiment, the epitaxial wafer can be realized at low cost.
Manufacturing cost can be reduced.

(Embodiment 5) In Embodiment 1,
By using a silicon wafer having an initial oxygen concentration of 17 ppma (in terms of JEIDA) or more, the fine defect density of the silicon wafer after epitaxial growth can be reduced to 1 × 10 ⁶ / cm ^3.
As described above, the initial oxygen concentration was 14 to 21 ppma (JEI
A DA-converted silicon wafer is manufactured according to the method of the first embodiment, and annealing for erasing oxygen donors in the silicon wafer is performed at least at 600 ° C. or more, and at least 30 minutes or more (for example, about 700 ° C. for about 1 hour). 2), the microscopic defect density of the silicon wafer after the epitaxial growth can be made 1 × 10 ⁶ / cm ³ or more.

The annealing at 600 ° C. or more and for 30 minutes or more may be performed in a separate step from the annealing for erasing the oxygen donor. This annealing (annealing for growing the glow-in defect) grows the glow-in defect, thereby preventing the disappearance and dissolution of the glow-in defect in the hydrogen annealing step before forming the epitaxial layer. After that, the fine defect density can be made 1 × 10 ⁶ / cm ³ or more.

The initial oxygen concentration is 14 to 21 ppma (J
After forming an epitaxial layer on a silicon wafer (equivalent to EIDA), in any step of forming a MISFET on this epitaxial layer, at least 600 ° C. or more
In addition, by separately performing annealing for at least 30 minutes or more, the fine defect density of the silicon wafer can be reduced to 1 × 10 ⁶
Pieces / cm ³ or more. At this time, by implanting impurities such as boron or argon (Ar) into the silicon wafer, minute defects are easily deposited.

As described above, the method of manufacturing a semiconductor integrated circuit device according to the present embodiment includes the following steps.

(A) The initial oxygen concentration is 14 to 21 ppma (J
A step of preparing a silicon wafer 1 having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b): (b) preparing the silicon wafer 1 at at least 600 ° C. and at least A step of erasing oxygen donors in the silicon wafer 1 by annealing for 30 minutes or more; (c) 1 × 10 ¹⁶ atoms / cm ^{3 of the} same conductivity type as the silicon wafer 1 on the silicon wafer 1
The step of growing an epitaxial layer 2 having a thickness of 0.3 to 5 μm, preferably 0.3 to 3 μm, to which less than 10% of an impurity is added, and a method of manufacturing a semiconductor integrated circuit device of the present embodiment are as follows: Process.

(A) The initial oxygen concentration is 14 to 21 ppma (J
A step of preparing a silicon wafer 1 having an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ^{3 in} terms of EIDA (b): (b) preparing the silicon wafer 1 at at least 600 ° C. and at least A step of erasing oxygen donors in the silicon wafer 1 by annealing for 30 minutes or more; (c) 1 × 10 ¹⁶ atoms / cm ^{3 of the} same conductivity type as the silicon wafer 1 on the silicon wafer 1
Growing an epitaxial layer 2 having a thickness of 0.3 to 5 μm, preferably 0.3 to 3 μm, to which impurities of less than 0.35 μm are added, and (d) thermally oxidizing the surface of the epitaxial layer 2 to form a gate of the MISFET. Step of forming oxide film 7.

Further, in the method of manufacturing the silicon wafer 1 and the semiconductor integrated circuit device according to the present embodiment, the fine defect density (BMP density) of the silicon wafer 1 after the step (b) is 1 × 10 ⁶ -1. × 10 ⁹ pieces / cm ³ .

In the method of manufacturing the silicon wafer 1 and the semiconductor integrated circuit device according to the present embodiment, the silicon wafer 1 after the step (b) has an OSDA defect density of 6 ×
It is 10 < ⁶ > to 2 * 10 < ⁸ > pieces / cm < ³ >.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

[0144]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, by increasing the oxygen concentration of a silicon wafer, minute defects serving as gettering sites are formed at a high concentration in the silicon wafer.
An epitaxial wafer with improved gettering ability for contaminants such as heavy metals can be realized.

According to the present invention, the breakdown voltage and film quality of the gate oxide film can be improved by forming the gate oxide film of the MISFET on the epitaxial layer formed on the silicon wafer with very few minute defects. That is,
Gate oxide film characteristics (GOI) can be improved.

According to the present invention, the manufacturing cost of the epitaxial wafer can be reduced by lowering the impurity concentration of the silicon wafer and the epitaxial layer. Also,
A step of forming a silicon oxide film on the back surface of the silicon wafer for the purpose of preventing impurities from diffusing out and auto-doping from the back surface of the silicon wafer during the formation of the epitaxial layer becomes unnecessary. Furthermore, since the amount of impurities from the silicon wafer is reduced, the thickness of the epitaxial layer can be reduced, and the fluctuation of the impurity concentration profile of wells and channel regions formed in the epitaxial layer can be prevented.

According to the present invention, the manufacturing cost of the epitaxial wafer can be reduced by forming the epitaxial layer thin. In addition, by forming the epitaxial layer thinly, it is possible to achieve low-temperature growth because the cost is commensurate even at a low growth rate. As a result, since slip-free can be realized, even when applied to a large-diameter wafer of 12 inches or more, it is possible to prevent the warpage of the wafer due to heat during epitaxial growth.

According to the present invention, the use of a silicon wafer having a high initial oxygen concentration eliminates the need for a process for preventing oxygen from dissolving into a high concentration from a quartz crucible during the lifting of the ingot. .

[Brief description of the drawings]

FIGS. 1A to 1G are explanatory diagrams showing a method for manufacturing a silicon wafer according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the epitaxial wafer according to the first embodiment of the present invention;

FIG. 3 is a graph showing a relationship between an initial oxygen concentration and a gate oxide film defect density of a silicon wafer.

FIG. 4 is a graph showing a relationship between a thickness of an epitaxial layer formed on a silicon wafer and a defect density of a gate oxide film.

FIG. 5 is a graph showing a relationship between a breakdown voltage of an oxide film formed on an epitaxial wafer and a cumulative failure rate.

FIG. 6 is a graph showing the relationship between the initial oxygen concentration of a wafer and the density of minute defects (BMD).

FIG. 7 is a graph showing the relationship between the initial oxygen concentration of a wafer and the density of minute defects observed using an OSDA apparatus.

FIG. 8 is a schematic explanatory view showing an optical system of the OSDA device.

FIG. 9 is a graph showing the relationship between the initial oxygen concentration of a wafer and the amount of precipitated oxygen.

FIG. 10 is a graph in which the relationship between the depth from the wafer surface and the oxygen concentration is analyzed by SIMS before and after the heat treatment.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 19 is an essential part cross sectional view showing the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 20 is an essential part cross sectional view illustrating the method of manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon wafer 2 epitaxial layer 2 EW epitaxial wafer 3 n n-type well 3 pp p-type well 4 element isolation groove 4 a groove 6 p-type semiconductor region (source region, drain region) 7 gate oxide film 8 gate electrode 9 n-type semiconductor region (source region) , Drain region) 10 silicon oxide film 11 sidewall spacer 12 silicon oxide film 13a to 13j wiring 14a to 14d connection hole 15 interlayer insulating film 16a to 16h wiring 17a connection hole 17b connection hole 18 passivation film 20 silicon oxide film 21 silicon oxide film Reference Signs List 22 silicon oxide film 23 silicon nitride film 24 silicon oxide film 25 lower electrode 26 capacitance insulating film 27 upper electrode 28 field oxide film 29 second gate oxide film 30 control gate 34 channel stopper layer 35 gate acid Oxide film 36 gate electrode 37 n ⁻ type semiconductor region 38 n ⁺ type semiconductor region 41 gate oxide film 42 gate electrode 45 n ⁻ type semiconductor region 46 gate oxide film 47 gate electrode 48 p type semiconductor region 49 to 51 metal wiring 100 ingot BL ₁ , BL ₂ bit line DL data line C information storage capacitor Qm n-channel MISFET Qn n-channel MISFET Qp p-channel MISFET Qt MISFET for memory cell selection Qtr transfer MISFET Vcc power supply line Vss GND WL word line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115 H01L 27/10 621B 27/108 29/78 301X 21/8242 371 29/78 21/8247 29/788 29/792 // H01L 21/205 (72) Inventor Shogo Kiyota 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Hirofumi Shimizu 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20 In the semiconductor division of Hitachi, Ltd. (72) Inventor Shigeaki Saito 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72) Tomomi Sato Tokyo 5-20-1, Josuihoncho, Kodaira-shi Nippon-cho Super SII Engineering Co., Ltd. (72) Inventor Yasushi Matsuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Semiconductor Co., Ltd. (72) Inventor Yuji Sugino 5--20-1, Kamimizu Honcho, Kodaira-shi, Tokyo Tokyo Co., Ltd. No. 20 No. 1 Semiconductor Division, Hitachi, Ltd. Address: Central Research Laboratory, Hitachi, Ltd. (72) Inventor: Tetsuya Ishihara 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Semiconductor Business Division, Hitachi, Ltd.

Claims (24)

[Claims] 1. A semiconductor wafer in which an epitaxial layer is grown on a main surface of a single-crystal silicon wafer manufactured by a Czochralski method, wherein a fine defect density (BMP density) of the single-crystal silicon wafer after the epitaxial growth is obtained.
Is 1 × 10 ⁶ to 1 × 10 ⁹ pieces / cm ³ . 2. The semiconductor wafer according to claim 1, wherein
A semiconductor wafer, wherein the thickness of the epitaxial layer is 0.3 to 5 μm. 3. The semiconductor wafer according to claim 1, wherein
The impurity concentration of the single crystal silicon wafer is 1 × 10 ¹⁵ at
A semiconductor wafer characterized by being at least oms / cm ^{3 and} less than 3 × 10 ¹⁶ atoms / cm ³ . 4. The semiconductor wafer according to claim 1, wherein
A semiconductor wafer, wherein the single-crystal silicon wafer and the epitaxial layer are doped with the same conductivity type and substantially the same concentration of impurities. 5. The semiconductor wafer according to claim 4, wherein
A semiconductor wafer, wherein the diameter of the single crystal silicon wafer is 12 inches. 6. A semiconductor wafer having an epitaxial layer grown on a main surface of a single crystal silicon wafer manufactured by the Czochralski method, wherein the single crystal silicon wafer after the epitaxial growth has a small defect density measured by an OSDA apparatus. Is 6 × 10 ^{6 to} 2 × 10 ⁸ pieces / cm ³ . 7. A method for producing a semiconductor wafer, comprising the following steps (a) and (b): (a) an initial oxygen concentration of 17 to 21 ppma (in terms of JEIDA) and an impurity concentration of 1 × 10 ^15; atoms / cm ³ or more, 3 × 1
Preparing a single crystal silicon wafer of less than 0 ¹⁶ atoms / cm ³ , (b) adding an impurity of less than 1 × 10 ¹⁶ atoms / cm ^{3 of the} same conductivity type as that of the single crystal silicon wafer on the single crystal silicon wafer Growing the epitaxial layer having a thickness of 0.3 to 5 μm. 8. A method for manufacturing a semiconductor wafer, comprising the following steps (a) to (c): (a) an initial oxygen concentration of 14 to 21 ppma (in terms of JEIDA) and an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more, 3 × 1
Preparing a single crystal silicon wafer of less than 0 ¹⁶ atoms / cm ^3,
A step of erasing oxygen donors in the single crystal silicon wafer by annealing at a temperature of 00 ° C. or higher for at least 30 minutes; (c) the same conductivity type as that of the single crystal silicon wafer on the single crystal silicon wafer At 1
An impurity of less than × 10 ¹⁶ atoms / cm ³ is added, and the film thickness is
Growing a 0.3-5 μm epitaxial layer. 9. The method for manufacturing a semiconductor wafer according to claim 7, wherein the single crystal silicon wafer after the step (b) has a micro defect density (BMP density) of 1 × 10.
^A method for producing a semiconductor wafer, wherein the density is ⁶ to 1 × 10 ⁹ / cm ³ . 10. The method of manufacturing a semiconductor wafer according to claim 7, wherein the single crystal silicon wafer after the step (b) has a minute defect density measured by an OSDA apparatus of 6 × 10 ^6. A method for manufacturing a semiconductor wafer, wherein the number is 2 × 10 ⁸ / cm ³ . 11. A semiconductor integrated circuit device having a gate oxide film of a MISFET formed by thermally oxidizing a surface of an epitaxial layer of the semiconductor wafer according to claim 1. 12. The semiconductor integrated circuit device according to claim 11, wherein an impurity concentration of said epitaxial layer is lower than an impurity concentration of a channel region of said MISFET. 13. The semiconductor integrated circuit device according to claim 11, wherein a second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer,
A semiconductor integrated circuit device, wherein a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. 14. The semiconductor integrated circuit device according to claim 13, wherein a part of said first conductivity type well includes a DRAM.
Is formed, and a complementary MISFET forming a peripheral circuit of the DRAM is formed in another part of the first conductivity type well and the second conductivity type well. A semiconductor integrated circuit device characterized in that: 15. The semiconductor integrated circuit device according to claim 13, wherein a part of said first conductivity type well is a second conductivity type MISFET forming a memory cell of a nonvolatile memory.
A complementary MISFET forming a peripheral circuit of the nonvolatile memory is formed in another part of the first conductivity type well and the second conductivity type well. Integrated circuit device. 16. The semiconductor integrated circuit device according to claim 13, wherein said first conductivity type well and said second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the surface impurity concentration. A semiconductor integrated circuit device comprising: 17. The semiconductor integrated circuit device according to claim 13, wherein said first conductivity type well and said second conductivity type well are separated from each other by an element isolation groove formed in said epitaxial layer. A semiconductor integrated circuit device characterized by the above-mentioned. 18. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (c): (a) an initial oxygen concentration of 17 to 21 ppma (in terms of JEIDA) and an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more, 3 × 1
A step of preparing a single crystal silicon wafer of less than 0 ¹⁶ atoms / cm ³ , (b) adding an impurity of less than 1 × 10 ¹⁶ atoms / cm ^{3 of the} same conductivity type as the single crystal silicon wafer on the single crystal silicon wafer Growing the epitaxial layer having a thickness of 0.3 to 5 μm, and (c) thermally oxidizing the surface of the epitaxial layer to form a gate oxide film of the MISFET. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the single crystal silicon wafer after the step (b) has a minute defect density (BMP density) of 1 × 1.
The method of manufacturing a semiconductor integrated circuit device which is a 0 ⁶ ~1 × 10 ⁹ pieces / cm ^3. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the single crystal silicon wafer after the step (b) has a minute defect density measured by an OSDA apparatus of 6 × 10 ^6. A method of manufacturing a semiconductor integrated circuit device, wherein the number is 2 × 10 ⁸ pieces / cm ³ . 21. A method for manufacturing a semiconductor wafer, comprising the following steps (a) to (d): (a) an initial oxygen concentration of 14 to 21 ppma (in terms of JEIDA) and an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more, 3 × 1
Preparing a single crystal silicon wafer of less than 0 ¹⁶ atoms / cm ^3,
A step of erasing oxygen donors in the single crystal silicon wafer by annealing at a temperature of 00 ° C. or higher for at least 30 minutes; (c) the same conductivity type as that of the single crystal silicon wafer on the single crystal silicon wafer At 1
An impurity of less than × 10 ¹⁶ atoms / cm ³ is added, and the film thickness is
Growing an epitaxial layer of 0.3-5 μm,
(D) MIS by thermally oxidizing the surface of the epitaxial layer
Forming a gate oxide film of the FET; 22. A method for manufacturing a semiconductor wafer, comprising the following steps (a) to (d): (a) an initial oxygen concentration of 14 to 21 ppma (in terms of JEIDA) and an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ or more, 3 × 1
Preparing a single crystal silicon wafer of less than 0 ¹⁶ atoms / cm ³ , (b) adding an impurity of less than 1 × 10 ¹⁶ atoms / cm ^{3 of the} same conductivity type as that of the single crystal silicon wafer on the single crystal silicon wafer Growing the epitaxial layer having a thickness of 0.3 to 5 μm, (c) thermally oxidizing the surface of the epitaxial layer to form a gate oxide film of the MISFET, and (d) forming MISF on the epitaxial layer.
In any step of forming ET, the single-crystal silicon wafer is heated to at least 600 ° C. and at least 30 ° C.
Performing a process of erasing oxygen donors in the single crystal silicon wafer by annealing for at least one minute. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the single crystal silicon wafer after the step (b) has a minute defect density (BMP density) of 1 × 10 ^{6 or} less. A method for manufacturing a semiconductor integrated circuit device, wherein the number is 1 × 10 ⁹ pieces / cm ³ . 24. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the single crystal silicon wafer after the step (b) has a micro defect density measured by an OSDA apparatus of 6 ×. 10 ^{6 to} 2 × 10 ⁸ pieces / cm ³
A method of manufacturing a semiconductor integrated circuit device.