JPH10189766A - Semiconductor integrated circuit device and fabrication thereof, semiconductor wafer and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the fabrication cost of MIS device employing an epitaxial wafer. SOLUTION: Impurity ions are implanted with high energy into the vicinity of interface between an epitaxial layer 2 and a silicon substrate 1 to form an ion implantation layer 5. The ion implantation layer 5 serves as a barrier wall for prevent a latent flaw or a micro defect on the surface of the silicon substrate 1 from having a significant effect on the epitaxial layer 2. A structural defect in the ion implantation layer 5 caused through amorphous process serves as a gettering layer for capturing contaminants, e.g. heavy metals, intruding into the substrate in the way of the process. Furthermore, the heavily doped low resistance ion implantation layer 5 contributes to enhancement of latch-up resistance of a CMOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to an epitaxial layer grown on a main surface of a single crystal silicon (Si) wafer.
MISFET (Metal Insulator Se) in (epitaxial layer)
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device that forms a semiconductor field effect transistor.

[0002]

2. Description of the Related Art In recent years, in the field of MIS devices in which an integrated circuit is constituted by MISFETs, a complementary MISFE has been developed.
An epitaxial layer is grown on the main surface of a single crystal silicon wafer (CZ wafer) manufactured by the CZ (Czochralski) method in order to improve the latch-up resistance of T and to improve the quality of the gate insulating film. The introduction of so-called epitaxial wafers has been advanced.

[0003] Further, in the CZ wafer, there is a concern that a gate breakdown voltage defect and an increase in leak current are caused by crystal defects such as vacancies mixed in during ingot pulling.
DRAM (Dynamic Random Ac
In the case of process memory, the use of an epitaxial wafer can be expected to improve the production yield by reducing the leak current.

In the epitaxial wafer described in Japanese Patent Application Laid-Open No. 1-260832, an impurity is introduced into a main surface of a CZ wafer, and then an epitaxial layer is grown on the main surface. Is diffused upward to form a diffusion layer.

[0005]

As an epitaxial wafer for a MIS device, a low-resistance CZ wafer doped with a high concentration of impurities is used in order to improve latch-up resistance. Further, in the epitaxial wafer, the oxygen precipitation in the wafer is suppressed by the heat treatment during the epitaxial growth, and the gettering ability for capturing a contaminant such as heavy metal is reduced. It is necessary to add a high concentration of impurities to the wafer.

However, CZ containing a high concentration of impurities
When an epitaxial layer is formed on the main surface of the wafer, CZ may be formed during the epitaxial growth or during the heat treatment during the process.
Impurities in the wafer may diffuse into the epitaxial layer, fluctuating the impurity profile of the epitaxial layer and deteriorating device characteristics.

On the surface of the CZ wafer, a COP (Crystal Originated Pi) generated during lifting of the ingot is placed.
There are minute defects such as t) and latent scratches generated in the polishing step and the like, which cause dislocations to be formed inside the epitaxial layer. Therefore, when the thickness of the epitaxial layer is small, this transition reaches the surface of the epitaxial layer, and adversely affects the characteristics of the MISFET.

Therefore, the epitaxial wafer for the MIS device must be grown thick (for example, about 8 to 10 .mu.m) in order to avoid the above-mentioned problem, so that the manufacturing cost is inevitably increased. . Further, a CZ wafer having a low resistance (for example, a specific resistance of about 0.1 Ωcm) to which an impurity is added at a high concentration,
The manufacturing cost is higher than that of a normal CZ wafer having a specific resistance of about 0.5 to 50 Ωcm.

Therefore, in manufacturing a MIS device using an epitaxial wafer, the effect of reducing the manufacturing cost due to the improvement of the manufacturing yield by introducing the epitaxial wafer is not offset by the manufacturing cost of the epitaxial wafer. As described above, it is essential to reduce the manufacturing cost of an epitaxial wafer as much as possible.

An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a MIS device using an epitaxial wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) preparing a silicon substrate having an epitaxial layer formed on a main surface thereof; and (b) forming a silicon substrate and an epitaxial layer. Implanting impurities so as to reach the vicinity of the interface, and forming an ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer near the interface.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the conductivity type of the ion-implanted layer is the same as the conductivity type of the silicon substrate.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the ion implantation of the impurity is performed over the entire main surface of the silicon substrate having a uniform impurity concentration.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the epitaxial layer has a thickness of about 0.3 to 5 μm.
It is.

(5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a first conductivity type impurity is ion-implanted into the first region of the silicon substrate to form a first conductivity type ion-implanted layer. A second conductivity type impurity is ion-implanted into the two regions to form a second conductivity type ion-implanted layer.

(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the impurity is boron, argon, carbon, phosphorus,
Contains any one of arsenic.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the specific resistance of the silicon substrate is about 0.5 to 50 Ωcm.
It is.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the ion implantation is performed so as to relieve a local stress existing near an interface between the silicon substrate and the epitaxial layer.

(9) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the ion implantation of the impurity is performed such that the vicinity of the interface between the silicon substrate and the epitaxial layer becomes amorphous.

(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the ion-implanted layer functions as a buffer region.

(11) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the ion-implanted layer is used as a gettering layer.

(12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a MISFET is formed in the epitaxial layer.

(13) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) a step of preparing a silicon substrate having an epitaxial layer formed on a main surface; and (b) ion implantation of impurities into the entire surface or a part thereof so as to reach near the interface between the silicon substrate and the epitaxial layer. Forming a first conductivity type ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer in the vicinity of the interface; and (c) forming a part of the first conductivity-type ion-implanted layer with the conductivity type. Forming a second conductivity type ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer by ion-implanting an impurity which inverts the above, and (d) forming a semiconductor element in the epitaxial layer.

(14) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) a step of preparing a silicon substrate having an epitaxial layer formed on a main surface; and (b) an impurity containing at least carbon or oxygen so as to reach near an interface between the silicon substrate and the epitaxial layer. Ion-implanting to form an ion-implanted layer constituting a gettering site near the interface; and (c) forming a semiconductor element on the epitaxial layer.

(15) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the semiconductor element is a MISFET.

(16) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) a step of preparing a silicon substrate having an epitaxial layer formed on a main surface; and (b) ion implantation of impurities to reach near an interface between the silicon substrate and the epitaxial layer. Forming an ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer in the vicinity; (c) ion-implanting a first conductivity type impurity into a first region of the epitaxial layer to form an ion-implanted layer in the first region; Forming a first conductivity type buried layer above the ion-implanted layer; (d) ion-implanting a second conductivity-type impurity into a second region of the epitaxial layer to form an ion-implanted layer in the second region; Forming a second conductivity type buried layer on top,
(E) forming a MISFET on the epitaxial layer;

(17) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the first conductivity type buried layer and the second conductivity type buried layer are in contact with a bottom of the element isolation region below the element isolation region. It is formed as follows.

(18) The semiconductor integrated circuit device according to the present invention
A MISFET is formed on the epitaxial layer grown on the main surface of the silicon substrate, the thickness of the epitaxial layer is about 0.3 to 5 μm, and the silicon layer is formed near the interface between the silicon substrate and the epitaxial layer. An ion-implanted layer having a higher impurity concentration than the substrate and the epitaxial layer is formed.

(19) The semiconductor integrated circuit device of the present invention
The conductivity type of the ion implantation layer is the same as the conductivity type of the silicon substrate.

(20) The semiconductor integrated circuit device according to the present invention
The ion implanted layer acts as a buffer region.

(21) The semiconductor integrated circuit device of the present invention
The ion implantation layer is used as a gettering layer.

(22) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer, and a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. Have been.

(23) The semiconductor integrated circuit device according to the present invention
The first conductivity type well and the second conductivity type well are separated from each other by an element isolation groove formed in the epitaxial layer.

(24) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET forming a memory cell of the DRAM is formed in a part of the first conductivity type well, and another part of the first conductivity type well and the second conductivity type well are Complementary MIS constituting peripheral circuits of the DRAM
An FET is formed.

(25) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET forming a memory cell of the nonvolatile memory is formed in a part of the first conductivity type well, and is connected to another part of the first conductivity type well and the second conductivity type well. Are formed with complementary MISFETs constituting a peripheral circuit of the nonvolatile memory.

(26) The semiconductor integrated circuit device of the present invention
The first conductivity type well and the second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the impurity concentration on the surface.

(27) The semiconductor integrated circuit device of the present invention
The ion implanted layer formed below the first conductivity type well constitutes a second conductivity type buried layer, and the ion implanted layer formed below the second conductivity type well is a first conductivity type buried layer. Is composed.

(28) The method of manufacturing a semiconductor wafer according to the present invention includes the following steps.

(A) forming a thermal oxide film on the main surface of the silicon wafer and then etching and removing the thermal oxide film; (b) a main surface of the silicon wafer from which the thermal oxide film has been removed Forming an epitaxial layer thereon,
(C) forming a semiconductor element on the epitaxial layer;

(29) In the method of manufacturing a semiconductor wafer according to the present invention, the temperature for forming the thermal oxide film is 1000 ° C. or less.

(30) In the method of manufacturing a semiconductor wafer according to the present invention, the thickness of the epitaxial layer is about 0.3 to 5 μm.

(31) In the method of manufacturing a semiconductor wafer according to the present invention, the thermal oxide film is formed at a temperature at which oxygen taken in at the time of pulling up the ingot using the Czochralski method remains near the surface of the silicon wafer.

(32) In the method of manufacturing a semiconductor wafer according to the present invention, the thermal oxide film has a thickness of 10 nm or more, and latent scratches and minute defects present on the surface of the silicon wafer are removed together with the thermal oxide film by the etching. Remove.

(33) In the semiconductor wafer of the present invention, an epitaxial layer having a thickness of about 0.3 to 5 μm is formed on the main surface of the silicon wafer, and the epitaxial layer is formed near the interface between the silicon wafer and the epitaxial layer. An ion implanted layer having a higher impurity concentration than the silicon wafer and the epitaxial layer is formed.

[0050]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a CZ wafer according to Embodiment 1 will be briefly described. First, as shown in FIG. 1A, an ingot 100 of single crystal silicon is manufactured by using the Czochralski (CZ) method. At this time, the initial oxygen concentration of the ingot 100 was 17 ppma (JEIDA
(Conversion) or more. However, if the amount of oxygen is excessive, the crystal strength is reduced, and the wafer is likely to be warped during the heat treatment during the process. Therefore, the upper limit of the oxygen concentration is set to 21 ppma (in JEIDA conversion). The setting of the oxygen concentration is performed by controlling, for example, the amount of dissolution from the quartz crucible, the convection of the molten silicon, and the amount of evaporation from the surface. In order to set the impurity concentration (that is, the specific resistance) of the CZ wafer to a value described later, the ingot 1
For example, boron (B) is added as a dopant when pulling up 00.

Next, as shown in FIG. 2B, a part of the ingot 100 is cut to leave only the ingot 100 in a region where the oxygen concentration and the impurity concentration are within desired ranges. As shown in c), the outer periphery of the ingot 100 is ground and the orientation flat (or orientation notch) is processed. Next, as shown in FIG. 2D, after the ingot 100 is sliced thinly to form the CZ wafer 1a, the outer peripheral portion of the CZ wafer 1a is chamfered in order to prevent chipping.

Next, as shown in FIG. 5E, after lapping both sides of the CZ wafer 1a to adjust the thickness and flatness, an acid or an acid is removed to remove mechanical strain caused by the lapping. Both surfaces of the CZ wafer 1a are etched using an alkaline solution.

Next, as shown in FIG. 4F, the CZ wafer 1a is annealed at, for example, about 600 ° C. for about 30 minutes in a nitrogen atmosphere, so that an oxygen donor generated by oxygen mixed in during the lifting of the ingot 100 is formed. Is performed. This is because 45%
This is because oxygen is turned into a donor around 0 ° C., and the resistivity in the wafer surface greatly changes, so that a heat treatment for erasing the oxygen donor is required to obtain a desired resistivity.

Next, as shown in FIG. 2G, the surface of the CZ wafer 1a on which the epitaxial layer is formed is mirror-polished to obtain a p ^- type CZ wafer 1 having a (100) orientation plane. Note that if an n-type impurity (for example, phosphorus (P)) is added as a dopant when the ingot 100 is pulled up, an n ⁻ -type CZ wafer can be obtained.

FIG. 2 is a cross-sectional view of a principal part showing the semiconductor integrated circuit device of the first embodiment.

The semiconductor integrated circuit device of the first embodiment is
An epitaxial substrate composed of a silicon substrate (CZ substrate) 1 and an epitaxial layer 2 grown on its main surface has a C
A MOS (Complementary Metal Oxide Semiconductor) circuit is formed. The silicon substrate 1 is made of p-type single crystal silicon manufactured by the above-described method, and has a specific resistance of, for example, about 0.5 to 50 Ωcm and an impurity concentration of 5 × 10 ^14.
１1 × 10 ¹⁶ atms / cm ³ . This silicon substrate 1 is doped with about 10 ¹⁶ atms / cm ³ of boron (B) as an impurity when the ingot (100) is pulled up.

The impurity (boron) concentration of the silicon substrate 1 is set to a value lower than the above-mentioned concentration as long as the impurity concentration profile of the element formation region of the epitaxial layer 2 does not fluctuate due to the impurities diffused out of the CZ wafer during the formation of the epitaxial layer. May be higher. However, in order to eliminate the need for a step of forming an insulating film on the back surface of the epitaxial substrate to prevent out-diffusion of impurities, the impurity concentration of the epitaxial layer 2 must be significantly increased, for example, to the order of 10 ¹⁵ atms / cm ^3. It is appropriate that the concentration is not exceeded. Specifically, the impurity (boron) concentration of the silicon substrate 1 is determined by the channel concentration (for example, 1 × 10 ¹⁷ atms) of a MISFET described later.
/ cm ³ ) which is about one digit lower than 3 × 10 ¹⁶ atms / cm ³ (specific resistance = approximately 0.5Ωcm).
Any range may be used as long as it does not affect the impurity concentration (for example, about 6 × 10 ¹⁷ atms / cm ³ ) of the well which determines the device characteristics.

The epitaxial layer 2 formed on the silicon substrate 1 has a small thickness of about 3 to 5 μm or less in order to reduce the manufacturing cost of the epitaxial substrate. Since an element is formed on the epitaxial layer 2, the lower limit of the film thickness must be at least about 0.3 μm or more, preferably about 1 μm or more. When the thickness of the epitaxial layer 2 is 0.3 μm or less, the gate breakdown voltage is reduced, that is, the defect density of the gate oxide film is increased. This epitaxial layer 2 contains about 1
0 ¹⁵ atms / cm ³ of boron is added.

In order to shorten the time for growing the epitaxial layer 2 and reduce the manufacturing cost of the epitaxial substrate, it is appropriate to set the upper limit of the thickness of the epitaxial layer 2 to 5 to 7 μm or less, preferably 4 μm or less. is there. On the other hand, the lower limit of the thickness of the epitaxial layer 2 may be determined in consideration of the amount of shaving due to thermal oxidation up to the gate oxide film forming step, heat treatment conditions, and the like. It is appropriate to do. The impurity (boron) concentration of the epitaxial layer 2 is set to be substantially the same as or lower than that of the silicon substrate 1.
MISFET channel concentration (for example, 1 × 10 ¹⁷ atms / c
m ³ ), that is, one order of magnitude lower, that is, 3 × 10 ¹⁶ atms
There is no problem if it is less than / cm ³ . It should be noted that reference symbol I in FIG.
Reference numeral ₁₂ denotes an interface between the silicon substrate 1 and the epitaxial layer 2.

FIG. 3 is a graph showing the relationship between the initial oxygen concentration [Oi] of the silicon substrate 1 and the defect density of the gate oxide film. The horizontal axis indicates the initial oxygen concentration (ppma (JEIDA conversion)), and the vertical axis indicates the gate oxide film defect density (relative value). Assuming that the gate oxide film defect density at an initial oxygen concentration of 18 ppma (in JEIDA) is 1, the gate oxide film defect density decreases as the oxygen concentration decreases. Thus, in the case of the silicon substrate 1, in order to reduce the defect density of the gate oxide film formed on the surface, it is necessary to set the initial oxygen concentration to 17 ppma (JEIDA conversion) or less.

FIG. 4 is a graph showing the relationship between the thickness of the epitaxial layer 2 and the defect density of the gate oxide film. The horizontal axis indicates the thickness (μm) of the epitaxial layer 2 and the vertical axis indicates the gate oxide defect density (relative value with respect to the silicon substrate). The initial oxygen concentration of the epitaxial layer 2 is 15, 16.5, 1
It is 9, 20 ppma (in JEIDA conversion). From this graph, it can be seen that the gate oxide defect density of the epitaxial layer 2 does not depend on the initial oxygen concentration of the silicon substrate 1 and decreases as the thickness of the epitaxial layer 2 increases.
It can be seen that when the thickness is more than μm, the thickness becomes about 1/30 of the silicon substrate 1 regardless of the initial oxygen concentration. That is, in the case of an epitaxial substrate, the initial oxygen concentration is 17 ppma (J
Even if it is higher than (EIDA conversion), the gate oxide film defect density does not increase. Therefore, it is appropriate that the thickness of the epitaxial layer 2 is at least 0.3 μm or more.

In FIG. 4, the epitaxial layer 2
When the film thickness is 0.3 μm or more, there is almost no variation in the defect density of the gate oxide film with respect to the initial oxygen concentration, and they appear to overlap. That is, the thickness of the epitaxial layer 2 is 0.3 μm
The above epitaxial substrate can improve the gate oxide film property (Gate Oxide Integrity: GOI) regardless of the initial oxygen concentration.

From the above, the present inventors have found that the initial oxygen concentration of the epitaxial substrate is 17 ppma (JEI
(Equivalent to DA conversion) or higher, the epitaxial layer 2
It has been found that the breakdown voltage of the gate oxide film on the surface does not deteriorate. Further, by using a silicon oxide film formed by thermally oxidizing the epitaxial layer 2 as a gate oxide film of the MISFET, a MISFET with a small gate oxide film defect density can be formed.

The epitaxial layer 2 has an n-type well 3
An n-type and a p-type well 3p are formed. Although not particularly limited, each of the n-type well 3n and the p-type well 3p is a retrograde in which the internal impurity concentration is higher than the surface impurity concentration in order to improve the latch-up resistance of the CMOSFET (complementary MISFET). It has a structure and is isolated from each other via an element isolation groove 4 formed in the epitaxial layer 2.

The silicon substrate 1 and the epitaxial layer 2
An ion-implanted layer 5 having a higher impurity concentration than the silicon substrate 1 and the epitaxial layer 2 is formed near the interface with the silicon substrate 1, that is, in a region extending from the uppermost portion of the silicon substrate 1 to the lowermost portion of the epitaxial layer 2. About 10 ¹⁸ atms / cm ³ of boron (B) is introduced into the ion-implanted layer 5 as an impurity. The ion-implanted layer 5 is formed on the entire main surface of the silicon substrate 1, that is, on the entire interface between the silicon substrate 1 and the epitaxial layer 2. That is, the ion-implanted layer 5 is formed by ion implantation without mask.

In the n-type well 3n formed in the epitaxial layer 2, a p-channel type MISFET Qp is formed.
An n-channel MISFET Qn is formed in the p-type well 3p. The p-channel type MISFET Qp mainly includes a pair of p-type semiconductor regions (source and drain regions) 6 and 6 formed in an n-type well 3n and an n-type well 3
A gate oxide film 7 formed on the surface of n and a gate electrode 8 formed on the gate oxide film 7 are formed. The n-channel MISFET Qn mainly includes a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed in the p-type well 3p and a gate oxide film 7 formed on the surface of the p-type well 3p. And a gate electrode 8 formed on the gate oxide film 7. The gate electrode 8 is composed of, for example, a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film. For example, a silicon oxide film 10 is formed on the gate electrode 8, and a sidewall spacer 11 made of a silicon oxide film is formed on a side wall. The silicon oxide film 10 and the side wall spacer 11 are formed by a gate electrode 8 and a wiring (1) formed thereover.
3a to 13d).

First-layer wirings 13 a to 13 d are formed above the p-channel MISFET Qp and the n-channel MISFET Qn via the silicon oxide film 12. The wiring 13a is connected to a p-channel MISFET Qp through a connection hole 14a formed in the silicon oxide film 12.
Is electrically connected to one of the p-type semiconductor regions 6,
3b is a p-channel type MISFE through the connection hole 14b.
It is electrically connected to the other p-type semiconductor region 6 of TQp. The wiring 13c is electrically connected to one n-type semiconductor region 9 of the n-channel MISFET Qn through the connection hole 14c, and the wiring 13d is connected to the other n-type semiconductor region 9 of the n-channel MISFET Qn through the connection hole 14d. It is electrically connected. Wirings 13a to 13d
Is made of, for example, an Al (aluminum) alloy to which Si (silicon) and Cu (copper) are added.

Second layer wirings 16a and 16b are formed above the first layer wirings 13a to 13d via an interlayer insulating film 15 made of a silicon oxide film or the like. The wiring 16a has a connection hole 17a formed in the interlayer insulating film 15.
The wiring 16b is electrically connected to the first layer wiring 13b through the connection hole 17b.
c and is electrically connected. The wirings 16a and 16b are
For example, it is composed of an Al alloy to which Si and Cu are added.

A passivation film 18 composed of a stacked film of a silicon oxide (SiO ₂ ) film and a silicon nitride (Si ₃ N ₄ ) film is formed on the wirings 16a and 16b.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 5, a p-type silicon substrate 1 manufactured by the method shown in FIG. 1 and having a specific resistance of about 0.5 to 50 Ωcm is prepared. An appropriate amount of oxygen is taken into the silicon substrate 1 when the single crystal is pulled.
Next, a thermal oxidation treatment at about 900 ° C. is performed to form a silicon oxide film 20 on the surface. This thermal oxidation treatment may be performed in a wet or dry oxygen atmosphere, but the thickness of the silicon oxide film 20 is preferably 10 nm or more. This thermal oxidation treatment is performed for 1000 to 1 to form a DZ (denuded) layer and remove contamination.
Since the heat treatment is performed at a temperature of 1000 ° C. or less (for example, about 900 ° C.), which is lower than the heat treatment of 100 ° C., even when a large-diameter substrate (wafer) is used, the substrate (wafer) due to non-uniform in-plane temperature is used. Warpage and occurrence of transition due to thermal stress can be suppressed. In addition, even if this thermal oxidation treatment is performed,
Micro defects such as COP and oxygen remain in the vicinity and inside of the surface of the silicon substrate 1.

FIG. 6 is a graph showing the relationship between the initial oxygen concentration and the amount of precipitated oxygen. The sample substrates are a silicon substrate and an epitaxial substrate. In order to promote oxygen precipitation, annealing for oxygen precipitation (800 ° C.
(Time + 1000 ° C., 16 hours). The amount of oxygen precipitation was determined by a Fourier transform infrared spectrophotometer as the difference between the oxygen concentrations before and after the heat treatment. As shown in the drawing, the amount of precipitated oxygen increases with an increase in the initial oxygen concentration in the silicon substrate, but slightly in the epitaxial substrate.

This graph also shows the amount of precipitated oxygen on the silicon substrate that has been subjected to the heat treatment up to the preheating (preheating for removing the natural oxide film) in the epitaxial growth step. It can be seen that oxygen precipitation is suppressed by heat treatment up to preheating. This is presumably because the high-temperature heat treatment up to the preheating dissolves and eliminates glow-in defects and small-diameter oxygen precipitate nuclei in the silicon substrate, thereby suppressing oxygen precipitation. The glow-in defect and the oxygen precipitation nucleus act as gettering sites for heavy metal contamination, and thus the epitaxial substrate may not be able to obtain sufficient gettering ability for heavy metal contamination.

In the present embodiment, the growth of glow-in defects and oxygen precipitation in silicon substrate 1 is promoted by this heat treatment, so that the silicon substrate is subjected to preheating in the epitaxial growth step (preheating for removing a natural oxide film). 1 can be prevented from dissolving the glow-in defect and oxygen precipitation nuclei, and the diameter of the oxygen precipitation nuclei can be increased.
Thereby, oxygen precipitation is promoted by the heat treatment, so that the gettering effect is improved even in a p / p epitaxial substrate having a low impurity concentration. That is, according to the present embodiment, an epitaxial substrate having improved gate oxide film characteristics (GOI) and improved gettering effect against heavy metal contamination can be realized at low cost.

Next, as shown in FIG.
By etching the surface of the silicon substrate 1, latent scratches, minute defects, contaminants and the like existing on the surface of the silicon substrate 1 are removed together with the silicon oxide film 20. This etching may be either wet or dry. Steps so far (formation of silicon oxide film 20 and removal by etching)
The effect of latent scratches, minute defects, contaminants, and the like on the surface of the silicon substrate 1 on the surface and inside of the epitaxial layer 2, that is, the transition caused by the latent scratches, minute defects, etc. It is possible to reduce the internal trouble. Further, the above-mentioned latent scratches, minute defects, contaminants and the like can be removed to some extent only by wet etching of the surface of the silicon substrate 1 without forming the silicon oxide film 20. In this case, latent scratches, minute defects, contaminants, and the like on the surface of the silicon substrate 1 that cannot be completely removed by simply wet etching the surface of the silicon substrate 1 can also be removed.

Next, as shown in FIG.
For example, the silicon substrate 1 is put into an epitaxial growth furnace, and annealing is performed in a hydrogen atmosphere at about 950 to 1200 ° C. for about 10 minutes to remove a natural oxide film on the surface. Then, the temperature in the furnace is lower than the annealing temperature. Temperature (about 900
.About.1100 ° C.) and a thickness of about 0.3 to 5 μm on the silicon substrate 1 by a thermal CVD method using a reaction gas composed of, for example, SiHCl ₃ + H ₂ or SiH ₄ + H ₂ + B ₂ H _6.
A p-type epitaxial layer 2 having an m and B (boron) concentration of about 10 ¹⁵ atms / cm ³ is grown.

In this embodiment, a silicon substrate having a low resistance (for example, specific resistance of about 0.1 Ωcm) to which impurities are added at a high concentration is not used.
Even if the thickness is reduced to μm or less, the amount of impurities diffused from the silicon substrate 1 to the epitaxial layer 2 during epitaxial growth is extremely small.

Further, in this embodiment, since the epitaxial layer 2 is formed with a small thickness without using an expensive low-resistance silicon substrate to which impurities are added at a high concentration, a thick film is formed on the low-resistance silicon substrate. (For example, about 8 to 10 μm)
Manufacturing cost can be greatly reduced as compared with an epitaxial substrate having an epitaxial layer formed thereon.

The reaction gas used for forming the epitaxial layer 2 is not limited to the one described above. Instead of SiHCl ₃ or SiH ₄ (monosilane), for example, SiH ₂ C
By using a reaction gas containing a silane-based gas containing Cl (chlorine), such as l ₂ , SiH ₃ Cl, or SiCl ₄ , fine steps on the surface of the silicon substrate 1 can be reduced. Prior to the step of forming the epitaxial layer 2, the surface of the silicon substrate 1 can be made fine by heat-treating the silicon substrate 1 in a non-oxidizing gas (inert gas) atmosphere such as hydrogen or Ar (argon). Can be reduced. Thus, epitaxial layer 2 is formed on silicon substrate 1 having a uniform impurity concentration on the main surface.

Next, as shown in FIG. 9, after the surface of the epitaxial layer 2 is thermally oxidized to form a thin silicon oxide film 21 on the surface, the silicon oxide film 21 is brought near the interface between the epitaxial layer 2 and the silicon substrate 1. By ion-implanting boron with high energy, an ion-implanted layer 5 is formed near this interface. As described above, the impurity (B) concentration of the ion-implanted layer 5 is higher than those of the silicon substrate 1 and the epitaxial layer 2, and is about 10 ¹⁸ at.
ms / cm ³ . Note that if the dose of the impurity is too large, crystal defects may occur. Therefore, the impurity concentration is preferably at most 10 ¹⁹ atms / cm ³ . The ion-implanted layer 5 is formed on the entire main surface of the silicon substrate 1 having a uniform impurity concentration on the main surface, that is, on the entire interface between the silicon substrate 1 and the epitaxial layer 2.

FIG. 10 shows an impurity concentration profile along the depth direction of the epitaxial substrate on which the ion-implanted layer 5 is formed. The ion-implanted layer 5 is formed in the silicon substrate 1 and the epitaxial layer 2 and has a maximum peak impurity concentration between the epitaxial layer 2 and the silicon substrate 1.
Is formed by ion-implanting impurities with high energy such as to reach the vicinity of the interface with the substrate. The dose of the impurity is set so that the vicinity of the interface between the silicon substrate 1 and the epitaxial layer 2 becomes amorphous. Thereby, since the silicon substrate 1 and the epitaxial layer 2 near the interface are made amorphous, local stress existing near the interface is reduced. That is, local stress caused by disorder such as mismatch at the atomic level is reduced.

That is, in the first embodiment in which the upper limit of the thickness of the epitaxial layer 2 is reduced to 7 μm or less, the amorphous ion-implanted layer 5 has the above-described latent damage on the surface of the silicon substrate 1 and its vicinity. , Acts as a buffer region for reducing the influence of micro defects, contaminants, etc. on the surface and inside of the epitaxial layer 2, and in the heat treatment step during the process (such as formation of a field oxide film for element isolation described later). Prevents the formation of metastases caused by local stresses inside the device.

The structural defects of the ion-implanted layer 5 caused by the amorphization also act as gettering layers for capturing contaminants such as heavy metals that enter the substrate during the process. In particular, the ion-implanted layer 5 containing argon (Ar), which is an inert gas, and the ion-implanted layer 5 containing boron (B) having a high ability to capture heavy metals such as iron (Fe) have a high gettering ability. Demonstrate. That is, by forming a gettering layer at a shallow interface whose depth from the main surface of the epitaxial layer 2 is 7 μm or less, a high gettering ability can be obtained, and the silicon substrate 1
By forming the ion-implanted layer 5 over the entire surface, the gettering ability is further improved.

Further, a low-resistance ion-implanted layer 5 containing a high-concentration impurity (for example, boron (B)) of the same conductivity type as the silicon substrate 1 is formed on the entire surface of the silicon substrate 1. Since the resistance can be reduced, it contributes to the improvement of the latch-up resistance of the CMOSFET as well as the low resistance silicon substrate to which the impurity is added at a high concentration.

As described above, by forming the above-described ion-implanted layer 5 near the interface between the epitaxial layer 2 and the silicon substrate 1, a thick film is formed on the low-resistance silicon substrate doped with impurities at a high concentration. It is possible to manufacture at low cost an epitaxial substrate having the same characteristics as the epitaxial substrate having the epitaxial layer formed thereon.

The impurities for forming the ion-implanted layer 5 are not limited to boron (B) or argon (Ar). Instead of the p-type impurity (B), an n-type impurity such as P (phosphorus), As (arsenic), or Sb (antimony) may be used. Further, C (carbon), Si, F (fluorine), O
(Oxygen), N (nitrogen) or the like may be added.

Next, after the silicon oxide film 21 on the surface of the epitaxial layer 2 is removed by etching,
As shown in FIG.
A silicon oxide film 22 and a silicon nitride film 23 are deposited by a mical vapor deposition method, and then the silicon nitride film 23 is patterned using a photoresist as a mask. Layer 2 is etched sequentially to form groove 4
a is formed. Subsequently, a thermal oxidation treatment at 900 to 1150 ° C. is performed to form a silicon oxide film (not shown) on the inner wall of the groove 4a.

Next, as shown in FIG. 12, a silicon oxide film 24 deposited by CVD on the epitaxial layer 2 is formed.
Is flattened by etch back or chemical mechanical polishing, and is left inside the groove 4a to form the element isolation groove 4. Subsequently, a heat treatment of about 1000 ° C.
The silicon oxide film 24 inside is densified (densify:
Baking). These heat treatments and thermal oxidation treatments belong to the highest temperature heat treatment in the manufacturing process of the first embodiment. By the heat treatment in the subsequent steps including this heat treatment, the ion-implanted layer 5 which has been made amorphous becomes a single crystal layer having no mismatch.

Next, as shown in FIG. 13, an n-type impurity (P or As) is ion-implanted into a part of the epitaxial layer 2 and a p-type impurity (B) is ion-implanted into another part. These impurities are thermally diffused into epitaxial layer 2 to form n-type well 3n and p-type well 3p. At this time, an n-type impurity and a p-type impurity are ion-implanted at a high acceleration voltage, and the n-type well 3n and the p-type well 3n are implanted.
p and have a retrograde structure. FIG. 14 (b)
Indicates a region where the p-type well 3p is formed (X in FIG.
-Epitaxial substrate 2 in the region along the line X ')
7 is an impurity concentration profile of FIG. As shown, the n-type well 3n also has the same impurity concentration profile as the p-type well 3p.

Next, as shown in FIG. 15, after a gate oxide film 7 is formed in the active region of the epitaxial layer 2, a gate electrode 8 is formed on the gate oxide film 7. The gate electrode 8 is formed on the epitaxial layer 2 on which the gate oxide film 7 is formed.
An n-type polycrystalline silicon film, a W (tungsten) silicide (silicide) film, and a silicon oxide film 10 are sequentially deposited on the upper surface by CVD, and these films are formed by patterning by dry etching using a photoresist as a mask. . The gate electrode 8 has W on the n-type polycrystalline silicon film.
It is composed of a polycide film in which a silicide film is laminated. Above the gate electrode 8, a single-layer film of n-type polycrystalline silicon or a three-layer film in which an n-type polycrystalline silicon film, TiN (titanium nitride film), and a W film are stacked may be used.

Next, as shown in FIG. 16, the gate electrode 8
N-type impurities (for example, P) are ion-implanted into the p-type wells 3p on both sides of the n-type well to form n-type semiconductor regions 9 and 9.
Forming the n-type MISFET Qn and the p-channel MISFET Q
Form p. After that, C
The silicon oxide film deposited by the VD method is processed by anisotropic etching to form a sidewall spacer 11 on the side wall of the gate electrode 8.

Next, as shown in FIG. 17, the n-channel MISFET Qn and the p-channel MISFET Qp
A silicon oxide film 12 is deposited on the epitaxial layer 2 on which the silicon oxide film 12 is formed by CVD, and a part of the silicon oxide film 12 is opened by dry etching using a photoresist as a mask, thereby forming a p-type MISFET Qp. Connection holes 14a and 14b are formed above the type semiconductor regions 6 and 6, and connection holes 14c and 14d are formed above the n-type semiconductor regions 9 and 9 of the n-channel MISFET Qn.

Next, as shown in FIG. 18, the connection holes 14a
After depositing an Al alloy film on the silicon oxide film 12 on which the layers .about.14d have been formed by, for example, a sputtering method, the Al alloy film is patterned by dry etching using a photoresist as a mask, thereby forming a p-channel type MISFE.
Wirings 13a and 13b electrically connected to p-type semiconductor regions 6 and 6 of TQp, and n-channel MISFET Q
Wiring 1 electrically connected to n n-type semiconductor regions 9
3c and 13d are formed.

Next, as shown in FIG.
A silicon oxide film or the like is deposited on the upper part of 13d by a CVD method to form an interlayer insulating film 15, and a part of the interlayer insulating film 15 is opened by dry etching using a photoresist as a mask, thereby forming the wiring 13b. A connection hole 17a is formed in the upper part, and a connection hole 17b is formed in the upper part of the wiring 13c.
Subsequently, after an Al alloy film was deposited on the interlayer insulating film 15 by, for example, a sputtering method, the Al alloy film was patterned by dry etching using a photoresist as a mask, thereby being electrically connected to the wiring 13b. A wiring 16b electrically connected to the wiring 16a and the wiring 13c is formed.

Thereafter, CV is applied to the upper portions of the wirings 16a and 16b.
By depositing a silicon oxide film and a silicon nitride film by the method D to form the passivation film 18, the CMOS circuit of the first embodiment is completed.

(Embodiment 2) FIG. 20 is an equivalent circuit diagram of a DRAM of the present embodiment. As shown, this D
A memory array (MARY) of a RAM includes a plurality of word lines WL (WLn-1, WLn, Wn) arranged in a matrix.
Ln + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell that stores one bit of information is
It is composed of one information storage capacitance element C and one memory cell selection MISFET Qs connected in series thereto. Source of MISFET Qs for memory cell selection,
One of the drains is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is connected to a sense amplifier SA.

As shown in FIG. 21, the DR of the present embodiment
AM is formed on an epitaxial substrate composed of a silicon substrate 1 and an epitaxial layer 2 grown on its main surface. Similar to the first embodiment, this epitaxial substrate has a specific resistance of about 0.5 to 50 Ωcm and is made of p-type single crystal silicon doped with B (boron) of about 10 ¹⁶ atms / cm ³ as an impurity. It comprises a substrate 1 and a p-type epitaxial layer 2 formed on its main surface with a thickness of about 0.3 to 5 μm and a B (boron) concentration of about 10 ¹⁵ atms / cm ³ . An ion implanted layer 5 having a higher impurity concentration than the silicon substrate 1 and the epitaxial layer 2 is formed near the interface between the silicon substrate 1 and the epitaxial layer 2. About 10 ¹⁸ atms / cm ³ of boron (B) is introduced into the ion-implanted layer 5 as an impurity.

A part of the p-type well 3p formed in the epitaxial layer 2 has n constituting a DRAM memory cell.
A channel type MISFET Qt for selecting a memory cell is formed, and an n-channel type MI
The SFET Qn is formed. A p-channel MISFET Qp of a peripheral circuit is formed in the n-type well 3n formed in the epitaxial layer 2. MISFET Qt for memory cell selection, n channel type MISFET Q
The n- and p-channel MISFETs Qp are provided on the surface of the epitaxial layer 2 with LOCOS (Local Oxidation of Silicon).
are separated from each other by a field oxide film 28 formed by the (con) method.

The memory cell selecting MISFET Qt and the n-channel MISFET Qn are mainly composed of a p-type well 3p
A gate oxide film 7 formed on the surface of the p-type well 3p, and a gate electrode formed on the gate oxide film 7. 8. p-channel type MI
The SFET Qp mainly includes a pair of p-type semiconductor regions (source region and drain region) formed in the n-type well 3n.
6, a gate oxide film 7 formed on the surface of the n-type well 3n, and a gate electrode 8 formed on the gate oxide film 7. The gate electrode 8 is composed of a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film.

Bit lines BL1 and BL2 are formed above the memory cell selecting MISFET Qt, and the p-channel MISFET Qp and the n-channel MI
The first layer wiring 13 is provided on each of the SFETs Qn.
e, 13f are formed. Bit lines BL1, BL2
The lower electrode 25, the capacitor insulating film 26 and the upper electrode 2
7 is formed, and further thereon, second layer wirings 16c to 16f are formed.

According to the present embodiment, in order to use an inexpensive and low-epitaxial epitaxial substrate,
The manufacturing cost of the DRAM can be significantly reduced.

(Embodiment 3) FIG. 22 is an equivalent circuit diagram of an AND flash memory according to the present embodiment.

Memory block B

In [0], the word line (WL) extends in the row direction, and the X-decoder circuit (X-
DEC). The buried bit line (dk) is formed of an n-type semiconductor region 9 formed inside an epitaxial substrate described later, and extends in a column direction substantially orthogonal to a row direction. Embedded bit line (dk)
Is electrically connected via the block selection MISFETT ₃ bit lines (Dk). Bit line (Dk)
Is formed of a conductive layer having a lower resistance than the embedded bit line (dk), extends in the column direction on the memory block B [1] adjacent in the column direction, and has a Y select circuit (Y-SELEC).
T). Although not shown, the memory block B [1]

[0] and is configured similarly, the inside of the buried bit lines (dk) are electrically connected via the block selection MISFETT ₃ bit lines (Dk).

[0105] DB0, DB1 is a memory block selection line is electrically connected with the block selection MISFETT _3, it is electrically connected to the X- decoder (X-DEC). In addition, a Y select circuit (Y-SE
LECT) is electrically connected to the Y-decoder circuit (Y-DEC). X-decoder circuit (X-DE
C), a Y-decoder circuit (Y-DEC) and a Y select circuit (Y-SELECT) constitute a peripheral circuit, and each peripheral circuit is composed of n-channel MISFETs Qn and p
And a channel-type MISFET Qp.

As shown in FIG. 23, the flash memory according to the present embodiment is formed on an epitaxial substrate including a silicon substrate 1 and an epitaxial layer 2 grown on the main surface thereof. This epitaxial substrate has a specific resistance of about 0.5 to 50 Ωcm and a silicon substrate 1 made of p-type single crystal silicon doped with boron of about 10 ¹⁶ atms / cm ³ as an impurity, as in the first embodiment. And a p-type epitaxial layer 2 having a thickness of about 0.3 to 5 μm and a B (boron) concentration of about 10 ¹⁵ atms / cm ³ formed on its main surface. An ion implanted layer 5 having a higher impurity concentration than the silicon substrate 1 and the epitaxial layer 2 is formed near the interface between the silicon substrate 1 and the epitaxial layer 2. About 10 ¹⁸ atms / cm ³ of boron is introduced into the ion-implanted layer 5 as an impurity.

An n-channel MISFET Qm constituting a memory cell of a flash memory is formed in a part of the p-type well 3p formed in the epitaxial layer 2, and an n-channel MISFET Qm of a peripheral circuit is formed in another part. MISFET
Qn is formed. The n-type well 3n formed in the epitaxial layer 2 has a p-channel type M of a peripheral circuit.
ISFET Qp is formed. n-channel MIS
The FET Qm, the n-channel MISFET Qn and the p-channel MISFET Qp are separated from each other by a field oxide film 28 formed on the surface of the epitaxial layer 2 by the LOCOS method.

Memory cell n-channel MISFET Q
m is a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed mainly in the p-type well 3p;
A gate oxide film 7 formed on the surface of the mold well 3p; a gate electrode (floating gate) 8 formed on the gate oxide film 7; a second gate oxide film 29 formed on the gate electrode 8; And a control gate 30 formed on a two-gate oxide film 29. The n-channel MISFET Qn of the peripheral circuit mainly includes a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed in the p-type well 3p and a gate oxide film 7 formed on the surface of the p-type well 3p. And a gate electrode 8 formed on the gate oxide film 7. The p-channel MISFET Qp mainly includes a pair of p-type semiconductor regions (source and drain regions) 6 and 6 formed in an n-type well 3n, a gate oxide film 7 formed on the surface of the n-type well 3n, A gate electrode 8 formed on the gate oxide film 7.

Memory cell n-channel MISFET Q
Above m, first-layer wirings 13g to 13i are formed, and further thereon, a second-layer wiring 16g is formed. Peripheral circuit p-channel MISFET
A first layer wiring 13j is formed above each of the Qp and the n-channel MISFET Qn, and a second layer wiring 16h is further formed thereon.

The n-channel type M forming the memory cell
Writing of information to the ISFET Qm is performed, for example, by using a gate oxide film 7 between the n-type semiconductor region 9 and the floating gate 8 for the n-channel MISFET Qm selected by the buried bit line (dk) and the word line (WLn). Through the tunneling of electrons through. Further, information is erased by, for example, tunneling electrons between the epitaxial substrate and the floating gate 8 through the gate oxide film 8.

According to the present embodiment, since an epitaxial substrate that is inexpensive and has improved gate oxide film 7 quality is used, the reliability of the flash memory can be improved and the manufacturing cost can be reduced.

In this embodiment, as shown in FIG. 24, for example, the ion-implanted layer 5 (p ⁺ ) below the p-type well 3p is made p-type, and the ion-implanted layer 5 below the n-type well 3n is formed. By making '(n ⁺ ) n-type, these ion-implanted layers 5, 5' can also be used as buried layers. The impurity concentration of the ion-implanted layer 5 (p ⁺ ) is higher than that of the p-type well 3 p, and the impurity concentration of the ion-implanted layer 5 ′ (n ⁺ ) is n-type well 3 n
Higher than that of. As shown in FIG. 25, for example, as shown in FIG. 25, the ion-implanted layers 5 and 5 ′ are formed in a region where an n-type well 3n is to be formed later by using the photoresist film 200 as a mask in a process corresponding to FIG. A type impurity (for example, phosphorus (P)) is ion-implanted, and then, as shown in FIG.
A p-type impurity (for example, boron (B)) is ion-implanted into a region for forming the mold well 3p. At this time,
By forming the photoresist film 210 using the reverse pattern of the photoresist film 200, a photomask can be easily formed.

(Embodiment 4) FIG. 27A is a cross-sectional view of a main part showing a semiconductor integrated circuit device of this embodiment, and FIG. 27B is a view taken along line XX 'of FIG. 4 is a graph showing an impurity concentration profile obtained.

The semiconductor integrated circuit device of the fourth embodiment is
An n-type well 3n and a p-type well 3p, and an n-type buried layer 3n 'and a p-type buried layer 3p' are provided inside the epitaxial layer 2. A p-channel MISFET Qp is formed in the n-type well 3n of the epitaxial layer 2, and an n-channel MISFET Qn is formed in the p-type well 3p.
Are formed. The p-type buried layer 3p 'is a p-type well 3
It is formed below p and has a higher impurity concentration than p-type well 3p. The n-type buried layer 3n 'is an n-type well 3
It is formed below n and has a higher impurity concentration than n-type well 3n. Since the n-type buried layer 3n ′ and the p-type buried layer 3p ′ act to suppress the extension of the depletion layer, a MISFET with improved punch-through resistance can be formed.

N-type buried layer 3n 'and p-type buried layer 3
p ′ is configured with, for example, a retrograde structure.
Further, an n-type buried layer 3n 'and a p-type buried layer 3p'
Are formed so as to be shallower than other portions below the element isolation trench 4, and function as a channel stopper layer. The n-type buried layers 3n 'and p
It goes without saying that not only the type buried layer 3p 'but also the n-type well 3n and the p-type well 3p thereover may be configured with a retrograde structure.

The ion-implanted layer 5 formed near the interface between the silicon substrate 1 and the epitaxial layer 2 is formed of, for example, the same p-type as the conductivity type of the silicon substrate 1, and includes an n-type buried layer 3n 'and a p-type buried layer 3p. 'Than the higher concentration of impurities are introduced. The conductivity type of the ion implantation layer 5 is not limited to p-type. For example, it may be formed by ion implantation of an inert gas such as argon (Ar).

A p-type buried layer 3p 'having a higher impurity concentration than the p-type well 3p is formed below the p-type well 3p, and an n-type buried layer having a higher impurity concentration than the n-type well 3n is formed below the n-type well 3n. According to the present embodiment in which the layer 3p 'is formed, the gettering effect is further improved as compared with the case where only the ion-implanted layer 5 is formed. Further, since the well resistance can be reduced, the latch-up resistance of the CMOSFET can be improved.

Further, n-type buried layer 3n ′ and p-type buried layer 3p functioning as a channel stopper layer are formed below element isolation groove 4 so as to be in contact with the bottom (4a) and side wall (4b) of element isolation groove 4. ', The element isolation characteristics (channeling prevention effect) are improved, so that the area of the element isolation groove 4, ie, the p-channel MI
The distance (L) between the SFET Qp and the n-channel MISFET Qn can be reduced. Thus, reduction in chip size or high integration of LSI can be promoted.

The n-type well 3 is provided inside the epitaxial layer 2.
In order to form the n-type and p-type wells 3p and the n-type buried layer 3n 'and the p-type buried layer 3p', for example, as shown in FIG. Part of the epitaxial layer 2 contains phosphorus (P) or arsenic (A
An n-type impurity such as s) is ion-implanted once with different energies, and then a p-type impurity such as boron (B) is implanted once with different energies into another part of the epitaxial layer 2 as shown in FIG. After ion implantation,
These impurities may be diffused into the epitaxial layer 2 by heat-treating the epitaxial substrate.

N-type buried layer 3n 'and p-type buried layer 3
p ′ is formed below the element isolation groove 4 so as to be in contact with the bottom (4a) and the side wall (4b) of the element isolation groove 4 (FIG. 27), for example, as shown in FIG. In order to avoid contact with the bottom (4a) of the element isolation groove 4, it is formed in a region deeper than the element isolation groove 4, or as shown in FIG. It may be formed in a region shallower than the element isolation groove 4 so as to be in contact therewith.

N-type buried layer 3n 'and p-type buried layer 3
so that p ′ is not in contact with the bottom (4a) of the element isolation groove 4;
When formed in a region deeper than the element isolation groove 4 (FIG. 30)
(A)) Although the channeling prevention effect is reduced as compared with the structure shown in FIG. 27, the gettering effect and the CMO
The effect of suppressing the latch-up of the SFET is obtained. Also, n
The buried layer 3n ′ and the p-type buried layer 3p ′ are in contact with only the side walls (4b) of the isolation groove 4 so that the
When formed in a shallower region (FIG. 30B), the effect of preventing channeling is reduced as compared with the structure shown in FIG. 27, but compared with the structure shown in FIGS. 27 and 30A. Thus, the gettering effect and the latch-up suppression effect of the CMOSFET are improved. Further, in the structure of FIG. 30B, the depths of the n-type well 3n and the p-type well 3p can be freely set without considering the depth of the element isolation groove 4, so that the degree of freedom in device design is improved. .

(Embodiment 5) FIG. 31 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of the present embodiment. In the present embodiment, one of the n-type buried layer 3n 'and the p-type buried layer 3p' of the fourth embodiment (p-type buried layer 3p ')
Are omitted to simplify the manufacturing process.

The semiconductor integrated circuit device of the fifth embodiment is
An n-type well 3n and a p-type well 3p and an n-type buried layer 3n 'are provided inside the epitaxial layer 2. N-type buried layer 3 provided below n-type well 3n
n ′ almost overlaps the ion-implanted layer 5 of the same conductivity type (p-type) as the silicon substrate 1, and an impurity of a higher concentration (about twice or more) than the ion-implanted layer 5 is introduced. That is, the n-type buried layer 3n 'is formed such that the maximum peak concentration of the impurity is substantially the same as that of the ion-implanted layer 5, and compensates the ion-implanted layer 5 with the impurity concentration. The n-type buried layer 3
n ′ is formed so as to be shallower than other portions under the element isolation groove 4 and functions also as a channel stopper layer. The n-type buried layer 3n 'can be formed by the same method as in the fourth embodiment. In the fifth embodiment, since the p-type buried layer 3p 'is not formed, the process is simpler than that in the fourth embodiment.

(Embodiment 6) FIG. 32 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of this embodiment. In the semiconductor integrated circuit device according to the sixth embodiment, C (carbon) or O (carbon) is provided near the interface between the silicon substrate 1 and the epitaxial layer 2.
An ion implantation layer 5a formed by implanting (oxygen) is provided. This ion implanted layer 5a is not formed using a p-type impurity such as boron (B) or an n-type impurity such as P (phosphorus), As (arsenic), and Sb (antimony). Only works as a ring sight.

The ion implantation layer 5a functioning only as a gettering site can be formed by using an inert element such as argon (Ar) or N (nitrogen), Si, F (fluorine), or the like. . The impurity concentration of the ion implantation layer 5a may not be higher than the impurity concentration of the silicon substrate 1 or the epitaxial layer 2.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above description, the invention made mainly by the present inventor is described in the CMO, which is a field of application which is the background of the invention.
The case where the present invention is applied to a semiconductor integrated circuit device technology having an S circuit has been described. However, the present invention is not limited thereto.
For example, the present invention can be applied to a semiconductor integrated circuit device having a bipolar-CMOS circuit in which a CMOS circuit and a bipolar transistor circuit are provided on the same semiconductor substrate. The present invention relates to a method in which the MISF
The present invention can be applied to a semiconductor integrated circuit device forming an ET.

In the first, fourth, fifth and sixth embodiments, the element isolation groove may be replaced with a field oxide film formed by the LOCOS method as used in the second and third embodiments. For forming the field oxide film, high-temperature steam oxidation of 1000 ° C. or more is used.

[0129]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, since the thickness of the epitaxial layer can be reduced without impairing the characteristics of the epitaxial substrate, the manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1G are explanatory views showing a method for manufacturing a semiconductor integrated wafer according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a graph showing a relationship between an initial oxygen concentration [Oi] of a silicon substrate 1 and a gate oxide film defect density.

FIG. 4 is a graph showing a relationship between a film thickness of an epitaxial layer 2 and a defect density of a gate oxide film.

FIG. 5 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a graph showing a relationship between an initial oxygen concentration and an amount of precipitated oxygen.

FIG. 7 is an essential part cross sectional view showing the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 8 is an essential part cross sectional view showing the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 10 is a graph showing an impurity concentration profile along a depth direction of an epitaxial substrate having an ion-implanted layer formed thereon.

FIG. 11 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

14A is a cross-sectional view of an epitaxial substrate having a well formed on an ion-implanted layer, and FIG. 14B is an impurity concentration along a depth direction of the epitaxial substrate having a well formed on an ion-implanted layer. It is a graph which shows a profile.

FIG. 15 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 19 is an essential part cross sectional view showing the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 20 is an equivalent circuit diagram of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 22 is an equivalent circuit diagram of the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 25 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device of the third embodiment of the present invention.

FIG. 26 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention;

FIG. 27A is a cross-sectional view of a principal part showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention, and FIG. 27B is an epitaxial substrate having a well and a buried layer formed above an ion-implanted layer; 4 is a graph showing an impurity concentration profile along a depth direction.

FIG. 28 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device of the fourth embodiment of the present invention.

FIG. 29 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device of the fourth embodiment of the present invention.

FIGS. 30A and 30B are cross-sectional views of main parts showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 31 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate (CZ substrate) 1a CZ wafer 2 epitaxial layer 3n n-type well 3p p-type well 3n 'n-type buried layer 3p' p-type buried layer 4 element isolation groove 4a groove 5 ion implanted layer 5 'ion implanted layer 5a ion Implanted layer 6 p-type semiconductor region (source region, drain region) 7 gate oxide film 8 gate electrode 9 n-type semiconductor region (source region, drain region) 10 silicon oxide film 11 sidewall spacer 12 silicon oxide films 13a to 13j wiring 14a To 14d Connection hole 15 Interlayer insulation film 16a to 16h Wiring 17a Connection hole 17b Connection hole 18 Passivation film 20 Silicon oxide film 21 Silicon oxide film 22 Silicon oxide film 23 Silicon nitride film 24 Silicon oxide film 25 Lower electrode 26 Capacitive insulating film 27 Upper Electrode 2 Field oxide film 29 Second gate oxide film 100 Ingot 200 Photoresist film 210 Photoresist film BL1, BL2 Bit line C Information storage capacitor Qm N-channel MISFET Qn N-channel MISFET Qp P-channel MISFET Qt For selecting memory cell MISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirofumi Shimizu 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Norio Suzuki Five, Josuihoncho, Kodaira-shi, Tokyo No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Kenichi Kuroda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated Hitachi Semiconductor Co., Ltd. (72) Inventor Saito Shigeaki Tokyo 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Tomomi Sato 5-2-1-1, Josuihoncho, Kodaira-shi, Tokyo Nichi-cho SII Engineering (72) Inventor Kazuo Takeda 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory (72) Who Masao Kawamura Ome, Tokyo Imai 2326 address Hitachi Seisakusho device development in the center (72) inventor Sugino Yushi, Tokyo Kodaira Josuihon-cho, Chome No. 20 No. 1 Co., Ltd. Hitachi semiconductor business unit

Claims (33)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) preparing a silicon substrate having an epitaxial layer formed on a main surface thereof; A step of ion-implanting an impurity so as to reach near an interface with the epitaxial layer, and forming an ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer near the interface; 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductivity type of said ion-implanted layer is the same as the conductivity type of said silicon substrate. Production method. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the ion implantation of the impurity is performed over the entire main surface of a silicon substrate having a uniform impurity concentration. A method for manufacturing a circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said epitaxial layer has a thickness of about 0.5.
A method for manufacturing a semiconductor integrated circuit device, wherein the thickness is 3 to 5 μm. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a first conductivity type impurity is ion-implanted into the first region of the silicon substrate to form a first conductivity type ion implantation layer. And forming a second conductivity type ion-implanted layer by ion-implanting a second conductivity type impurity into the second region. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said impurities include any one of boron, argon, carbon, phosphorus, and arsenic. Device manufacturing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the specific resistance of said silicon substrate is about 0.5.
A method for manufacturing a semiconductor integrated circuit device, wherein 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said ion implantation is performed so as to reduce local stress existing near an interface between said silicon substrate and said epitaxial layer. A method for manufacturing a semiconductor integrated circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the ion implantation of the impurity is performed so as to make the vicinity of the interface between the silicon substrate and the epitaxial layer amorphous. Of manufacturing a semiconductor integrated circuit device. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said ion-implanted layer functions as a buffer region. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the ion implantation layer is used as a gettering layer. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said epitaxial layer has a MISFE.
A method for manufacturing a semiconductor integrated circuit device, wherein T is formed. 13. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) preparing a silicon substrate having an epitaxial layer formed on a main surface thereof; Impurity is ion-implanted on the entire surface or a part thereof so as to reach the vicinity of the interface with the epitaxial layer, and a first conductivity type ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer is formed near the interface. And (c) ion-implanting a second conductivity-type ion implanted at a higher impurity concentration than the silicon substrate and the epitaxial layer by ion-implanting an impurity for inverting the conductivity type into a part of the first conductivity-type ion implanted layer. Forming a layer, and (d) forming a semiconductor element on the epitaxial layer. 14. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) preparing a silicon substrate having an epitaxial layer formed on a main surface; To reach the vicinity of the interface with the epitaxial layer, ion implantation of impurities containing at least carbon or oxygen,
Forming an ion-implanted layer constituting a gettering site near the interface; and (c) forming a semiconductor element on the epitaxial layer. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein said semiconductor element is a semiconductor integrated circuit device.
A method for manufacturing a semiconductor integrated circuit device, which is an SFET. 16. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) preparing a silicon substrate having an epitaxial layer formed on a main surface; and (b) preparing a silicon substrate. (C) forming an ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer near the interface by ion-implanting impurities so as to reach near an interface with the epitaxial layer; A first conductivity type impurity is ion-implanted in the first region, and a first impurity is implanted on the ion-implanted layer in the first region.
Forming a conductive type buried layer; (d) ion-implanting a second conductive type impurity into the second region of the epitaxial layer to form a second conductive type buried layer above the ion-implanted layer in the second region. Forming; and (e) forming a MISFET in the epitaxial layer. 17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first conductivity type buried layer and the second conductivity type buried layer are formed below the element isolation region. A method for manufacturing a semiconductor integrated circuit device, wherein the method is formed so as to be in contact with a bottom. 18. A semiconductor integrated circuit device in which a MISFET is formed on an epitaxial layer grown on a main surface of a silicon substrate, wherein said epitaxial layer has a thickness of about 0.3.
A semiconductor integrated circuit device having a thickness of 3 to 5 [mu] m, wherein an ion-implanted layer having a higher impurity concentration than the silicon substrate and the epitaxial layer is formed near an interface between the silicon substrate and the epitaxial layer. 19. The semiconductor integrated circuit device according to claim 18, wherein the conductivity type of said ion implantation layer is the same as the conductivity type of said silicon substrate. 20. The semiconductor integrated circuit device according to claim 18, wherein said ion-implanted layer functions as a buffer region. 21. The semiconductor integrated circuit device according to claim 18, wherein the ion implantation layer is used as a gettering layer. 22. The semiconductor integrated circuit device according to claim 18, wherein a second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer,
A semiconductor integrated circuit device, wherein a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. 23. The semiconductor integrated circuit device according to claim 22, wherein the first conductivity type well and the second conductivity type well are separated from each other by an element isolation groove formed in the epitaxial layer. A semiconductor integrated circuit device characterized by the above-mentioned. 24. The semiconductor integrated circuit device according to claim 22, wherein a part of said first conductivity type well includes a DRAM.
Is formed, and a complementary MISFET forming a peripheral circuit of the DRAM is formed in another part of the first conductivity type well and the second conductivity type well. A semiconductor integrated circuit device characterized in that: 25. The semiconductor integrated circuit device according to claim 22, wherein a second conductivity type MISFET forming a memory cell of a nonvolatile memory is provided in a part of the first conductivity type well.
A complementary MISFET forming a peripheral circuit of the nonvolatile memory is formed in another part of the first conductivity type well and the second conductivity type well. Integrated circuit device. 26. The semiconductor integrated circuit device according to claim 22, wherein the first conductivity type well and the second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the impurity concentration on the surface. A semiconductor integrated circuit device comprising: 27. The semiconductor integrated circuit device according to claim 22, wherein the ion-implanted layer formed below the first conductivity type well forms a second conductivity type buried layer.
The semiconductor integrated circuit device according to claim 1, wherein the ion-implanted layer formed below the second conductivity type well forms a first conductivity type buried layer. 28. A method for manufacturing a semiconductor wafer, comprising the following steps: (a) forming a thermal oxide film on a main surface of a silicon wafer, and then removing the thermal oxide film by etching; ,
(B) forming an epitaxial layer on the main surface of the silicon wafer from which the thermal oxide film has been removed, and (c) forming a semiconductor element on the epitaxial layer. 29. The method for manufacturing a semiconductor wafer according to claim 28, wherein the temperature for forming the thermal oxide film is 100.
A method for producing a semiconductor wafer, wherein the temperature is 0 ° C. or lower. 30. The method of manufacturing a semiconductor wafer according to claim 28, wherein said epitaxial layer has a thickness of about 0.3.
A method of manufacturing a semiconductor wafer, wherein 31. The method for manufacturing a semiconductor wafer according to claim 28, wherein oxygen taken in at the time of pulling up the ingot using the Czochralski method removes the thermal oxide film at a temperature remaining near the surface of the silicon wafer. Forming a semiconductor wafer. 32. The method according to claim 28, wherein the thermal oxide film has a thickness of 10 nm or more,
A method for manufacturing a semiconductor wafer, comprising removing latent scratches and minute defects present on the surface of the silicon wafer together with the thermal oxide film by the etching. 33. A silicon wafer having a film thickness of about 0.
A semiconductor, wherein an epitaxial layer of 3 to 5 μm is formed, and an ion-implanted layer having a higher impurity concentration than the silicon wafer and the epitaxial layer is formed near an interface between the silicon wafer and the epitaxial layer. Wafer.