JPH10105154A - Graphic display device and graphic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the access efficiency of" a graphic memory and improve the picture quality of a enjoying picture on a memory integrated type graphic, display device by controlling display access by the graphic processor adaptively to the cache mode of' a CPU. SOLUTION: Of the memory integrated type graphic display device wherein the CPU 10 and graphic processor 20 accesses the common graphic memory 40, the graphic processor 20 is provided with a bit specifying the cache system of the CPLI 10 and according to this specification, the time of' single-time maximum display access is varied. Namely, when a copy-back system is adopted, write access by the CPU is shorter than that of' a store-through system, so the display access time of the graphic processor 20 is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphics display device, and more particularly to a graphics display device and a graphics processor in which a plurality of pieces of information necessary for displaying a moving image are integrated in the same memory.

[0002]

2. Description of the Related Art As a processor for processing high-speed three-dimensional graphics, "3D CG drawing LSI-300,000 polygons / sec realized by a personal computer-(Nikkei Electronics;
No. 640, 1995. 7.17, pp. 109-120) "(Cited Example 1). This processor is provided with three types of memories dedicated to the processor: a texture memory, a frame buffer memory, and a local memory. Although this architecture is advantageous in terms of improving performance, it is not suitable for small and inexpensive devices such as personal portable devices due to the use of multiple memories.

On the other hand, an example in which graphics information is unified and the number of memories can be reduced as compared with the cited reference 1 is disclosed in
No. 257793 (Reference 2). In this graphics system, a CPU program, texture data, a frame buffer, and the like are integrated in a main memory of the CPU.

[0004]

In the above-mentioned prior art, it is realized that a sufficiently high-speed memory system having a memory access capability of several hundred MB / s is provided, and a sufficient time for reading display data is ensured. It is a premise of.
This requires an expensive memory system and hinders miniaturization and cost reduction.

In the configuration of the cited reference 2, if the access capability of the memory is reduced by using an inexpensive memory system, in order to secure the readout time of the display data necessary for the moving image, the drawing and CPU access other than the display need to be performed. Needs to be adjusted. The write access time from the CPU varies depending on the data amount, but the data amount per time for high-speed graphics increases, and the access time per screen also increases.

For this reason, display access is prioritized in the memory integrated type. However, even if an access request for reading out the drawing data from the graphics memory (hereinafter referred to as display access) is issued, during execution of another access such as a CPU, the process waits until the access is completed. When the data in the buffer becomes empty, the display screen of the moving image is disturbed. Therefore, the display access time has a margin, the data storage amount of the display buffer is increased, and the image quality of the moving image is maintained. However, in the conventional display access priority method, the access efficiency of the graphics memory is reduced, so that it becomes difficult for the CPU to process high-speed graphics.

Generally, a CPU has a built-in cache memory for transferring output data, and the timing of memory access differs depending on the cache system. For example, for a write-through method that transfers only one word,
In the copy-back method in which a plurality of words are continuously transferred, the drawing procedure information (hereinafter referred to as a drawing command) can be transferred collectively.
In the write-through method having a long access time, a sufficient display access time is secured. That is, since no consideration is given to the difference between the cache methods, the memory access efficiency is reduced, and the high-speed graphic display that can be performed by the copy-back method is sacrificed.

An object of the present invention is to optimize the continuous time of one display access according to the cache system of a CPU when using one graphics memory accessed from both a CPU and a graphics processor. It is an object of the present invention to provide a display device which increases the access efficiency of the device and realizes a high-speed graphic display, and a graphic processor for the display device.

[0009]

A graphics display device according to the present invention, which achieves the above object, has a CPU for generating drawing procedure information (drawing command) including a type of a graphics figure to be displayed, a vertex parameter, and the like. And its C
One memory for storing the drawing procedure information written from the PU (write access) and the drawing data (bitmap information) to be output to the display, and performing drawing access to the drawing procedure information and storing the drawing data in the memory A graphics processor that performs display reading (display access) for outputting the drawing data to the display device; and the graphics processor is a cache memory that is provided in the CPU and transfers data to the memory. The display read timing for the memory is changed according to a cache method.

[0010] The graphics processor provides cache system information from the CPU indicating whether the cache system is a system for continuously transferring a plurality of words of data to the memory or a system for transferring one word at a time. In the former case, the continuous time of one display readout is shorter than that in the latter case.

A graphics processor according to the present invention, which achieves the above object, comprises: a storage area for drawing procedure information (drawing command) including a type of a graphics figure to be displayed and vertex parameters; A graphics memory having an area for storing information, a drawing access for generating the bitmap information, and a display access for outputting display data to a display device, further comprising: Transfer method information indicating whether the write access of the drawing procedure information to the Ix memory is a method of transferring data of a plurality of words at a continuous address or a method of transferring data for each word is set, and in the former case, compared to the latter, A continuous time of one display access is shortened.

Further, the graphics processor comprises:
A drawing unit for performing the drawing access, a display controller for performing the display access, an interface unit for receiving data transfer from a CPU and performing the write access, and controlling such that the memory access request is accepted and the display access is prioritized. Memory controller means for transferring the drawing procedure information.
The transfer method information is set according to the PU cache method, and when the cache method is the copy-back method, the continuous time of one display access is shortened as compared with the write-through method.

Further, the graphics processor includes a display buffer for temporarily storing bitmap information read from the graphics memory by the display access and outputting the bitmap information at the timing of a display, and The number of consecutive words according to the maximum value of the number of data held in the display buffer, the timing of the display access request issuance is a threshold value less than the number of data holding, these maximum value and the threshold value in the transfer method information It is characterized in that it is changed according to it.

According to the configuration of the present invention, when the CPU uses the copy-back method, the writing of data to the graphics memory of the CPU is a continuous address, so that the write access time for the same data amount can be shortened. As a result, a margin time for ensuring display access priority can be reduced, and the overall write access time and display access time can be reduced as compared with the case of the write-through method, so that the memory access efficiency increases. , High-speed graphics processing becomes possible. In other words, CPU
The high-speed copy-back method enables high-speed drawing processing to follow write access to drawing data.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a configuration diagram of a graphic processing system to which the present invention is applied. The CPU 10 controls the entire apparatus and executes a program for displaying a graphic on the display 51. The main memory 11 is
The data and programs to be processed by the PU 10 are stored. C
The D-ROM controller 12 accesses the graphic information on the CD-ROM, and the communication controller 13 sends and receives information to and from another device (not shown).

The graphics processor 20 draws a figure in a display area in the graphics memory 40, reads out the drawn data, and displays the figure on a display 51. DAC (Digital to Analog Converter) 10
Converts the digital display data output from the graphics processor 20 into analog data.

It is desirable to use a DRAM as an element constituting the graphics memory 40. This is because the DRAM has a higher degree of integration of transistors with respect to the chip area than other memories. In addition, it has an access method called high-speed page mode access, and high-speed access is possible in continuous access when the upper part of the address (for example, bit 9 or more) matches.

The graphics displayed by the present apparatus are displayed in a moving image of graphics graphics by changing the size and position of the graphics little by little at a period of 1/60 seconds or 1/30 seconds, and showing the screen continuously. . Therefore, the CPU 10 and the graphics processor 20 perform drawing for one screen within 1/60 second or 1/30 second. Drawing of a figure is performed in the following procedure, and processing for one screen is repeated.

(1) Coordinate conversion of graphic data by CPU 10 For a graphic to be displayed, the direction, size, etc. are calculated, and the vertex coordinates of the graphic are calculated. In the case of a complicated figure formed by combining a large number of simple figures such as triangles and squares, the vertex coordinates of all the simple figures are calculated.

(2) Creation of Display List by CPU 10 In order to draw a complicated figure composed of a large number of simple figures in the graphics memory 40, the CPU 10 sends a drawing command (hereinafter simply referred to as a command) to the graphics processor 20. Is converted into an executable command format and transferred to the graphics memory 40. Normally, commands in simple figure units are combined and linked to commands for one figure. A combination of these commands is called a display list. The display list has a size of several tens to several hundreds of kilobytes and is stored in the display list area 401.

(3) Drawing by the graphics processor 20
0 is sequentially read, and the drawing / display area 40 in the graphics memory 40 is read in accordance with the command shown in the list.
Draw on 2.

(4) Display by the graphics processor 20 The graphics drawn in the drawing / display area 402 are read out at the display timing by the graphics processor 20 and displayed on the display 51. The drawing / display area 402 is composed of a double buffer, and the drawing and display buffers are alternately switched.

The above processes (1) to (4) are performed by
Repeat in second or 1/30 second cycle. System bus 14
Transfers the data of the display list in the above cycle.

Next, an outline of the configuration and operation of the graphics processor 20 will be described. The CPU I / F 21 is a CP
U10 controls access to the registers such as the system control register 32 and the graphics memory 40. The drawing unit 23 fetches the display list in the graphics memory 40 and performs drawing according to the command indicated in the list. Parameter converter 2
2 converts command parameters as needed.
The display controller 24 performs control for displaying data drawn by the drawing unit 23.

As described above, the graphics processor 2
Since 0 accesses the graphics memory 40 each time the element performs some processing, increasing the access efficiency of the graphics memory 40 leads to an improvement in the processing speed. Therefore, the graphics processor 20
Access efficiency is enhanced by providing a cache or FIFO for each access request.

The CPU FIFO 25 speeds up access to the graphics memory 40 by the CPU 10. Cache (1) 26 is dedicated to command, Cache (2)
27 is dedicated to texture, and cache (3) 28 is dedicated to drawing. Further, it has a display buffer 29 for display data.

The memory controller 30 receives an access request to the graphics memory 40 from the caches (1) to (3), the FIFO 25, and the like, determines a priority order, and controls access. The memory controller 30 gives the highest priority to access from the display controller 24. However, while the access from the CPU 10 or the drawing unit 23 is being performed, the access from the display controller is awaited without interruption.

The system control register 32 is a register for designating the operation mode of the graphics processor 20. The register 32 has a CAM (CPU Access Mode) bit that specifies the cache mode of the CPU 10.

FIG. 2 shows the terminal functions (1) to (5) of the graphics processor 20.

(1) System system This is a terminal for inputting a system mode setting and a clock and reset. The graphics processor 20 can input independent clocks for the drawing system and the display system,
Irrespective of the performance of the drawing, the drawing system can always perform high-speed processing.

(2) CPU system This is a terminal for the CPU I / F 21. The CPU 10 can access the entire space of the graphics memory 40 and internal registers such as the system control register 32. To access the graphics memory 40, use CS0
Set the terminal to Low and CS1 to access the register.
Set the terminal to Low. Write access to the graphics memory 40 has two write enable files so that byte units can be used. In addition, there are DREQ and DACK terminals for controlling DMA transfer, a WAIT terminal for extending a bus cycle, and an IRL terminal for generating an interrupt to the CPU 10.

(3) Power System There are terminals for supplying power, a terminal dedicated to a PLL for performing clock control, and other terminals for general use.

(4) Display system Display terminals include a dot clock output (DCLK), a display data output (DD0-DD15), and a synchronizing signal input / output terminal (HSYNC, VSYNC).

(5) Memory system A DRAM is used as an I / F with the graphics memory 40.
The terminal which can be directly connected is provided.

FIG. 3 shows a drawing command of the graphics processor. The quadrangle drawing command draws the rectangular texture data while transforming it into an arbitrary quadrangle.
If the texture data is binary, color expansion is performed. L
INE draws a single line or a plurality of lines. M
OVE moves the drawing start point. LOFS shifts the origin of drawing coordinates. The command after the MOVE is executed draws the coordinate parameters shown in the display list with the coordinates shifted by the amount specified by the command. AFFIN designates rotation, enlargement, and reduction when drawing a figure. With respect to the coordinate parameters shown on the display, the coordinates are rotated (or enlarged or reduced) by the amount designated by AFFIN and drawn. JUMP branches the display list. GOSUB calls the display list subroutine. RET returns from the subroutine. TRAP ends the display list fetch. The FLASH invalidates data existing in the cache (2) 27 which is a cache of texture data, and newly reads data from the graphics memory 40.

FIG. 4 shows a data list of each register in the graphics processor, and its function will be described below.

(1) System control register SRES initializes the drawing unit 23 by software, and DRES initializes the display controller 24 by software. The DAC switches the display area (frame buffer area). The RS starts fetching the display list. CAM is CPU10
The type of the cache 101 is designated.

As a feature of the operation in which the CPU 10 stores data in the graphics memory 40, the cache 10
In the case where the copy back method 1 is employed, data is written collectively by the cache line size.
On the other hand, when the write-through method is adopted, data is written in units of one word. Therefore, it is possible to specify or switch the cache method of the CPU by setting the CAM.

(2) Status register VBK notifies switching of the display frame. TRA
Notifies that the TRAP command has been executed and display list fetching has been completed. The DBF indicates which of the two frame buffers is currently being displayed.

(3) Status register / clear register The corresponding status register bit is cleared.

(4) Interrupt enable register According to each bit of the corresponding status register, CP
Specifies that an interrupt is to be generated in U10.

(5) Rendering Mode MWX specifies whether the horizontal width of the screen is 512 pixels or less, or 513 pixels or more and 1024 pixels or less. GBM specifies whether one pixel is 8 bits or 16 bits.

(6) Display Mode The SCM specifies whether the display is interlaced or non-interlaced. The TVM specifies whether the mode is the TV synchronous mode or the master mode. RC
YN designates the number of refresh cycles of the graphics memory 40.

(7) Display Size The size of the display screen in the X and Y directions is specified.

(8) Display Start Address The start addresses of the two frame buffers on the graphics memory 40 are specified.

(9) Display List Address The start address of the display list on the graphics memory 40 is specified.

(10) Source area start address Designates the start address of the texture data storage area.

(11) Display Control Registers Register numbers 10 to 1A are registers relating to display control. The timing of reading the display data is set according to the size of the display screen, and the cycle of the horizontal / vertical synchronization signal is set. The display reset output register sets a color value to be displayed on the screen when display reading is not performed. For example, the screen can be set to blue back (blue display) while the display operation is stopped.

(12) Command status register This register notifies the memory address when the fetch of the display list is stopped.

Next, the configuration and operation of the CPU FIFO 25 for allowing the CPU 10 to access the graphics memory 40 will be described.

FIG. 5 is a functional block diagram of the CPU FIFO. Each time the CPU 10 performs a store operation to the graphics memory 40, a write request signal is sent from the CPU I / F unit 21. Then, the counter 252 counts up, and the write address and data of the CPU 10 at that time are stored in the FIFO 250. The coincidence detection unit 253 compares the value of the counter 252 with the FIFO capacity. When it is found that the FIFO is full, the flip-flop 258 is set. As a result, CPUI
/ F section 21 is notified of the busy state of FIFO 250, and C
Prevent PU 10 from storing data anymore.

On the other hand, a write request to the graphics memory 40 is output to the memory controller 30.
The memory controller 30 outputs a FIFO counter update signal for updating the counter 256 every time one word of data is written. The value of the counter 256 is the coincidence detector 25
5 is compared with the value of the counter 252. The counter 256 is a read counter of the FIFO 250, and the counter 252 is a write counter of the FIFO. When the two values match (that is, when the memory controller 30 reads the number of words written by the CPU 10), the flip-flop 258 is reset to stop writing to the graphics memory 40.

The free-run counter 254 indicates that the predetermined period C
When there is no writing by PU10, FIFO2
It operates to write 50 data into the graphics memory 40. Further, when the CPU 10 reads the graphics memory 40 or when the drawing unit 23 starts fetching the display list, the data of the FIFO 250 is stored in the graphics memory 4 in advance.
Operate to write 0.

Here, the internal cache 10 of the CPU 10
The difference in the access time of the graphics memory 40 due to the difference in the first method will be described. As a cache method of the CPU 10, a copy-back method and a write-through method are known.

In the copy-back method, even if the CPU 10 executes a store instruction to the memory 40, only the cache 101 in the CPU 10 is changed, and the data in the memory 40 is not changed immediately. The memory 40 is changed when data of a plurality of words called a cache line is flushed from the cache 101 to the memory 40 at a time. The data of the cache line is a plurality of words of a continuous address. That is, addresses of data written to the graphics memory 40 via the FIFO 250 are continuous. Therefore, writing to the graphics memory 40 from the FIFO 25 can be performed in a short time by the high-speed page mode access of the DRAM.

On the other hand, in the write-through method, when the CPU 10 executes a store instruction for the memory 40, data is immediately written to the memory 40 in word units. Therefore, the FIFO memory 250 has the graphics memory 4
Data written to 0 may be a discontinuous address. In the worst case, everything may be discontinuous. If the address is discontinuous, the FIFO
From 25, the writing time to the graphics memory 40 becomes longer. In the worst case, 4
This is about twice as long (up to 80 cycles).

Next, the configuration and operation of the drawing cache 28 will be described. FIG. 6 is a block diagram of a drawing cache. The cache (3) is dedicated to drawing, but the drawing unit 23 does not read data in the cache (3) 28. That is, since it does not have a function of performing data calculation with a sketch at a drawing destination, only a write operation is performed. Since there is no need to read a sketch, high-speed operation with extremely reduced memory access is possible.

When the drawing unit 23 writes the data,
The drawing address and the drawing data are stored in the register file 2900, and the counter 2901 is counted up. The value of the counter 2901 is compared by the coincidence detection unit 2902, and when the register file 2900 is full, the memory controller 30 via the flip-flop 2903
Output write request to. Drawing unit 23
Has a function of flushing data in the cache when one graphic drawing command is completed in a state where the cache (3) 28 is empty. When the flash signal becomes active, the cache 28 stores the counter 2901
The data is written into the graphics memory 40 by the number of words indicated by.

The CPU FIFO 25 and the cache 2
8 is that write data is transferred by the number of words detected by the counter 252 or the counter 2901 and unnecessary data transfer is not performed. In this regard, a general cache used in a CPU or the like performs writing in units of a line size, and therefore also transfers a portion of data that is not rewritten.

FIG. 7 shows the address mapping of the CPU. The software of the CPU 10 can access the graphics memory 40 without distinguishing it from the main memory 11.

In the graphics memory area, a frame buffer 0 and a frame buffer 1 are provided. When displaying a moving image of graphics, the display is performed by switching the frame buffer areas 0 and 1 in units of 1/60 seconds (or 1/30 seconds). The drawing unit 23 always draws on the frame buffer that is not displaying. This makes it possible to display a high-quality moving image without displaying an intermediate state of drawing. Display list area is also 2
And the drawing unit 23 and the CPU 10 alternately use them.

Next, the display access of the graphics memory 40 by the display controller 24 and the display buffer 2
9 will be described.

FIG. 8 is a functional block diagram of the display controller. The display controller 24 outputs a synchronization signal (HSYNC, VSYNC) and display data to the display 51 and displays a graphic on the screen of the display 51. The timing control unit 246 includes a synchronization signal (HSYNC, VSYNC)
Is generated, and the output timing of the data in the display buffer 29 is notified to the display data output control 245.

The display buffer 29 buffers a part of the data in the display area of the graphics memory 40.
For example, if the display buffer 29 has 128 words, 1
In a system in which the pixel is one byte, data of 256 pixels is held.

The data transfer speed from the graphics memory 40 to the display buffer 29 depends on the display buffer 29.
Is much faster than that from to. For example, the former operates at 28 MHz and the latter operates below 14 MHz. Therefore, even if the readout timing of the display data from the graphics memory 40 is slightly shifted, the data transfer timing to the display 51 can always be kept constant.

Reading and writing of the display buffer 29 are performed as follows. Display data output control unit 2
Reference numeral 45 denotes the display buffer 29 which is sequentially read from the address indicated by the read address register 242 in accordance with the display dot clock (the output of the DCLK terminal of the graphics processor 20 and the clock of one pixel of the display 51). Outputting the data to the display 51,
Update the read address register 242.

On the other hand, the graphics memory access control section 240 is activated by the graphics memory access trigger signal, and the number of continuous access words (for example, 3
2 words / 64 words)
The graphics memory 40 is read through the memory controller 30 and the read data is displayed in the display buffer 29.
Write to. The write address is specified from the write address register 241.

The write address register 241 and the read address register 242 are always subtracted by a subtractor 243, and the difference value is compared with a constant value by a comparator 244. That is, when the difference value becomes equal to or less than the set constant value (for example, 12 words / 48 words), the trigger signal is output, and the graphics memory access control unit 240 accesses the graphics memory 40 for display, The display data is stored in the display buffer 29.

FIG. 9 is a time chart showing the above operation. The first operation of the display access to the graphics memory 40 is started by the HSYNC signal.
With this display access, the number of data held in the display buffer 29 increases, and when the number of continuous access words (32 words in the figure) read in one display access is reached, the display access is interrupted and the display stored in the buffer 29 is stopped. The data is transferred to the display 51 and gradually decreases. Then, when the number decreases below the constant A (12 words in the figure),
A display access request is issued from the display controller 24 to the memory controller 30. When the request is permitted, the display access to the graphics memory 40 is performed again. In this example, one screen is 320 × 24
In the case of 0 dot, display access is repeated 1200 times for displaying one screen.

Since writing to the display buffer 29 is faster than reading, there is ample time from when a display access request signal is issued to when display access is started. The illustrated display access delay time Td corresponds to this, and if the display access is not started even after the elapse of Td, the display buffer 29 becomes empty and the screen of the display device 51 is disturbed. As described above, the memory controller 30 gives the highest priority to the display access, but if another access such as the CPU is being executed at the time of the request, the display access waits until the end.

Therefore, in order to prevent the display buffer 29 from being emptied, it is necessary to maintain the relationship of another access time Ta <Td of the graphics processor 40. The constant A is determined from the maximum time of Ta.

Accesses from other sources, in particular, write accesses of drawing commands by the CPU 10 are frequent, and their access times differ depending on the cache system, and differ at most about four times between the copy-back system and the write-through system.

FIG. 10 is a time chart showing an operation of an example in which Ta is quadrupled as compared with FIG. The constant B for issuing the display access request is 48 words, which is four times the constant A. In addition, the number of continuous words read in one display access also increases, and in this example, the number is 64 words.
Incidentally, the display access for one screen in this example is 6
00 times.

In this embodiment, as shown in FIG. 8, the display controller 24 sets two constants, A = 12 and B = 48, in the comparator 244, and sets the number of continuous access words to be set in the graphics memory access control unit 240. A = 32,
b = 64 are prepared, and are selected in accordance with the designation of the CAM bit (FIG. 4) of the above-described system control register according to the cache system of the CPU 10. That is, if the value of the CAM bit indicates the copy-back method, the values of A and a are selected, and if the value of the CAM bit indicates the write-through method, the values of B and b are selected.

According to this, when the CPU adopts the copy-back method, the CPU is one unit smaller than in the case of the write-through method.
Display access time can be reduced to 1/4 and CP
Since the number of U write accesses can be increased, high-speed graphics can be realized without using a high-speed memory system.

Further, since it is possible to cope with different cache systems only by switching the CAM bit value, the versatility of the graphics processor is enhanced. Further, in a system in which the graphics memory is written by a plurality of CPUs having different cache schemes, the display access scheme of the graphics processor is switched according to the cache scheme of the CPU that issued the write access.
There is no sacrifice of graphics due to the high-speed cache method.

[0077]

According to the present invention, it is possible to efficiently access the graphics memory by setting the difference in the cache system of the CPU for the graphics processor. Therefore, the speed of the graphics display processing can be increased.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a graphic processing apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a terminal function of the graphics processor.

FIG. 3 is an explanatory diagram of a drawing command of the graphics processor.

FIG. 4 is an explanatory diagram of a graphics processor register function.

FIG. 5 is a functional block diagram of a CPU FIFO.

FIG. 6 is a functional block diagram of a drawing cache (3).

FIG. 7 is an explanatory diagram of CPU address mapping.

FIG. 8 is a configuration diagram of a display controller.

FIG. 9 is a time chart showing an example of access to a graphics memory and control of a display buffer.

FIG. 10 is a time chart showing another example of access to the graphics memory and control of the display buffer.

[Explanation of symbols]

10 CPU, 11 main memory, 20 graphics processor, 21 CPU I / F, 22 parameter converter, 23 drawing unit, 24 display controller,
25: CPU FIFO, 26: Cache (1), 27
... Cache (2), 28 ... Cache (3), 29 ...
Display buffer, 30: memory controller, 40: graphics memory, 50: DAC (Digital to Analog)
Converter), 51: display unit, 101: CPU built-in cache, 320: CAM bit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/18 G06F 15/72 A

Claims (5)

[Claims] 1. A CPU for generating drawing procedure information including a type of a graphics figure to be displayed, a vertex parameter, and the like, and storing the drawing procedure information written from the CPU and drawing data to be output to a display. A memory and a graphics processor for performing drawing access to the drawing procedure information, storing drawing data in the memory, and further performing display reading for outputting the drawing data to the display device, wherein the CPU and the graphics processor A graphics display device that accesses the memory from both of them. The graphics processor reads and displays the graphics memory according to a cache system of a cache memory provided in the CPU and transferring data to the graphics memory. Thailand Graphics display device characterized by varying the ring. 2. The graphics processor according to claim 1, wherein the graphics processor determines whether the cache system transfers a plurality of words of data to the graphics memory continuously or by word. A graphics display device, wherein cache system information is provided from the CPU, and in the former case, the continuous time of one display reading is shortened as compared with the latter. 3. A graphics memory having an area for storing drawing procedure information including a type of a graphics figure to be displayed and a vertex parameter and an area for storing bitmap information to be output to a display device. In a graphics processor that performs drawing access for generating bitmap information and display access for outputting display data to a display, a write access of the drawing procedure information to the graphics memory continuously performs data of a plurality of words. A transfer method is set which indicates whether transfer is to be performed by an address or a transfer method for each word. In the former case, the continuous time of one display access is shortened compared to the latter. Processor. 4. The graphics processor according to claim 3, wherein the graphics processor comprises: a rendering unit for performing the rendering access; a display controller for performing the display access; and interface means for receiving data transfer from a CPU and performing the write access; A memory controller for receiving the memory access request and controlling the display access with priority; setting the transfer mode information according to a cache mode of the CPU for transferring the drawing procedure information; In the graphics processor, the continuous time of one display access is shortened as compared with the write-through system. 5. The display buffer according to claim 3, wherein the graphics processor temporarily stores bitmap information read from the graphics memory by the display access, and outputs the bitmap information according to a timing of a display. The number of continuous words by the one display access is set to the maximum value of the number of data held in the display buffer, the timing of issuing the display access request is set to a threshold value less than the number of data held, And a threshold value that changes according to the transfer method information.