JP2011199804A - Image display apparatus, projector, and data acquiring method in image display apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency of distortion correction processing of an image display apparatus.SOLUTION: The image processing apparatus includes: a frame video storage section; a block video storage section having a plurality of block region and storing the block video data; a correction processing section for generating corrected video data by using the block video data; a block video acquiring section for acquiring the block video data and storing the acquired data into the block video storage section; and an acquiring request issuing section for issuing an acquiring request including position information corresponding to a position, in a frame video, of a video represented by the block video data to be acquired. If position information included in the acquiring request issued during a predetermined period includes position information in which the coordinate positions of a first direction of the frame video are the same, the block video acquiring section continuously acquires the block video data representing the video shown by the position information from the frame video storage section.

Description

  The present invention relates to an image display device, a projector, and a data acquisition method in the image display device.

  In an image display device such as a projector, when an image is displayed on a display surface such as a screen, the image displayed on the display surface may be distorted due to, for example, the relative positional relationship between the projector and the display surface. In order to solve this problem, trapezoidal distortion correction is known in which an image distorted in a trapezoidal shape is corrected to a rectangular shape by using a projective transformation technique.

JP 2007-150531 A

  However, there is still room for improvement in the efficiency of distortion correction processing in the image display apparatus.

  The present invention has been made to solve at least a part of the above-described problems, and an object thereof is to improve the efficiency of distortion correction processing in an image display apparatus.

  A first aspect of the present invention provides an image display device. An image display apparatus according to a first aspect of the present invention includes a frame video storage unit that stores video data representing a frame video, and a plurality of block areas for storing block video data including a predetermined number of pixels, Using the block video storage unit that stores a part of the video data stored in the frame video storage unit as block video data in each block area, and the block video data stored in each block area, the frame video A correction processing unit that generates corrected video data representing a corrected frame video that has been subjected to predetermined correction, and obtains block video data from a part of the video data stored in the frame video storage unit, A block video acquisition unit for storing in the block area of the block video storage unit; and For the block video data to be acquired from the video data stored in the frame video storage unit, an acquisition request including position information corresponding to the position in the frame video of the video represented by the block video data to be acquired is sent to the block video An acquisition request issuing unit for issuing to the acquisition unit, wherein the block video acquisition unit includes a frame video in position information included in each of the acquisition requests issued from the acquisition request issue unit during a predetermined period. If the coordinate information in the first direction is equal to each other, block image data representing the image indicated by the position information is continuously acquired from the image data stored in the frame image storage unit. To do.

  According to the image display device according to the first aspect, when the position information included in the acquisition request issued in a predetermined period includes position information in which the coordinate positions in the first direction of the frame video are equal to each other In this case, since the block video data respectively corresponding to the position information is continuously acquired from the video data, the efficiency of the distortion correction process can be improved.

  In the image display device according to the first aspect, the block video acquisition unit is stored in the buffer unit for sequentially storing the acquisition requests issued from the acquisition request issuing unit, and in the buffer unit for the predetermined period. In response to the acquisition request, a rearrangement unit that rearranges the reading order of the acquisition requests so that acquisition requests including position information in which the coordinate positions of the frame images in the first direction are equal to each other are continuously read. An acquisition unit that reads out acquisition requests from the buffer unit according to the order rearranged by the replacement unit, and acquires block video data from video data stored in the frame video storage unit in response to the read acquisition request. It may be. In this case, in response to the acquisition request stored in the buffer unit during a predetermined period, the acquisition request including the position information in which the coordinate positions in the first direction of the frame image are equal to each other is continuously read. Since the readout order is rearranged and the block video data is acquired according to the rearranged order, the efficiency of the distortion correction processing can be improved.

  In the image display device according to the first aspect, the acquisition request issuing unit predicts block video data that the correction processing unit will later use to generate corrected video data, and the predicted block video data is the block video data. If it is not stored in any block area of the storage unit, the block video prediction unit that issues an acquisition request for acquiring the predicted block video data, or the correction processing unit performs the next correction It is determined whether the block video data used for generating the video data is stored in any block area of the block video storage unit, and the block video data is stored in any block area of the block video storage unit If not, at least one of the determination units that issue an acquisition request for acquiring the block video data One may also include one. In this case, since the acquisition request issuing unit issues an acquisition request when block video data used for generating corrected video data is not stored in the block video storage unit, the efficiency of distortion correction processing is improved. be able to.

  In the image display device according to the first aspect, the frame image has a rectangular outer shape in which a plurality of pixels are arranged in a predetermined number in the first direction and in a direction orthogonal to the first direction, and the block The video data includes pixel values of pixels constituting a partial region of the frame video, and the block video acquisition unit is configured to perform the acquisition based on the acquisition requests issued from the acquisition request issue unit during a predetermined period. When acquiring a plurality of block video data from the video data stored in the frame video storage unit, for all pixel values included in the plurality of block video data, upstream pixels in the first direction of the frame video You may acquire in order. In this case, the distortion correction processing can be performed with high accuracy by sequentially acquiring all pixel values included in the plurality of block video data from the upstream pixel in the first direction of the frame video.

  In the image display device according to the first aspect, the frame image has a rectangular outer shape in which a plurality of pixels are arranged in a predetermined number in the first direction and in a direction orthogonal to the first direction, and the block The video data includes pixel values of pixels constituting a partial region of the frame video, and the block video acquisition unit is configured to perform the acquisition based on the acquisition requests issued from the acquisition request issue unit during a predetermined period. When acquiring a plurality of block video data from the video data stored in the frame video storage unit, after acquiring all the pixel values included in one block video data from the frame video storage unit, the other block video data The pixel value included in may be acquired. In this case, it is possible to improve the efficiency of the distortion correction processing by acquiring pixel values included in other block video data after acquiring all the pixel values included in one block video data.

  A second aspect of the present invention provides a projector that projects and displays an image on a projection surface. A projector according to a second aspect of the present invention includes an image light output unit that generates and outputs image light representing the image, a frame image storage unit that stores image data representing a frame image, and a predetermined number of pixels. A plurality of block areas for storing block video data, and a block video storage unit for storing a part of the video data stored in the frame video storage unit in each block area as block video data, and each of the blocks Corrected video data representing a corrected frame image obtained by performing processing for correcting distortion of the image projected on the projection surface with respect to the frame image using block image data stored in an area And a correction processing unit that outputs to the video light output unit and a part of the video data stored in the frame video storage unit A block video acquisition unit that acquires lock video data and stores it in the block area of the block video storage unit, and block video data that the block video acquisition unit should acquire from the video data stored in the frame video storage unit An acquisition request issuing unit that issues an acquisition request including position information corresponding to a position in the frame video of the video represented by the block video data to be acquired to the block video acquisition unit, the block video In the acquisition unit, the position information included in each of the acquisition requests issued from the acquisition request issuing unit during a predetermined period includes position information in which the coordinate positions in the first direction of the frame image are equal to each other. The block video data representing the video indicated by the position information is stored in the frame video storage unit. To get continuously from that video data.

  According to the projector according to the second aspect, when the position information included in the acquisition request issued in a predetermined period includes position information in which the coordinate positions in the first direction of the frame image are equal to each other. Since the block video data corresponding to each of these position information is continuously acquired from the video data, it is possible to improve the efficiency of processing for correcting distortion of the video projected on the projection surface in the projector. it can.

  Note that the present invention can be realized in various modes, and can be realized by, for example, a projector television, a monitor, a block video storage device, a projection conversion processing device, an image processing device, or the like. Further, a data acquisition method, an image processing method, and a computer program for realizing the functions of these methods or apparatuses, a recording medium on which the computer program is recorded, and data embodied in a carrier wave including the computer program It can be realized in the form of a signal or the like.

It is explanatory drawing which shows a trapezoid distortion correction | amendment notionally. It is explanatory drawing which shows notionally the production method of the image data after correction | amendment. It is a figure which shows notionally the method of pixel interpolation. 1 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. 3 is a functional block diagram illustrating a configuration of a trapezoidal distortion correction unit 120. FIG. FIG. 6 is a process diagram schematically showing an operation flow of a trapezoidal distortion correction unit 120. It is explanatory drawing which shows the timing of each process when the trapezoid distortion correction part 120 calculates the pixel value of 1 pixel of the image | video after correction | amendment. 3 is a diagram schematically showing a relationship between a frame buffer 150 and a cache block storage unit 122. FIG. It is a figure which shows notionally the relationship between the cache block memory | storage part 122 and the tag information storage part 123 for cache blocks. It is a figure which shows the relationship between a cache block and an interpolation block. It is explanatory drawing for demonstrating the prefetch determination in the prefetch request issuing part. It is explanatory drawing for demonstrating the order in which the cache block stored in the cache block memory | storage part 122 is updated. It is explanatory drawing which shows the example of the hit determination using tag information. It is process drawing which shows the process of a hit determination process typically. It is process drawing which shows the process of a hit determination process typically. 3 is a functional block diagram illustrating a configuration of a cache block control unit 121. FIG. It is explanatory drawing for demonstrating rearrangement of the read request by the buffer read control part 137. FIG. FIG. 10 is an explanatory diagram for explaining a cache block read order by a cache block acquisition unit 138; FIG. 11 is an explanatory diagram for explaining a reading order of pixel values of pixels included in a cache block by a cache block acquisition unit 138.

Hereinafter, a projector which is one embodiment of the present invention will be described in the following order based on embodiments with reference to the drawings.
A. First embodiment:
A-1. Keystone correction:
A-2. Projector configuration:
A-3. Keystone distortion correction section:
A-4. Prefetch determination:
A-5. Hit judgment:
A-6. Cache block controller:
B. Variations:

A. First embodiment:
A-1. Keystone correction:
The projector 100 as one embodiment of the present invention projects image light representing an image and displays the image on a projection surface such as a screen SC. The projector 100 is a projector capable of correcting a trapezoidal distortion of a video displayed on the screen SC and displaying a rectangular video when a rectangular video is input. Here, the trapezoidal distortion means that an image displayed on the projection surface is distorted into a trapezoid, a parallelogram, other quadrilaterals, or the like due to the relative positional relationship between the projector and the projection surface. Prior to the description of the configuration of the projector 100, trapezoidal distortion correction in the projector 100 of the present embodiment will be briefly described.

  FIG. 1 is an explanatory diagram conceptually showing trapezoidal distortion correction. As shown in the figure, when the projector 100 is arranged with an inclination in the horizontal direction (left-right direction) and the vertical direction (up-down direction) with respect to the screen SC, it is displayed on the liquid crystal panel unit 192. The video (pre-correction video IG0) is rectangular, whereas the video PIG0 projected on the screen SC has a trapezoidal distortion in each of the horizontal and vertical directions. In FIG. 1, for convenience of explanation, the liquid crystal panel unit 192 included in the projector 100 is displayed outside the projector 100.

  The projector 100 uses a projective transformation technique to form an image (corrected image IG1) distorted in the opposite direction to the image projected on the screen SC on the liquid crystal panel unit 192, thereby forming the image on the screen SC. A rectangular image PIG1 is displayed (FIG. 1). Here, correction that is performed in order to make an image having trapezoidal distortion appear rectangular (the shape of an image that should be originally displayed) is referred to as “trapezoidal distortion correction”. The trapezoidal distortion correction in this embodiment corresponds to “predetermined correction” in the claims.

  FIG. 2 is an explanatory diagram conceptually showing a method of creating corrected video data. FIG. 2A shows a pre-correction image IG0. FIG. 2B shows the corrected image IG1. The broken line in FIG. 2B shows the outer shape of the pre-correction image IG0. Since the pre-correction video IG0 has been subjected to video processing so as to be displayed on the full frame of the liquid crystal panel unit 192, the broken line in FIG. 2B indicates the frame of the liquid crystal panel unit 192.

  In this embodiment, the coordinates of the pre-correction video IG0 and the post-correction video IG1 refer to pixel coordinates when the pre-correction video IG0 and the post-correction video IG1 are displayed on the liquid crystal panel unit 192. Hereinafter, the pixel coordinates of the liquid crystal panel unit 192 when the corrected image IG1 is displayed are referred to as corrected coordinates. Of the pixel coordinates of the liquid crystal panel unit 192, the pixel coordinates of the area where the corrected image IG1 is not displayed are also referred to using the corrected coordinates. The coordinates obtained by converting the corrected coordinates to the coordinate positions (pixel coordinates of the liquid crystal panel) in the pre-correction video IG0 by reverse projection conversion are referred to as pre-correction coordinates.

  An outline of a method of creating corrected video data representing the corrected video IG1 will be described with reference to FIG. The projector 100 generates post-correction video data by obtaining pixel values (R, G, and B values) of all pixel coordinates constituting the post-correction video IG1 based on the pixel values of the pre-correction video IG0. To do. As an example, a method of obtaining the pixel value of the coordinate P1 (X, Y) surrounded by the middle square of the corrected image IG1 shown in FIG.

  First, the projector 100 converts the corrected coordinates P1 (X, Y) of the pixel whose pixel value is to be obtained into the uncorrected coordinates P0 (x, y). At this time, since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the calculated pre-correction coordinates P0 (x, y) include decimals. Therefore, the projector 100 estimates the pixel value of the pre-correction coordinates P0 (x, y) using the pixel values of 16 coordinates in the vicinity of the corresponding pre-correction coordinates P0 (x, y). This estimation of the pixel value is also called pixel interpolation. Accordingly, the projector 100 reads out the pixel block near the pre-correction coordinate P0 (x, y) based on the converted pre-correction coordinate P0 (x, y) including the decimal point, and applies a filter coefficient to the read pixel block. Is used to perform pixel interpolation. Thereby, the projector 100 calculates the pixel value of the coordinate P1 (X, Y) of the corrected image IG1. That is, the projector 100 calculates the pixel values of all the pixels (coordinates) constituting the corrected image IG1 by performing the pixel interpolation for each pixel, and the corrected image data representing the corrected image IG1. Is generated.

  FIG. 3 is a diagram conceptually illustrating a pixel interpolation method. FIG. 3 illustrates a method of obtaining a pixel value corresponding to the pre-correction coordinate P0 (x, y) obtained by converting the post-correction coordinate P1 (X, Y) by pixel interpolation. In the figure, the position of the pre-correction coordinates P0 (x, y) is indicated by hatched circles, and the positions of the surrounding 16 coordinates are indicated by white circles. Since the pixel value corresponding to the pre-correction coordinate P0 (x, y) is obtained by pixel interpolation, the pixel value corresponding to the pre-correction coordinate P0 (x, y) is set to “interpolated pixel” and the pre-correction coordinate P0 (x, y). ) The pixel values of the surrounding 16 pixels are pre-correction video data and are known, so they are also referred to as “known pixels”.

  In FIG. 3, pixel values of 16 pixels that are known pixels are represented by DATA [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction). ). The interpolation pixel is obtained by a convolution operation of the pixel value of 16 pixels and the filter coefficient. The filter coefficient takes into account the influence of the distance between the interpolation pixel and the known pixel (for example, the distance between the known pixel of DATA [1] [1] and the interpolation pixel is dx in the x direction and dy in the y direction). It is a coefficient and is determined for each known pixel. In FIG. 3, the filter coefficients are indicated as COEF [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction)). In this embodiment, a two-dimensional filter coefficient is used, but the filter coefficient may be decomposed into one dimension.

A-2. Projector configuration:
FIG. 4 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. As illustrated, the projector 100 includes a video input unit 110, an IP conversion unit 112, a resolution conversion unit 114, a video synthesis unit 116, a trapezoidal distortion correction unit 120, a liquid crystal panel drive unit 140, and a frame buffer 150. A high-speed bus control unit 160, a low-speed bus control unit 162, a processor unit 170, an imaging unit 180, a sensor unit 182, an illumination optical system 190, a liquid crystal panel unit 192, and a projection optical system 194. Prepare. Each component other than the illumination optical system 190, the liquid crystal panel unit 192, and the projection optical system 194 is connected to each other via the high-speed bus 102 or the low-speed bus 104.

  The video input unit 110 performs A / D conversion on an input video signal input from a DVD player or personal computer (not shown) via a cable, if necessary, and supplies the digital video signal to the IP conversion unit 112.

  The IP conversion unit 112 executes processing for converting the format of the video data supplied from the video input unit 110 from the interlace method to the progressive method, and supplies the obtained video data to the resolution conversion unit 114.

  The resolution conversion unit 114 performs a size enlargement process or a reduction process (that is, resolution conversion process) on the video data supplied from the IP conversion unit 112, and supplies the obtained video data to the video synthesis unit 116. To do.

  The video composition unit 116 synthesizes the video data supplied from the resolution conversion unit 114 and an OSD (On Screen Display) such as a menu screen, and writes the resultant data in the frame buffer 150 as pre-correction video data.

  The frame buffer 150 can store data of one frame or a plurality of frames. In this embodiment, an inexpensive and large-capacity DRAM (Dynamic Random Access Memory) is used as the frame buffer 150. The frame buffer 150 in this embodiment corresponds to a “frame video storage unit” in the claims.

  The trapezoidal distortion correction unit 120 corrects trapezoidal distortion that occurs when projection is performed with the projection axis of the projector 100 tilted with respect to the screen SC. Specifically, in order to display the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 on the liquid crystal panel unit 192 in a shape that compensates for trapezoidal distortion, the correction processing is performed on the pre-correction video data. The corrected video data is supplied to the liquid crystal panel driving unit 140. The trapezoidal distortion correction unit 120 will be described in detail later with reference to FIG.

  The liquid crystal panel drive unit 140 drives the liquid crystal panel unit 192 based on the digital video signal input through the trapezoidal distortion correction unit 120. The liquid crystal panel unit 192 includes a transmissive liquid crystal panel in which a plurality of pixels are arranged in a matrix. The liquid crystal panel unit 192 is driven by the liquid crystal panel driving unit 140, and changes the light transmittance in each pixel arranged in a matrix, thereby changing the illumination light emitted from the illumination optical system 190 to an effective image. An image for modulation into a new image light is formed. In this embodiment, the mode of the liquid crystal panel unit 192 is WUXGA, and the resolution is 1920 × 1200 dots. In this embodiment, the liquid crystal panel pixel coordinates are defined as x = 0 to 1919 and y = 0 to 1199. The liquid crystal panel unit 192 may have a resolution different from that of this embodiment.

  The illumination optical system 190 includes, for example, lamps such as a high pressure mercury lamp and an ultrahigh pressure mercury lamp, and other light emitters. The projection optical system 194 is attached to the front surface of the housing of the projector 100, expands the light modulated into the image light by the liquid crystal panel unit 192, and projects it onto the screen SC. The projection optical system 194 includes a zoom lens (not shown), and can change the degree of enlargement (zoom state) when projecting light transmitted through the liquid crystal panel unit 192. The liquid crystal panel driving unit 140, the liquid crystal panel unit 192, the illumination optical system 190, and the projection optical system 194 in this embodiment correspond to the “image light output unit” in the claims.

  The processor unit 170 controls the operation of each unit in the projector 100 by reading and executing a control program stored in a storage unit (not shown). Further, corrected coordinates (X0 to X3, Y0 to Y3) described later based on the captured image captured by the imaging unit 180, the tilt of the projector 100 detected by the sensor unit 182 and the instruction from the user (FIG. 2), a conversion coefficient (described in detail later) of the coordinate conversion matrix is calculated and output to the trapezoidal distortion correction unit 120. In this embodiment, the processor unit 170 is configured to receive an instruction from the user through an operation panel (not shown) provided in the main body of the projector 100. For example, the instruction from the user through a remote control is controlled by the remote controller. The processor unit 170 may receive the instruction from the user via the low-speed bus 104.

  The imaging unit 180 includes a CCD camera, and captures an image displayed on the screen SC by the projector 100 to generate a captured image. The captured image generated by the imaging unit 180 is stored in a captured image memory (not shown). Note that the imaging unit 180 may have another imaging device instead of the CCD camera.

  The sensor unit 182 can detect the tilt angle formed by the CCD optical axis of the imaging unit 180 and the horizontal plane by detecting the tilt of the projector 100 from the vertical direction.

A-3. Keystone distortion correction section:
As described above, the trapezoidal distortion correction unit 120 generates post-correction video data in which the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 is corrected to a shape that compensates for trapezoidal distortion. FIG. 5 is a functional block diagram illustrating a configuration of the trapezoidal distortion correction unit 120. The trapezoidal distortion correction unit 120 includes a cache block control unit 121, a cache block storage unit 122, a cache block tag information storage unit 123, an interpolation block reading unit 124, a pixel interpolation unit 125, a FIFO unit 126, and a register. A unit 127, a control unit 128, a coordinate conversion unit 129, a filter coefficient calculation unit 130, a hit determination unit 131, and a prefetch request issuing unit 132.

  The cache block control unit 121 acquires part of the pre-correction video data stored in the frame buffer 150 in units of cache blocks including 8 × 8 pixels and stores the acquired data in the cache block storage unit 122. Hereinafter, the cache block represents video data including a pixel value of 8 × 8 pixels. In addition, the cache block control unit 121 updates tag information described later stored in the cache block tag information storage unit 123. The cache block control unit 121 acquires the cache block specified by the hit determination unit 131 or the prefetch request issuing unit 132 from the frame buffer 150. Specific processing for acquiring the cache block designated by the hit determination unit 131 or the prefetch request issuing unit 132 from the frame buffer 150 will be described later with reference to FIGS. The cache block control unit 121 in this embodiment corresponds to a “block video acquisition unit” in the claims.

  The cache block storage unit 122 stores a part of the pre-correction video data for one frame stored in the frame buffer 150 in units of cache blocks each including 8 × 8 pixels. The cache block storage unit 122 includes a plurality of block areas that can store one cache block. In this embodiment, as will be described in detail later, the cache block storage unit 122 includes a block area of 240 columns × 4 rows. In the present embodiment, the cache block storage unit 122 is configured by a small-capacity and high-speed SRAM (Static Random Access Memory), and the SRAM uses a 1-port RAM to read and write as will be described in detail later. Can be performed simultaneously. The cache block storage unit 122 in this embodiment corresponds to a “block video storage unit” in the claims. In this embodiment, a block area group of 1 column × 4 rows in the cache block storage unit 122 is also referred to as a block area column. That is, the cache block storage unit 122 in the present embodiment has a configuration in which block region columns are arranged in 240 columns in parallel.

  The cache block tag information storage unit 123 includes information on whether or not a cache block is stored for each block area constituting the cache block storage unit 122, information for specifying the stored cache block, etc. Stores tag information which is information for managing the block area. Specific contents of the tag information will be described later with reference to FIG.

  The interpolation block reading unit 124 reads out an interpolation block composed of 4 × 4 pixels necessary for pixel interpolation in the pixel interpolation unit 125 from the cache block storage unit 122 and supplies it to the pixel interpolation unit 125. The position where the interpolation block reading unit 124 reads the interpolation block from the cache block storage unit 122 will be described later with reference to FIG.

  The pixel interpolation unit 125 performs pixel interpolation processing based on the interpolation block supplied from the interpolation block reading unit 124 and the filter coefficient supplied from the filter coefficient calculation unit 130 to obtain the pixel value of the interpolation pixel. The method by which the pixel interpolation unit 125 calculates the pixel value of the interpolation pixel is as described above with reference to FIGS. The pixel interpolation unit 125 calculates the pixel value of one interpolation pixel from one interpolation block and the filter coefficient. In the present embodiment, the pixel interpolation unit 125 first calculates the pixel value of the most upstream pixel (upper left in FIG. 2B) in both the x direction and the y direction of the corrected video, and thereafter, FIG. The pixel values are sequentially calculated for the pixels on the downstream side in the x direction according to the arrow direction. When the pixel value of the pixel on the most downstream side in the x direction is calculated, the pixel value is calculated in order from the pixel on the most upstream side in the x direction in the same way for a column on the downstream side in the y direction. This is sequentially repeated, and the corrected video data representing the corrected video is generated by calculating up to the pixel value of the most downstream pixel in both the x and y directions. The generated corrected video data is output to the liquid crystal panel driving unit 140 (FIG. 4) via the FIFO unit 126. The interpolation block reading unit 124 and the pixel interpolation unit 125 in this embodiment correspond to a “correction processing unit” in the claims.

  The register unit 127 stores parameters supplied from the processor unit 170. Specifically, the register unit 127 stores parameters such as the frame width and frame height of one frame of the pre-correction video, and the transformation coefficients A to H of the coordinate transformation matrix. The conversion coefficients A to H are calculated by the processor unit 170 using the following determinant (formula 1) of projective transformation. Specifically, the processor unit 170 converts the uncorrected coordinates (x0 to x3, y0 to y3) (see FIG. 2) into the corrected coordinates (X0 to X3, Y0 to Y3) (see FIG. 2) by projective transformation. As converted, the four coordinates (X0 to X3, Y0 to Y3) of the corrected image IG1 are input to the determinant (Formula 1) to derive the coefficients A to H.

  In this embodiment, before the correction image data generation process is started, the image PIG0 displayed on the screen SC before the trapezoidal distortion correction is imaged by the imaging unit 180. The processor unit 170 (FIG. 4) obtains the coordinates (X0 to X3, Y0 to Y3) (FIG. 2B) of the four vertices in the corrected image IG1 after the trapezoidal distortion correction based on the captured image. Yes.

  Note that the sensor unit 182 may detect the inclination of the projector 100 from the vertical direction, and obtain corrected coordinates (X0 to X3, Y0 to Y3) based on the detected angle. Also, the keystone distortion correction may be performed manually by the user operating the remote controller. In such a case, the processor unit 170 obtains corrected coordinates (X0 to X3, Y0 to Y3) based on an instruction from the user received via the remote control unit.

  The control unit 128 performs overall control of the trapezoidal distortion correction unit 120. For example, a frame start signal indicating the start of a frame is output to the coordinate conversion unit 129 in accordance with the synchronization signal input to the control unit 128. For example, when 60 frames are displayed per second, the synchronization signal is input every 1/60 seconds.

  The coordinate conversion unit 129 uses the coordinate conversion coefficients A to H supplied from the register unit 127 and the following (Expression 2) and (Expression 3) to correct the coordinates of the corrected image IG1 after performing the trapezoidal distortion correction. The value (coordinate after correction) is converted into the coordinate value (coordinate before correction) of the pre-correction video IG0 (rectangular video). Since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the pre-correction coordinates calculated by the coordinate conversion unit 129 include decimals. The coordinate conversion unit 129 divides the coordinates before correction into an integer part and a decimal part, supplies the integer part to the hit determination unit 131 and the prefetch request issuing unit 132, and supplies the decimal part to the filter coefficient calculation unit 130.

  Here, the above-described calculation method of the pre-correction coordinates will be described. Since the corrected image IG1 is considered to be an image obtained by projective transformation of the uncorrected image IG0, the uncorrected coordinates are based on the following (Expression 2) and (Expression 3) with respect to the corrected coordinates. Then, it is calculated by reverse projective transformation. It is assumed that the uncorrected coordinates (x, y) are converted to corrected coordinates (X, Y) by projective transformation.

上記（式２）、（式３）中の係数Ａ〜Ｈは、レジスター部１２７に記憶されている。

The coefficients A to H in the above (Expression 2) and (Expression 3) are stored in the register unit 127.

  Based on the decimal part supplied from the coordinate conversion unit 129, the filter coefficient calculation unit 130 selects a filter coefficient used when executing the pixel interpolation process from the filter coefficient table, and selects the selected filter coefficient as a pixel. This is supplied to the interpolation unit 125. The filter coefficient table is a table showing the relationship between the distance between the interpolation pixel and the known pixel shown in FIG. 3 and the filter coefficient, and a result calculated in advance is stored in a memory included in the filter coefficient calculation unit 130.

  The hit determination unit 131 determines whether the pixel value of the coordinates used for pixel interpolation in the pixel interpolation unit 125 is stored in the cache block storage unit 122 based on the integer part of the coordinates before correction supplied from the coordinate conversion unit 129. Determine whether. Hereinafter, this determination is referred to as “hit determination”. As a result of the hit determination, when a pixel value necessary for pixel interpolation is not stored in the cache block storage unit 122, a request to read a necessary cache block is issued to the cache block control unit 121. As a result of the hit determination, when a pixel value necessary for pixel interpolation is stored in the cache block storage unit 122, the read position in the cache block storage unit 122 is supplied to the interpolation block reading unit 124. The flow of the hit determination process will be described later with reference to FIGS. The hit determination unit corresponds to the “determination unit” in the claims.

  The prefetch request issuing unit 132 predicts a cache block necessary for the subsequent pixel interpolation processing based on the integer part of the coordinates before correction supplied to the coordinate conversion unit 129. The prefetch request issuing unit 132 causes the cache block storage unit 122 to store the predicted cache block by issuing a read request for the predicted cache block to the cache block control unit 121. The prefetch request issuing unit 132 predicts a cache block necessary for the subsequent pixel interpolation process when the interpolation block reading unit 124 reads an interpolation block from a predetermined cache block. Specific processing by the prefetch request issuing unit 132 will be described later. The cache block prediction described above is also referred to as “prefetch determination”. The prefetch request issuing unit 132 corresponds to a “block video prediction unit” in the claims.

  The flow of the operation of each of the constituent parts constituting the trapezoidal distortion correcting part 120 will be briefly described. FIG. 6 is a process diagram schematically showing an operation flow of the trapezoidal distortion correction unit 120. First, the coordinate conversion unit 129 (FIG. 5) of the trapezoidal distortion correction unit 120 stands by until a frame start signal is input (step S102: NO), and when a frame start signal is input (step S102: YES). Then, the coordinates of the corrected image (corrected coordinates) are converted to obtain the coordinates before correction (step S104). The method for calculating the coordinates before correction by converting the coordinates after correction is as described above.

  The hit determination unit 131 (FIG. 5) supplies the interpolation block readout position to the interpolation block readout unit 124 based on the integer part of the coordinates before correction calculated by the coordinate conversion unit 129. The interpolation block reading unit 124 (FIG. 5) reads the interpolation block from the cache block storage unit 122 based on the supplied reading position (step S106). On the other hand, the filter coefficient calculation unit 130 (FIG. 5) selects a filter coefficient from the filter coefficient table based on the decimal part of the coordinates before correction obtained in step S104. The interpolation block readout process (also referred to as “block read”) in step S106 and the filter coefficient calculation process in step S108 are performed simultaneously. When both processes are completed, the process proceeds to the next process (step S110).

  The pixel interpolation unit 125 (FIG. 5) calculates the pixel value of the corrected coordinates using the interpolation block and the filter coefficient (step S110). Specifically, the pixel interpolation unit 125 uses the interpolation block supplied from the interpolation block reading unit 124 and the filter coefficient supplied from the filter coefficient calculation unit 130 to calculate the pixel value of the corrected coordinate by a convolution operation. calculate.

  The trapezoidal distortion correction unit 120 repeats the above steps S104 to S110 from the corrected coordinates (X, Y) = (0, 0) to (frame width−1, frame height−1). Generate corrected video data. In this embodiment, since the frame width is 1920 and the frame height is 1200, steps S104 to S110 are repeated until the corrected coordinates (X, Y) = (0, 0) to (1919, 1199). When the frame width and the frame height are different from those of the present embodiment, the steps S104 to S110 are performed after the corrected coordinates (X, Y) = (0, 0) to (frame width−1, frame height− By repeating the process up to 1), the corrected video data can be generated.

  FIG. 7 is an explanatory diagram showing the timing of each process when the trapezoidal distortion correction unit 120 calculates the pixel value of one pixel of the corrected image. When the coordinate conversion unit 129 receives the frame start signal output from the control unit 128, the coordinate conversion unit 129 starts coordinate conversion processing. When the coordinate conversion process is completed and the pre-correction coordinates are calculated, the filter coefficient calculation unit 130 starts the filter coefficient calculation process, and the hit determination unit 131 performs a tag information read process for hit determination. Start.

  When the hit determination unit 131 determines that the cache block including the area to be read by the interpolation block reading unit 124 is not stored in the cache block storage unit 122 as a result of performing the hit determination by reading the tag information, It waits for a cache block including an area to be read by the interpolation block reading unit 124 to be stored in the cache block storage unit 122 (hereinafter also referred to as “block write wait”).

  On the other hand, at the same time as the filter coefficient calculation process and the tag information reading process, the prefetch request issuing unit 132 determines whether or not prefetching of the cache block is necessary. , Also called “prefetch request”). When a cache block read request is issued from the hit determination unit 131 or the prefetch request issuing unit 132, the cache block control unit 121 reads the cache block from the requested position in the frame buffer 150 and stores it in the cache block storage unit 122. To do. When the cache block including the area to be read by the interpolation block reading unit 124 is stored in the cache block storage unit 122, the hit determination unit 131 stores the cache block including the area to be read by the interpolation block reading unit 124 in the cache block storage. The interpolation block reading unit 124 determines that the interpolation block is stored in the unit 122, and reads the interpolation block from the newly stored cache block.

  When the calculation of the filter coefficient and the reading of the interpolation block are completed, the pixel interpolation unit 125 starts pixel interpolation. In FIG. 7, the solid line frame indicates that the processing time is fixed, and the broken line frame indicates that the processing time is variable. Further, the length of the frame does not represent the length of processing. In this embodiment, the block write waiting time in the hit determination unit is shortened by making a prefetch request.

A-4. Prefetch determination:
Prior to the description of the prefetch determination in the prefetch request issuing unit 132, the relationship between the frame buffer 150, the cache block storage unit 122, and the cache block tag information storage unit 123 in this embodiment, and the relationship between the cache block and the interpolation block. This will be described in detail.

  FIG. 8 is a diagram schematically illustrating the relationship between the frame buffer 150 and the cache block storage unit 122. FIG. 8 shows a state where the pre-correction video data for one frame stored in the frame buffer 150 is divided into cache block units each consisting of 8 × 8 pixels. In this embodiment, the pre-correction video data stored in the frame buffer 150 is composed of 1920 × 1200 pixels, and such pre-correction video data is divided into 240 × 150 cache blocks. The position of each cache block in the pre-correction video data stored in the frame buffer 150 shown in FIG. 8 is the position of the video (region) represented by each cache block in the pre-correction video represented by the pre-correction video data. It corresponds to. In FIG. 8, the character string (x, y) described in each cache block indicates the position (column number, line number) in the x direction and y direction of the cache block. In this embodiment, the direction in which the columns are arranged is the x direction, and the direction in which the rows are arranged is the y direction. The y direction in the present embodiment corresponds to a “first direction” in the claims, and the x direction corresponds to a “direction orthogonal to the first direction” in the claims. In both the x direction and the y direction, the side of the cache block with the smaller character string (x, y) number is called the upstream side, and the side with the larger character string (x, y) number is called the downstream side.

  The cache block storage unit 122 includes 240 × 4 rows of block areas that can store one cache block. In FIG. 8, in order to identify each block area, numbers (column (0-239), row (0-3)) are given. That is, in the cache block storage unit 122, block region columns composed of four block regions (rows 0 to 3) arranged in the direction along the y direction are arranged in 240 columns (columns 0 to 239) in the direction along the x direction. It has a configuration. The cache block storage unit 122 can store 240 × 4 pieces of partial data (cache blocks) of pre-correction video data for one frame stored in the frame buffer 150.

  In this embodiment, when the trapezoidal distortion correction process is started, first, the cache blocks (0, 0) to (239, 3) are read from the frame buffer 150 and stored in the cache block storage unit 122. . The cache block is stored in the block area having the same column number as the column number of each cache block in the cache block storage unit 122. Therefore, when the trapezoidal distortion correction process is started, first, in each block area of the cache block storage unit 122, a cache block having a column number and a row number identical to the column number and line number of the block area is stored. (FIG. 8). The width of the cache block storage unit 122 is the same as the width of the frame buffer 150. The height of the cache block storage unit 122 is 4 cache blocks, and pixel data for 32 lines (4 cache blocks × 8 px) of one frame is stored. In the cache block storage unit 122, the cache blocks are sequentially stored in the order of the column numbers of the frame buffer 150, that is, from the upstream side to the downstream side in the x direction. Can do.

  The cache block tag information storage unit 123 stores tag information that is management information when the cache block storage unit 122 is managed in units of block areas. FIG. 9 is a diagram conceptually illustrating the relationship between the cache block storage unit 122 and the cache block tag information storage unit 123. As shown in the figure, the cache block tag information storage unit 123 stores 240 × 4 tag information corresponding to the 240 × 4 block areas of the cache block storage unit 122.

  Specifically, as tag information, (1) information indicating whether or not to wait for writing from the frame buffer 150 to the cache block storage unit 122 (WRITING = 1 in the case of waiting for writing), and (2) data in the block area is valid. (Valid = 1 when valid, valid = 0 when invalid), and (3) a coordinate Y_ADR indicating where in the frame buffer 150 the cache block stored in the block area is located Stored. The coordinate Y_ADR in (3) holds information in which the y coordinate in the frame buffer 150 of the upper left pixel of the cache block is 1/8. In this embodiment, the line number shown in FIG. 8 is set as the coordinate Y_ADR. In (2), “valid” indicates that the cache block is stored in the cache block storage unit 122, and “invalid” indicates that the cache block is not stored in the cache block storage unit 122. In this embodiment, at the start of the trapezoidal distortion correction process, before the cache blocks (0, 0) to (239, 3) are stored in the cache block storage unit 122, all tag information includes “invalid ( VALID = 0) ”.

  FIG. 10 is a diagram illustrating the relationship between the cache block and the interpolation block. In FIG. 10, the interpolation block is indicated by hatching. In this embodiment, since the cache block is composed of 8 × 8 pixels and the interpolation block is composed of 4 × 4 pixels, the interpolation block becomes a part of the cache block.

  As will be described later, the cache blocks stored in the cache block storage unit 122 are sequentially updated for each block area column as the trapezoidal distortion correction process proceeds. Therefore, during the trapezoidal distortion correction process, the cache blocks of the frame buffer 150 corresponding to the cache blocks stored in the cache block storage unit 122 are stepped as shown in FIG. 10, for example.

  FIG. 11 is an explanatory diagram for explaining prefetch determination in the prefetch request issuing unit 132. In FIG. 11, the cache block (u, v), the cache block (u, v + 1), the cache block (u, v + 2), and the cache block (u, v + 3) of the video data before correction are the block areas of the cache block storage unit 122. It is assumed that (u, 0), block area (u, 1), block area (u, 2), and block area (u, 3) are stored.

  The prefetch request condition is that the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 is a row of cache blocks stored in each block area column of the cache block storage unit 122. This means that the cache block with the highest number has been entered. When a prefetch request is issued, the cache block control unit 121 reads out from the frame buffer 150 a cache block having one row number larger than the cache block having the largest row number in each block area column, and the cache block storage unit Of the cache blocks stored in 122, the block area in which the cache block with the smallest row number is stored is overwritten.

  A specific example of the prefetch determination will be described with reference to FIG. The prefetch request issuing unit 132 has the input integer part Int (x, y) of the coordinates before correction, among the plurality of cache blocks stored in the block area column, the cache block (u, It is determined whether it is included in v + 3). When the integer part Int (x, y) is included in the cache block (u, v + 3), the prefetch request issuing unit 132 stores the cache block (u, v + 3) next to the cache block (u, v + 3) with the largest row number ( A read request for reading u, v + 4) from the frame buffer 150 is issued to the cache block control unit 121. In the read request, the coordinates in the frame buffer 150 of the block to be prefetched, that is, the row number and column number of the cache block, and the coordinate position of the cache block storage unit 122 that stores the cache block, that is, the row number and column of the block area Numbers etc. are included. When the cache block control unit 121 receives the read request, the block area (u, 0) in which the cache block (u, v) having the smallest row number among the cache blocks stored in the block area column is stored. In addition, the previously read cache block (u, v + 4) is overwritten.

  In this embodiment, the prefetch request issuing unit 132 and the cache block (u, v + 3) representing the most downstream area in the y direction of the frame buffer 150 among the cache blocks stored in the block area column and the pre-correction video , The cache block (u, v + 4) representing an adjacent area on the downstream side is predicted as a cache block from which the interpolation block reading unit 124 later acquires the interpolation block video data.

  Note that the prefetch request issuing unit 132 updates the tag information corresponding to the designated block area as well as issuing a read request. Specifically, WRITEING = 1 and Y_ADR is set to the coordinates (line number) of the cache block to be prefetched. Further, when the designated cache block is stored in the block area designated by the prefetch request, the prefetch request issuing unit 132 sets the corresponding tag information in the cache block tag information storage unit 123 to VALID = 1 and WRITEING = 0. Update.

  FIG. 12 is an explanatory diagram for explaining the order in which cache blocks stored in the cache block storage unit 122 are updated. FIG. 12 illustrates a cache block stored in the second block area column in the cache block storage unit 122. In FIG. 12, each cache block stored in the block area column is identified using the coordinates in the pre-correction video of the upper left pixel of each cache block. For example, a cache block whose coordinates in the pre-correction image of the upper left pixel are (16, 0) is indicated as a cache block (16, 0).

  FIG. 12A illustrates a cache block stored in each block area of the block area sequence at the start of the trapezoidal distortion correction process. Here, cache block (16, 0) is stored in block area (2, 0), cache block (16, 8) is stored in block area (2, 1), and block area (2, 2). The cache block (16, 16) is stored in, and the cache block (16, 24) is stored in the block area (2, 3). When the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 enters the cache block (16, 24), that is, the integer part of the input y coordinate is 24 to 31. In the case where the pre-read request is issued, the cache block (16, 32) is read from the frame buffer 150. Then, among the cache blocks stored in the second block area column of the cache block storage unit 122, the block area (2, 0) in which the cache block (16, 0) having the smallest y coordinate is stored. ) Is overwritten with the read cache block (16, 32) (FIGS. 12A and 12B).

  Thereafter, when the integer part Int (x, y) of the coordinates before correction input to the prefetch request issuing unit 132 enters the cache block (16, 32), that is, the integer part of the input y coordinate is 32 to 32. If it is 39, the next prefetch request is issued and the cache block (16, 40) is read from the frame buffer 150. Then, among the cache blocks stored in the second block area column of the cache block storage unit 122, the block area (2, 1) in which the cache block (16, 8) having the smallest y coordinate is stored. ) Is overwritten with the read cache block (16, 40) (FIGS. 12B and 12C).

A-5. Hit judgment:
FIG. 13 is an explanatory diagram illustrating an example of hit determination using tag information. FIG. 13 illustrates tag information corresponding to the cache block stored in the cache block storage unit 122 illustrated in FIG. That is, tag information related to the block area (2, 0) in the cache block storage unit 122 is stored in 2 columns and 0 rows of the cache block tag information storage unit 123. The 16 pixels used for pixel interpolation are (x [0], y [0]), (x [1], y [1]), (x [2], y [2]), ..., (x [15], y [15]), hit determination is performed pixel by pixel in order from (x [0], y [0]). For example, hit determination when (x [0], y [0]) = (16, 40) will be described with reference to FIG.

  When determining whether or not a cache block including (x [0], y [0]) = (16, 40) is stored in the cache block storage unit 122, first, the hit determination unit 131 uses the cache block The tag of the corresponding column is extracted from the tag information storage unit 123. Since one cache block is composed of 8 × 8 pixels, the corresponding column can be obtained by dividing the x coordinate of the pixel used for pixel interpolation by 8. Since (x [0], y [0]) = (16, 40) corresponds to the second column, the tag in the second column is extracted.

  In FIG. 13, the extracted tag information is described on the right side of the page. The hit determination unit 131 performs hit determination in ascending order of tag line numbers. Hereinafter, tag information is represented by TAG [line number]. TAG [0] is WRITEING = 0, VALID = 1, and Y_ADR = 4. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 4 is converted to the y coordinate of the pre-correction video, 4 × 8 = 32. That is, according to TAG [0], it can be seen that a block of y-coordinate = 32 of the pre-correction video exists in the cache block storage unit 122.

  TAG [1] is WRITEING = 1, VALID = 0, and Y_ADR = 5. WRITEING = 1 indicates that prefetching is in progress, and VALID = 0 indicates that the data is invalid. When Y_ADR = 5 is converted into the y coordinate of the pre-correction video, 5 × 8 = 40. That is, according to TAG [1], it can be seen that the block of y-coordinate = 40 in the pre-correction video is being pre-read and can be read after a while.

  TAG [2] is WRITEING = 0, VALID = 1, and Y_ADR = 2. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 2 is converted to the y coordinate of the pre-correction video, 2 × 8 = 16. That is, according to TAG [2], it can be seen that the block of y coordinate = 16 of the pre-correction video exists in the cache block storage unit 122.

  TAG [3] is WRITEING = 0, VALID = 1, and Y_ADR = 3. WRITEING = 0 indicates that prefetching is not being performed, and VALID = 1 indicates that the data is valid. When Y_ADR = 3 is converted into the y coordinate of the pre-correction video, 3 × 8 = 24. That is, according to TAG [3], it can be seen that the block of y coordinate = 24 of the pre-correction video exists in the cache block storage unit 122.

  That is, as a result of determining whether or not a cache block including (x [0], y [0]) = (16, 40) is stored in the cache block storage unit 122, (x [0], y [0 ]) = (16, 40) is included in the prefetch, and after a while, it is determined that the cache block can be read.

  14 and 15 are process diagrams schematically showing the process of hit determination processing in the hit determination unit 131 (FIG. 5). When the integer part Int (x, y) of the coordinates before correction is input from the coordinate conversion unit 129 to the hit determination unit 131, the hit determination process in the hit determination unit 131 is started. Based on the integer part Int (x, y) of the uncorrected coordinates input from the coordinate conversion unit 129, the hit determination unit 131 coordinates (x [0], y [0]), (x [1], y [1]), (x [2], y [2]),..., (X [15], y [15]) are calculated (step S202). Subsequent processing includes coordinates (x [0], y [0]), (x [1], y [1]), (x [2], y [2]),. 15], y [15]).

  When the calculation of the coordinates of the surrounding 16 pixels is completed, the hit determination unit 131 reads the tag information (TAG [0], [1], [2], [3]) from the cache block tag information storage unit 123 (Step S1). In S204, it is determined whether Y_ADR of TAG [0] (that is, the line number of the cache block) is equal to y [0] / cache block height (8 px) (step S206). If they are the same (YES in step S206), the hit determination unit 131 determines whether or not WRITE [1] of TAG [0] is 1 (step S208). On the other hand, if they are not the same (NO in step S206), the process proceeds to step S216.

  If WRITEING = 1 in step S208, the process returns to step S204. If WRITEING = 0, the hit determination unit 131 determines whether VALID = 1 of TAG [0] is set (step S210). When VALID = 1, the hit determination unit 131 calculates the coordinates (column, row) of the cache block corresponding to the hit tag (step S212). On the other hand, if VALID = 0, the hit determination unit 131 reads the cache block (x [0] / cache block width (8 px), y [0] / cache block height (8 px)). Is output to the cache block control unit 121 (step S214).

  In steps S216, S226, and S236, processing similar to that in step S206 is performed for TAG [1], TAG [2], and TAG [3], respectively. In steps S218, S228, and S238, processing similar to that in step S208 is performed for TAG [1], TAG [2], and TAG [3], respectively. In steps S220, S230, and S240, processing similar to that in step S210 is performed for TAG [1], TAG [2], and TAG [3], respectively.

  That is, if the line number of the cache block included in the tag information is not the same as y [0] / 8, the first processing is performed from the tag information on the 0th line so that the same processing is performed on the next tag information. The tag information is determined in order of the line, the second line, and the third line. In steps S208, S218, S228, and S238, WRITEING = 1 means that the cache block is being written to the block area corresponding to the tag information, so that writing is completed, that is, WRITEING = 0. Until it is, reading and determination of tag information are repeated. If VALID = 1 in steps S210, S220, S230, and S240, it can be said that the cache block including the pixel value of the target coordinate exists (hits) in the cache block storage unit 122. The coordinates (column, row) of the corresponding cache block are calculated.

A-6. Cache block controller:
As described above, the cache block control unit 121 acquires the cache block specified in the read request issued by the hit determination unit 131 or the prefetch request issuing unit 132 from the frame buffer 150. FIG. 16 is a functional block diagram showing the configuration of the cache block control unit 121. The cache block control unit 121 includes a read request buffer 134, a buffer management tag unit 135, a buffer status determination unit 136, a buffer read control unit 137, and a cache block acquisition unit 138.

  The read request buffer 134 includes a storage area for storing a read request issued from the prefetch request issuing unit 132 or the hit determination unit 131. The buffer management tag unit 135 stores management information for managing read requests stored in the storage area of the read request buffer 134. The management information includes, for example, read request address information stored in the storage area of the read request buffer 134, order information indicating the order in which the read requests are stored in the storage area of the read request buffer 134, and a buffer read control unit. Information indicating whether or not the request is read by 137 is included. The read request buffer 134 corresponds to a “buffer unit” in the claims.

  The buffer state determination unit 136 receives the read request issued by the prefetch request issuing unit 132 or the hit determination unit 131 and stores the read request in the read request buffer 134. The buffer state determination unit 136 stores the read requests in the read request buffer 134 in the order in which they are issued. The buffer state determination unit 136 refers to the management information of the buffer management tag unit, and stores the received read request in an area other than the area where the read request that has not yet been read by the buffer read control unit 137 is stored. . When the received read request is stored in the read request buffer 134, the buffer status determination unit 136 updates the management information in the buffer management tag unit 135.

  The buffer read control unit 137 includes a wait counter (not shown) that can measure a predetermined period (time), and the order in which the cache block acquisition unit 138 reads the read requests stored in the read request buffer 134 during the predetermined period. Rearrangement is performed (hereinafter simply referred to as “reading order”). The buffer read control unit 137 reads the read request from the read request buffer 134 with reference to the buffer management tag unit 135 and stores the read request in which the read order is rearranged in the read request buffer 134. In the present embodiment, the read request that has been rearranged in the read order is stored in an area other than the area in which the read request before the rearrangement is stored in the read request buffer 134. A specific method of rearranging the reading order by the buffer reading control unit 137 will be described later with reference to FIG. The buffer read control unit 137 updates the management information of the buffer management tag unit 135 when the read order is rearranged. The buffer read control unit 137 corresponds to a “sorting unit” in the claims.

  The cache block acquisition unit 138 reads a read request from the read request buffer 134 in the order rearranged by the buffer read control unit 137. The cache block acquisition unit 138 reads the cache block specified in the read request that has been read from the frame buffer 150 and stores it in the block area of the cache block storage unit 122. The cache block acquisition unit 138 uses the position information indicating the position to read the cache block included in the read request, and the address indicating the position of the area where the pixel value of each pixel constituting the cache block is stored in the frame buffer 150. The cache block is read by reading the pixel value of each pixel value from the generated address. The cache block acquisition unit 138 corresponds to an “acquisition unit” in the claims.

  FIG. 17 is an explanatory diagram for explaining rearrangement of read requests by the buffer read control unit 137. FIG. 17 shows a read request stored in the read request buffer 134 during a predetermined period. In other words, the read requests issued by the prefetch request issuing unit 132 or the hit determining unit 131 in the predetermined period are shown in the order in which they are issued. Each read request is stored in the order of the storage in the read request buffer 134 at each address of the storage area constituting the read request buffer 134. “Column” and “Row” described in each read request in FIG. 17 are cache blocks that request reading from the respective cache blocks constituting the pre-correction video data for one frame stored in the frame buffer 150. Is the position information for specifying the column address and the column address and row address of the cache block requesting reading. For example, a read request including position information of “Column: 2 Row: 0” indicates that the coordinate position in the column direction (x direction) is “2” and the coordinate in the row direction (y direction) in the frame buffer 150 shown in FIG. This is a request for reading the cache block whose position is “0”, that is, the cache block (2, 0) from the frame buffer 150 and storing it in the block area of the cache block storage unit 122. As the column address and row address, for example, as shown in FIG. 12, the address of a storage area in which the pixel value of the upper left pixel of each cache block in the frame buffer 150 is stored may be used. Numbers 1 to 8 described on the right side of each read request indicate the order in which each read request is stored in the read request buffer 134.

  As shown in FIG. 17A, the buffer read control unit 137 first reads out the read requests stored in the read request buffer 134 with the oldest stored time, that is, first in a predetermined period. Read issued read request. In this embodiment, the read request with the oldest time stored in the read request buffer 134 is the first read request “Column: 0 Row: 0”, so the buffer read control unit 137 reads the read request “Column: “0 Row: 0” is read out. The read request that has been read is stored in a different storage area of the read request buffer 134.

  Thereafter, the buffer read control unit 137 searches the read request stored in the read request buffer 134 for a read request having the same row address as the first read request and having a continuous column address. In this embodiment, the buffer read control unit 137 has the same coordinate position in the Row direction (y direction) as the first read request “Column: 0 Row: 0”, and the coordinate position in the Column direction (x direction) is the same. The sequential read requests are searched from the read requests stored in the read request buffer 134. Of the read requests stored in the read request buffer 134, the fourth read request “Column: 1 Row: 0” is the first read request “Column: 0 Row: 0” and the row direction (y direction). The coordinate positions are both equal to “0”, and the first read request “Column: 0 Row: 0” and the coordinate position in the Column direction (x direction) are “0” and “1”. Further, the eighth read request “Column: 2 Row: 0” is equal to the first read request “Column: 0 Row: 0” and the coordinate position in the Row direction (y direction) is both “0”, and The fourth read request “Column: 1 Row: 0” and the coordinate position in the Column direction (x direction) are “1” and “2”. Therefore, as illustrated in FIG. 17B, the buffer read control unit 137 reads the fourth read request “Column: 1 Row: 0” from the read request buffer 134 and then the eighth read request “ “Column: 2 Row: 0” is read out. The read request that has been read is stored in a different storage area of the read request buffer 134 so as to be read in order following the first read request. The Row direction in the present embodiment corresponds to the “first direction” in the claims.

  Thereafter, the buffer read control unit 137 searches the read request stored in the read request buffer 134 for a read request having the same row address as the first read request. That is, here, unlike the above, a search is performed including a read request in which the Column address is not continuous. In the present embodiment, the buffer read control unit 137 searches the read request stored in the read request buffer 134 for a read request of “Row: 0”. Among the read requests stored in the read request buffer 134, the sixth read request “Column: 4 Row: 0” is “Row: 0”, and the coordinate position in the Row direction is equal to the first read request. . Therefore, as illustrated in FIG. 17C, the buffer read control unit 137 reads the sixth read request “Column: 4 Row: 0” from the read request buffer 134. The read request that has been read is stored in a different storage area of the read request buffer 134 so as to be read following the eighth read request. When the sixth read request “Column: 4 Row: 0” is read, all the read requests stored in the read request buffer 134 that include “Row: 0” in the position information are buffer read control units. It is read by 137.

  The buffer read control unit 137 reads all the read requests including “Row: 0” in the position information, and then stores the read requests stored in the read request buffer 134 without including “Row: 0” in the position information. Read the read request with the oldest stored time. In the present embodiment, since the second read request “Column: 0 Row: 1” corresponds, the buffer read control unit 137 reads the read request “Column: 0 Row: 1”. After that, the buffer read control unit 137 sets “Row: 1” to the position information in the same manner as the second read request in the same manner as the read order for the read request including “Row: 0” in the position information described above. Read about the read request that includes it. The buffer read control unit 137 repeats the above to read all the read requests stored in the read request buffer 134 during a predetermined period as shown in FIG. 17D, and the read request is read. The order is rearranged and stored in the read request buffer 134. The cache block acquisition unit 138 reads the read request in the order rearranged by the buffer read control unit 137. That is, the read requests shown on the left side of FIG. 17D are read in order from the oldest stored time of each read request according to the numerical order described on the left side of each read request.

  FIG. 18 is an explanatory diagram for explaining the order in which cache blocks are read by the cache block acquisition unit 138. FIG. 18 shows a state in which the pre-correction video data for one frame stored in the frame buffer 150 is divided into cache blocks as in FIG. The numbers shown inside each cache block indicate the order of reading by the cache block acquisition unit 138. In FIG. 18A, as a comparative example, the number corresponding to the read order shown in FIG. 17A, that is, the read order before the read requests are rearranged by the buffer read control unit 137, is shown for each cache. It is attached to the block. On the other hand, FIG. 18B shows the read order shown on the left side of the read request in FIG. 17D, that is, the read order after the read requests are rearranged by the buffer read control unit 137. A corresponding number is assigned to each cache block.

  As shown in FIG. 18A as a comparative example, the read order before the read requests are rearranged by the buffer read control unit 137, that is, the read request is issued from the prefetch request issuing unit 132 or the hit determining unit 131. When the cache blocks are read from the frame buffer 150 according to the order, the cache block acquisition unit 138 acquires cache blocks having the same row direction in a non-continuous manner. For example, the cache block acquisition unit 138 is first, fourth, for cache blocks (0,0), (1,0), (2,0), (4,0) whose Row direction is “0”. , Acquisition is performed in the order that is not continuous with the sixth and eighth.

  On the other hand, as shown in FIG. 18B, when the cache block is read from the frame buffer 150 according to the read order after the read requests are rearranged by the buffer read control unit 137, the cache block acquisition unit 138 Cache blocks with the same direction are acquired continuously. For example, the cache block acquisition unit 138 performs the first and second operations on the cache blocks (0, 0), (1, 0), (2, 0), and (4, 0) whose row direction is “0”. Acquisition is performed in the order of 3rd, 4th and consecutive. In addition, the cache block acquisition unit 138 includes cache blocks (0, 1) and (1, 1) whose row direction is “1”, and cache blocks (0, 2) and (1, 2) whose row direction is “2”. In the same manner, the acquisition is performed in the order of the fifth and the sixth and the order of the seventh and the eighth.

  When the coordinate position in the row direction of the cache blocks in which the acquisition order is continuous is not the same, the cache block acquisition unit 138 uses the cache for the address specified for acquiring the pixel value of each pixel constituting the cache block. An address is generated so that the pixel value is read out for each block. That is, when cache blocks having different coordinate positions in the Row direction are continuously acquired, first, among the 8 × 8 pixels constituting one cache block, the most upstream side in the Row direction (y direction). Addresses for acquiring pixel values of eight pixels constituting one row are generated. Thereafter, an address for acquiring the pixel values of the eight pixels constituting one column on the downstream side in the row direction (y direction) is generated. Addresses are similarly generated for the third to eighth stages in the Row direction (y direction). After that, among the 8 × 8 pixels constituting the second cache block, an address for obtaining the pixel values of the eight pixels constituting the most upstream line in the row direction (y direction) is generated. To do. The readout order of pixel values using addresses generated in the above order will be described later with reference to FIG.

  On the other hand, when the coordinate position in the row direction of the cache blocks having the same acquisition order is the same, the cache block acquisition unit 138 uses the address specified for acquiring the pixel value of each pixel constituting the cache block. The address is generated so that the pixel value is read out in each row direction across the cache block. That is, in the case where cache blocks having the same coordinate position in the Row direction are continuously acquired, the most upstream line in the Row direction (y direction) among the 8 × 8 pixels constituting each cache block is configured. The respective addresses for acquiring the pixel values of the eight pixels are continuously generated. Thereafter, the respective addresses for acquiring the pixel values of the eight pixels constituting one column downstream in the row direction (y direction) are successively generated. Similarly, the respective addresses are continuously generated for the third to eighth stages in the row direction (y direction). The readout order of pixel values using addresses generated in the above order will be described later with reference to FIG.

  FIG. 19 is an explanatory diagram for explaining the reading order of the pixel values of each pixel constituting the cache block by the cache block acquisition unit 138. FIG. 19A corresponds to FIG. 18A which is a comparative example, and FIG. 19B corresponds to FIG. In FIGS. 19A and 19B, in each cache block, the direction in which the pixel value of each pixel constituting the cache block is read is indicated by an arrow. When the coordinate positions in the row direction (y direction) of the cache blocks in which the reading order is continuous are different, the cache block acquisition unit 138 selects, among the 8 × 8 pixels constituting the cache block, the row in each cache block. In the direction (y direction), the pixel values of the eight pixels constituting one row on the most upstream side are read out along the Column direction, and when the reading for one row is completed, it is folded back and one column on the downstream side in the Row direction (y direction). Are read out. By repeating the same operation for the 3rd to 8th stages in the Row direction (y direction) by repeating the loop, reading of one cache block is completed.

  The cache block acquisition unit 138 does not perform read-back for each cache block with respect to a plurality of cache blocks having the same read direction (y direction) and consecutive read orders, but does not perform read-back for each cache block. Pixel values are read continuously across the cache blocks for pixels having the same position. When the reading of the pixel values for one line in the most downstream cache block in the Column direction (x direction) is completed, it is folded back in the Row direction (y direction) of the most upstream cache block in the Column direction (x direction). The pixel values of the pixels constituting one row downstream are read. By repeating this for the third to eighth stages in the Row direction (y direction), reading of a plurality of cache blocks having the same Row direction (y direction) is completed.

  In FIG. 18A, which is a comparative example, as described above, the reading order of cache blocks having the same row direction is not continuous. Therefore, as shown in FIG. 19A, the cache block acquisition unit 138 reads out the pixel value while turning back the line to be read out for each cache block. For example, the cache block acquisition unit 138 reads out each pixel constituting one row on the most upstream side in the row direction (y direction) of the cache block (0, 0), and then continuously reads the cache block (1,0). ) In the row direction (y direction) of the most upstream line, instead of reading from each pixel constituting the most upstream row, the second row in the row direction (y direction) of the cache block (0, 0) is folded. Read out from each pixel. The cache block acquisition unit 138 reads out each pixel constituting one row on the most upstream side in the row direction (y direction) of the cache block (1, 0), in the row direction (y direction) of the cache block (0, 2). ) And after reading from each pixel constituting one row on the most downstream side.

  On the other hand, in FIG. 18B, as described above, the reading order of the cache blocks having the same Row direction is continuous. Therefore, as illustrated in FIG. 19B, the cache block acquisition unit 138 continuously reads out pixel values across the cache blocks for pixels having the same position in the row direction (y direction). For example, the cache block acquisition unit 138 performs the row direction (y direction) in each cache block (0, 0), (1, 0), (2, 0), (4, 0) whose Row direction is “0”. For each pixel constituting the most upstream column, first, reading is performed from each pixel constituting the most upstream column of the cache block (0, 0), and then the cache block (1, 0) is continuously read. Reading is performed from each pixel constituting one column on the most upstream side. Thereafter, the cache block acquisition unit 138 continuously reads from the cache block (2, 0) and one column on the most upstream side of the cache block (4, 0). The cache block acquisition unit 138 reads out from each pixel constituting the second upstream column of the cache block (0, 0) after being read from the most upstream column of the cache block (4, 0). To do. The cache block acquisition unit 138 configures the most upstream column in the row direction (y direction) of the cache block (0, 1) after reading from the most downstream column of the cache block (4, 0). Read out from each pixel. As described above, the cache block acquisition unit 138 reads cache blocks from the frame buffer 150 according to the read order after the read requests are rearranged by the buffer read control unit 137.

  As described above, according to the projector 100 in the present embodiment, the position information included in the read request issued in a predetermined period includes position information with the same coordinate position in the Row direction of the frame buffer 150. If so, the cache blocks respectively corresponding to these pieces of position information are continuously acquired from the frame buffer 150, so that the efficiency of the distortion correction processing can be improved. Specifically, the frame buffer 150 constituted by a DRAM has a feature that when reading data from a storage area, the reading speed in the Row direction is slower than the reading speed in the Column direction. That is, when a column address and a row address are specified for the frame buffer 150 and data stored at the specified position is read, the specified row is compared with a case where the specified column address is changed and data is read. It takes longer to read data when the address is changed. According to the projector 100 according to the present invention, when the position information included in the read request includes position information having the same coordinate position in the row direction of the frame buffer 150, the position information corresponds to the position information. By continuously acquiring cache blocks from the frame buffer 150, the number of times to change the Row address can be reduced. As a result, the time required for reading the cache block can be suppressed, so that the efficiency of the distortion correction processing can be improved.

  According to the projector 100 in the present embodiment, the buffer read control unit 137 includes position information in which the positions of the frame buffer 150 in the Row direction are equal to each other with respect to the read request stored in the read request buffer 134 during a predetermined period. The read order of the read requests is rearranged so that the read requests are read continuously, and the cache block acquisition unit 138 acquires block video data according to the rearranged order, thereby improving the efficiency of the distortion correction processing. Can be planned. Specifically, the cache block acquisition unit 138 arranges the read order of the read requests so that the read requests including the position information having the same position in the row direction of the frame buffer 150 are continuously read, so that the cache block acquisition unit 138 can When generating an address for acquiring the pixel value of each pixel constituting the pixel, it is possible to generate an address so as to continuously acquire pixel values for pixels having the same Row address but different Column addresses. . Thereby, since the number of times of changing the Row address can be reduced, the efficiency of the distortion correction processing can be improved.

  According to the projector 100 in the present embodiment, the cache block acquisition unit 138 has a cache block having the same coordinate position in the Row direction (y direction) and a plurality of cache blocks whose reading order is continuous in the Row direction (y direction). The pixel values are continuously read out across the cache blocks for the pixels having the same coordinate position, and when the reading of the pixel values for one line in the cache block on the most downstream side in the column direction (x direction) is completed, the pixel values are returned. Since pixel values of pixels constituting one row on the downstream side in the direction (x direction) are read, it is possible to improve the efficiency of the distortion correction processing. Specifically, the cache block acquisition unit 138 includes a read request stored in the read request buffer 134 and includes an order in which the cache blocks having the same coordinate position in the row direction (y direction) are continuously read. When generating an address for acquiring the pixel value of each pixel constituting the cache block, the address is generated so that the pixel value is continuously acquired for pixels having the same Row address but different Column addresses. To do. Thereby, since the number of times of changing the Row address can be reduced, the efficiency of the distortion correction processing can be improved.

B. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

B1. Modification 1:
In the present embodiment, the cache block acquisition unit 138, for a plurality of cache blocks having the same row direction (y direction) and having a continuous read order, for each cache block having the same coordinate position in the row direction (y direction). Although pixel values are continuously read across blocks, even in the case where the reading order is continuous for cache blocks having the same coordinate position in the Row direction (y direction), the cache direction is changed in the Row direction (y direction). ), The pixel values of the pixels constituting one row on the most upstream side are read, and when the reading for one row is completed, the pixel values of the pixels constituting the second column in the Row direction (y direction) are read back. After the second cache block is read, the second cache block is read Out it may be configured to perform. Even in this case, after reading the first cache block, the bus right that controls the high-speed bus 102 is held without passing it to other functional units, and the second cache block is continuously held. By performing reading, the block write waiting time shown in FIG. 7 can be shortened, so that the efficiency of distortion correction processing can be improved.

B2. Modification 2:
In this embodiment, the buffer read control unit 137 stores the read request in which the read order is rearranged in an area other than the area in which the read request before the rearrangement is stored in the read request buffer 134. However, the read request buffer 134 does not include a storage area for storing the read requests that have been rearranged, and the buffer read control unit 137 sequentially reads the acquisition requests in the rearranged read order, The configuration may be such that each time the data is read, the data is transferred to the cache block acquisition unit 138. Even in this case, cache blocks having the same coordinate position in the Row direction of the frame buffer 150 can be continued from the frame buffer 150, so that the efficiency of distortion correction processing can be improved. In addition, the read request buffer 134 may be configured to overwrite the read request in which the read order is rearranged in the read request buffer 134 in an area in which the read request before the rearrangement is stored. Even in these cases, the efficiency of the distortion correction process can be improved.

B3. Modification 3:
In the present embodiment, the projector 100 includes the hit determination unit 131 and the prefetch request issuing unit 132, but may be configured not to include either one. Even in this case, since the read request is issued by at least one of them, the cache block can be read from the frame buffer 150 based on the read request and stored in the cache block storage unit 122.

B4. Modification 4:
The number of pixels of the frame buffer 150, the number of pixels of the cache block storage unit 122, the number of pixels of the cache block, and the number of pixels of the interpolation block (the number of pixels used for pixel interpolation) are not limited to the above-described embodiments, and are arbitrarily set. can do.

B5. Modification 5:
In this embodiment, the projector 100 modulates the light from the illumination optical system 190 using the transmissive liquid crystal panel unit 192, but is not limited to the transmissive liquid crystal panel unit 192. The light from the illumination optical system 190 is modulated using a micromirror device (DMD (registered trademark): Digital Micro-Mirror Device), a reflective liquid crystal panel (LCOS (registered trademark): Liquid Crystal on Silicon), or the like. You may make it the structure to carry out. Also, a CRT projector that projects an image on a small CRT (cathode ray tube) onto a projection surface may be used.

B6. Modification 6:
In the projector 100 according to the present embodiment, a part of the configuration realized by the hardware in the above embodiment may be replaced with software. Conversely, a part of the configuration realized by the software is replaced with the hardware. It may be replaced with wear.

B7. Modification 7:
The present invention can be realized in various modes, and can be realized by, for example, a projector television, a monitor, a block video storage device, a projection conversion processing device, an image processing device, or the like. Further, a data acquisition method, an image processing method, and a computer program for realizing the functions of these methods or apparatuses, a recording medium on which the computer program is recorded, and data embodied in a carrier wave including the computer program It can be realized in the form of a signal or the like.

DESCRIPTION OF SYMBOLS 100 ... Projector 102 ... High speed bus 104 ... Low speed bus 110 ... Video input part 112 ... IP conversion part 114 ... Resolution conversion part 116 ... Video composition part 120 ... Trapezoid distortion correction part 121 ... Cache block control part 122 ... Cache block memory | storage part 123 ... tag information storage unit for cache block 124 ... interpolation block reading unit 125 ... pixel interpolation unit 126 ... FIFO unit 127 ... register unit 128 ... control unit 129 ... coordinate conversion unit 130 ... filter coefficient calculation unit 131 ... hit determination unit 132 ... prefetching Request issuing unit 134 ... Read request buffer 135 ... Buffer management tag unit 136 ... Buffer state determination unit 137 ... Buffer read control unit 138 ... Cache block acquisition unit 140 ... Liquid crystal panel drive unit 150 ... Frame buffer 16 ... Fast bus control unit 162 ... low-speed bus control unit 170 ... processor 180 ... imaging unit 182 ... sensor unit 190 ... illumination optical system 192 ... liquid crystal panel unit 194 ... projection optical system

Claims (8)

An image display device,
A frame video storage unit for storing video data representing a frame video;
A block video storage unit comprising a plurality of block areas for storing block video data composed of a predetermined number of pixels, and storing a part of the video data stored in the frame video storage unit as block video data in each block area When,
A correction processing unit for generating corrected video data representing a corrected frame video obtained by performing a predetermined correction on the frame video using the block video data stored in each of the block areas;
A block video acquisition unit that acquires block video data from a part of video data stored in the frame video storage unit, and stores the block video data in the block area of the block video storage unit;
For the block video data to be acquired from the video data stored in the frame video storage unit by the block video acquisition unit, position information corresponding to the position in the frame video of the video represented by the block video data to be acquired An acquisition request issuing unit that issues an acquisition request including the block video acquisition unit,
The block image acquisition unit includes position information in which the coordinate positions in the first direction of the frame image are equal to each other in the position information included in each of the acquisition requests issued from the acquisition request issuing unit during a predetermined period. If so, block image data representing the image indicated by the position information is continuously acquired from the image data stored in the frame image storage unit. The image display device according to claim 1,
The block video acquisition unit
A buffer unit for sequentially storing the acquisition requests issued from the acquisition request issuing unit;
In response to the acquisition request stored in the buffer unit during the predetermined period, the acquisition request is continuously read out so that the acquisition request including position information in which the coordinate positions in the first direction of the frame image are equal to each other is read continuously. A rearrangement unit for rearranging the reading order;
An acquisition unit that reads out acquisition requests from the buffer unit according to the order rearranged by the rearrangement unit, and acquires block video data from video data stored in the frame video storage unit in response to the read acquisition request; An image display device comprising: The image display device according to claim 1 or 2,
The acquisition request issuing unit
When the correction processing unit predicts block video data to be used later for generation of corrected video data, and the predicted block video data is not stored in any block area of the block video storage unit, A block video prediction unit that issues an acquisition request for acquiring predicted block video data, or
The correction processing unit determines whether block video data to be used for generation of corrected video data next is stored in any block area of the block video storage unit, and the block video data is stored in the block video storage An image display device including at least one of a determination unit that issues an acquisition request for acquiring the block video data when the block video data is not stored in any block area. The image display device according to any one of claims 1 to 3,
The frame image includes a rectangular outer shape in which a plurality of pixels are arranged in a predetermined number in the first direction and in a direction orthogonal to the first direction,
The block video data includes pixel values of pixels constituting a partial area of the frame video,
When the block video acquisition unit acquires a plurality of block video data from the video data stored in the frame video storage unit based on each acquisition request issued from the acquisition request issuing unit in a predetermined period, An image display device that sequentially acquires all pixel values included in the plurality of block video data from an upstream pixel in the first direction of a frame video. The image display device according to any one of claims 1 to 3,
The frame image includes a rectangular outer shape in which a plurality of pixels are arranged in a predetermined number in the first direction and in a direction orthogonal to the first direction,
The block video data includes pixel values of pixels constituting a partial area of the frame video,
When the block video acquisition unit acquires a plurality of block video data from the video data stored in the frame video storage unit based on each acquisition request issued from the acquisition request issuing unit in a predetermined period, An image display device that acquires pixel values included in other block video data after acquiring all pixel values included in one block video data from the frame video storage unit. A projector that projects and displays an image on a projection surface,
An image light output unit for generating and outputting image light representing the image;
A frame video storage unit for storing video data representing a frame video;
A block video storage unit comprising a plurality of block areas for storing block video data composed of a predetermined number of pixels, and storing a part of the video data stored in the frame video storage unit as block video data in each block area When,
Correction representing a corrected frame image obtained by performing processing for correcting distortion of the image projected on the projection surface with respect to the frame image using block image data stored in each of the block areas. A correction processing unit that generates post video data and outputs the post video data to the video light output unit;
A block video acquisition unit that acquires block video data from a part of video data stored in the frame video storage unit, and stores the block video data in the block area of the block video storage unit;
For the block video data to be acquired from the video data stored in the frame video storage unit by the block video acquisition unit, position information corresponding to the position in the frame video of the video represented by the block video data to be acquired An acquisition request issuing unit that issues an acquisition request including the block video acquisition unit,
The block image acquisition unit includes position information in which the coordinate positions in the first direction of the frame image are equal to each other in the position information included in each of the acquisition requests issued from the acquisition request issuing unit during a predetermined period. A block video data representing a video indicated by the position information from the video data stored in the frame video storage unit. An image processing method in an image display device,
Storing video data representing a frame video;
Obtaining block video data from a portion of the video data and storing it in a block area;
Using the block video data stored in the block area, generating corrected video data representing a corrected frame video obtained by performing a predetermined correction on the frame video;
Issuing an acquisition request including position information corresponding to a position in the frame image of the image represented by the block image data to be acquired from the image data,
When the position information included in each of the acquisition requests issued in a predetermined period includes position information in which the coordinate positions in the first direction of the frame image are equal to each other, the image indicated by the position information is A method of continuously obtaining block video data to be represented from the video data. A frame video storage unit that stores video data representing a frame video and a plurality of block areas for storing block video data including a predetermined number of pixels, and a part of the video data stored in the frame video storage unit A method of acquiring data in an image display device comprising a block video storage unit that stores block video data in each block area,
Issuing an acquisition request including position information corresponding to a position in the frame image of the image represented by the block image data to be acquired from the image data;
Obtaining block video data from a part of the video data stored in the frame video storage unit in response to the acquisition request, and storing the block video data in the block area, and
When the position information included in each of the acquisition requests issued in a predetermined period includes position information in which the coordinate positions in the first direction of the frame image are equal to each other, the image indicated by the position information is A method of continuously obtaining block video data to be represented from the video data.

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