JPH0364049A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0364049A JPH0364049A JP19939489A JP19939489A JPH0364049A JP H0364049 A JPH0364049 A JP H0364049A JP 19939489 A JP19939489 A JP 19939489A JP 19939489 A JP19939489 A JP 19939489A JP H0364049 A JPH0364049 A JP H0364049A
- Authority
- JP
- Japan
- Prior art keywords
- header
- integrated circuit
- resin
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims abstract description 41
- 239000011347 resin Substances 0.000 claims abstract description 41
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 229920003023 plastic Polymers 0.000 abstract description 2
- 239000004033 plastic Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 17
- 230000000694 effects Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 238000005266 casting Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 102000003810 Interleukin-18 Human genes 0.000 description 1
- 108090000171 Interleukin-18 Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置、特にレジンが充填される封
止ケースで封止された混成集積回路装置の製造に適用し
て有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology that is effective when applied to the manufacture of hybrid integrated circuit devices, particularly hybrid integrated circuit devices sealed with a sealing case filled with resin. .
半導体装置のパッケージの一つとして、注型法（Ｃａ、
ｓｔｉｎｇ）がある、このキャスティング法については
、たとえば、工業調査会発行「電子材料Ｊ １９７３年
３月号、昭和４８年３月１日発行、Ｐ４８〜Ｐ５４に記
載されている。この文献には、ケースを用いるキャステ
ィング法とケースを用いないキャスティング法がある旨
記載されている。ケースを用いる封止方法の一つとして
、ケース内に樹脂を流し込み、ケース内に所望部分を封
止する方法が記載されている。また、ケースを用いない
キャスティング法として、一定量の樹脂を素子表面に滴
下させて硬化形成するドロッピング法、素子全体を樹脂
液中に浸漬し取出し後硬化させるディッピング法、半硬
化状の樹脂粉末をタブレット状に予備成形しこれを素子
表面に載せた後加熱炉内で溶融硬化させるメルトキャス
ト法等がある。Casting method (Ca,
This casting method is described, for example, in "Electronic Materials J, March 1973 issue, March 1, 1973, published by Kogyo Research Association, pages 48 to 54. In this document, It is stated that there are casting methods that use a case and casting methods that do not use a case.One of the sealing methods that use a case is to pour resin into the case and seal the desired part inside the case. Casting methods that do not use a case include the dropping method, in which a certain amount of resin is dropped onto the element surface to form a hardened state, the dipping method, in which the entire element is immersed in a resin liquid and then cured after being taken out, and the semi-cured method. There is a melt casting method in which resin powder is preformed into a tablet shape, placed on the surface of the element, and then melted and hardened in a heating furnace.
また、特開昭５２−１０３６７７号公報には、基板にＩ
Ｃ（集積回路）を構成する半導体素子（チップ）や他の
電子部品を搭載し、かつこれらチップや電子部品を保護
レジンで被った構造が記載されている。In addition, Japanese Patent Application Laid-Open No. 52-103677 discloses that an I
A structure is described in which semiconductor elements (chips) and other electronic components constituting a C (integrated circuit) are mounted, and these chips and electronic components are covered with a protective resin.
（発明が解決しようとする！！題）
パワートランジスタ、パワーＩＣ（集積回路）等のパワ
ー半導体素子（パワーチップ）を組み込んだ混成集積回
路装置にあっては、熱伝導率の良好な銅等の金属板（ヘ
ッダ）と、このヘッダの主面に重ね合わせたセラ逅ツク
板からなる配線基板とによって基板が構成され、かつ発
熱量の多いパワーチップは直接または熱伝導性の良好な
放熱板を介してヘッダに固定される場合が多い、そして
、このパワーチップは保護レジン（アンダーコートレジ
ン）で被われている。この場合前記保護レジンは、配線
基板と略同−の熱膨張係数を有するもの、たとえばフェ
ノールレジンが使用されている。(Problem to be solved by the invention!!) For hybrid integrated circuit devices incorporating power semiconductor elements (power chips) such as power transistors and power ICs (integrated circuits), materials such as copper or the like with good thermal conductivity are used. The board is composed of a metal plate (header) and a wiring board made of a ceramic board overlaid on the main surface of the header. Power chips that generate a lot of heat can be installed directly or with a heat sink with good thermal conductivity. This power chip is often fixed to the header via a protective resin (undercoat resin). In this case, the protective resin used has approximately the same coefficient of thermal expansion as the wiring board, such as phenol resin.
しかし、このような構造の混成集積回路装置を、マイナ
ス５５”Ｃからプラス１５０°Ｃに亘る苛酷な温度サイ
クル試験に掛けてみると、前記パワーチップに接続され
るワイヤが破断したり、チップにクラックが発生したり
することがあることが判明した。However, when a hybrid integrated circuit device with such a structure is subjected to a severe temperature cycle test ranging from -55"C to +150°C, the wires connected to the power chip break or the chip is damaged. It was found that cracks may occur.
これは、保護レジンでパワーチップを被う構造によるも
のであることが分かった。すなわち、パワーチップを被
う保護レジンは、ヘッダや配線基板に亘って延在してい
る０ｗ４からなるヘッダの熱膨張係数は、１６〜１８Ｘ
１０−’／”Ｃとなるとともに、セラミックからなる配
線基板およびフェノールレジンの熱膨張係数は６／７
Ｘ １０−’／”Ｃと一桁も違う、この結果、温度サイ
クル試験で保護レジンには大きな熱応力が作用し、保護
レジンで被われるワイヤやチップに大きな力が働き、ワ
イヤ破断やチップクランクが発生してしまう。It turns out that this is due to the structure in which the power chip is covered with a protective resin. In other words, the protective resin covering the power chip has a thermal expansion coefficient of 16 to 18X for the header made of 0W4 that extends over the header and wiring board.
10-'/''C, and the thermal expansion coefficient of the ceramic wiring board and phenol resin is 6/7.
As a result, a large thermal stress acts on the protective resin during a temperature cycle test, and a large force acts on the wires and chips covered with the protective resin, causing wire breakage and chip cranking. will occur.
そこで、本発明者は、パワーチップを保護レジンで被う
ことなく封止ケースのみで封止を行い、他の電子部品を
保護レジンで被う構造にすることによって、電子部品を
始めとしてパワーチップの耐湿性が図れることに気が付
き、本発明を威した。Therefore, the present inventor has developed a structure in which the power chip is sealed only with a sealing case without covering it with a protective resin, and other electronic components are covered with the protective resin. It was noticed that the moisture resistance of the material could be improved, and the present invention was applied.
本発明の目的は、混成集積回路装置において、搭載電子
部品をレジンで保護するとともに、発熱量の大きい半導
体素子およびこれに接続されるワイヤの熱応力に起因す
る不良発生を抑止することにある。An object of the present invention is to protect mounted electronic components with a resin in a hybrid integrated circuit device, and to suppress the occurrence of defects due to thermal stress in semiconductor elements that generate a large amount of heat and wires connected thereto.
本発明の他の目的は、温度サイクルに強い信頼性の高い
混成集積回路装置を提供することにある。Another object of the present invention is to provide a highly reliable hybrid integrated circuit device that is resistant to temperature cycles.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明の混成集積回路装置は、基板が放熱性
の良好なヘッダと、このヘッダに部分的に重ね合わされ
たセラミック板からなる配線基板とによって構成され、
抵抗、コンデンサ等は直接前記配線基板に固定され、パ
ワーチップは放熱板を介してヘッダに搭載されている。That is, in the hybrid integrated circuit device of the present invention, the substrate is constituted by a header with good heat dissipation, and a wiring board made of a ceramic plate partially superimposed on the header,
Resistors, capacitors, etc. are directly fixed to the wiring board, and the power chip is mounted on the header via a heat sink.
また、前記基板の主面は封止ケースが取り付けられ、基
板に固定された電子部品を全て被うようになっている。Further, a sealing case is attached to the main surface of the board, so as to cover all the electronic components fixed to the board.
また、前記封止ケースは、封止ケースに取り付けられる
蓋によって塞がれるレジン充填部と、前記蓋で塞がれる
前に既に上部が閉じられた中空部とからなり、前記中空
部はパワーチップを被い、レジン充填部は他の電子部品
を被う構造となっている。また、前記レジン充填部には
前記蓋を取り付ける前に保護レジン（封止レジン）が充
填されて電子部品を保護するようになっている。したが
って、前記パワーチップは保護レジン（アンダーコート
レジン等）に被われることなく封止ケースのみによって
封止されるようになっている。Further, the sealing case includes a resin-filled part that is closed by a lid attached to the sealing case, and a hollow part whose upper part is already closed before being closed by the lid, and the hollow part is a power chip. The resin-filled part is structured to cover other electronic components. Further, the resin filling portion is filled with a protective resin (sealing resin) to protect the electronic components before the lid is attached. Therefore, the power chip is sealed only by the sealing case without being covered with a protective resin (undercoat resin, etc.).
上記した手段によれば、本発明の混成集積回路装置にあ
っては、発熱量の多いパワーチップは封止ケースの中空
部で封止されるため、パワーチップは単に放熱板上に載
る構造であるとともに、ワイヤはその両端をそれぞれ別
々にパワーチップの電極または配線基板の配線層に接続
する構造となっていて、従来のように保護レジン（アン
ダーコートレジン等）で被われるようなことはないので
、熱変動に伴うヘッダと配線基板との相互の位置変化が
生じても、熱応力がパワーチップやワイヤに作用するこ
ともなく、ワイヤ破断やチップクラックが発生しなくな
る。According to the above means, in the hybrid integrated circuit device of the present invention, the power chip that generates a large amount of heat is sealed in the hollow part of the sealing case, so that the power chip is simply placed on the heat sink. In addition, the wires have a structure in which both ends are connected separately to the power chip's electrodes or the wiring layer of the wiring board, and are not covered with protective resin (undercoat resin, etc.) as in the past. Therefore, even if the relative positions of the header and wiring board change due to thermal fluctuations, thermal stress will not act on the power chip or wires, and wire breakage and chip cracks will not occur.
以下図面を参照して本発明の一実施例について説明する
。An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による混成集積回路装置の要
部を示す断面図、第２図は同じく平面図、第３図は同じ
く封止ケースの蓋を取り除いた状態の混成集積回路装置
の平面図である。FIG. 1 is a sectional view showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view of the same, and FIG. 3 is a hybrid integrated circuit device with the lid of the sealed case removed. FIG.
この実施例の混成集積回路装置は、第１図および第２図
に示されるような構造となっている。すなわち、この混
成集積回路装置にあっては、各種電子部品を搭載する基
板ｌは、ヘッダ２と、このヘッダ１の主面に重ね合わさ
れる配線基板３とで形成されている。前記へラダ２は熱
伝導性の良好な金属板、たとえば、ニッケルメッキを施
した淳さ２．３ｍｍの銅板で構成されている。また、前
記配線基板３は厚さ０．６ｍｍ程度のセラミック配線基
板からなり、図示しない半田を介してヘッダ２に固定さ
れている。前記配線基板３は、その幅員がヘッダ２の幅
員と略同じであるが、長さはヘッダ２よりも短く形成さ
れ、配線基板３の両端にヘッダ２の両端がそれぞれ同程
度突出するようになっている。そして、これら突出部に
は、混成集積回路装置を実装する際使用される取付溝４
が設けられている。The hybrid integrated circuit device of this embodiment has a structure as shown in FIGS. 1 and 2. That is, in this hybrid integrated circuit device, a board 1 on which various electronic components are mounted is formed of a header 2 and a wiring board 3 superimposed on the main surface of the header 1. The spatula 2 is made of a metal plate with good thermal conductivity, for example, a nickel-plated copper plate with a thickness of 2.3 mm. Further, the wiring board 3 is made of a ceramic wiring board with a thickness of about 0.6 mm, and is fixed to the header 2 via solder (not shown). The width of the wiring board 3 is approximately the same as the width of the header 2, but the length is formed shorter than the header 2, so that both ends of the header 2 protrude from both ends of the wiring board 3 to the same extent. ing. These protrusions have mounting grooves 4 that are used when mounting a hybrid integrated circuit device.
is provided.
一方、前記配線基板３は、その主面に所望パターンから
なる配線層５が設けられている。また、配＆！基［３に
はスルーホール６やくり抜き部７が設けられている。前
記スルーホール６には図示しない導体が埋め込まれてい
て、配線層５の一部がこの導体を介してヘッダ２に電気
的に接続されている。また、前記くり抜き部７に露出す
るヘッダ２の主面には、電子部品の一つであるパワー半
導体素子（パワーチップ）８が銅の放熱板９を介して固
定されている。前記放熱板９は図示しない半田でヘッダ
２に固定され、パワーチップ８は放熱板９に固定されて
いる。また、前記パワーチップ８の電極と、この電極に
対応する配線層５とは、導電性のワイヤ１０で電気的に
接続されている。On the other hand, the wiring board 3 is provided with a wiring layer 5 having a desired pattern on its main surface. Also, Kai &! The base 3 is provided with a through hole 6 and a cutout 7. A conductor (not shown) is embedded in the through hole 6, and a portion of the wiring layer 5 is electrically connected to the header 2 via this conductor. Furthermore, a power semiconductor element (power chip) 8, which is one of the electronic components, is fixed to the main surface of the header 2 exposed in the hollowed out part 7 via a copper heat sink 9. The heat sink 9 is fixed to the header 2 with solder (not shown), and the power chip 8 is fixed to the heat sink 9. Further, the electrode of the power chip 8 and the wiring layer 5 corresponding to this electrode are electrically connected by a conductive wire 10.
また、前記配線基板３の主面には、抵抗、コンデンサ等
からなる電子部品１１が搭載されている。Further, on the main surface of the wiring board 3, electronic components 11 made of resistors, capacitors, etc. are mounted.
そして、これら電子部品１１．パワーチップ８゜配線層
５等によって所望の回路が構成されている。And these electronic components 11. A desired circuit is constituted by the power chip 8° wiring layer 5 and the like.
他方、前記配線基板３の主面全域に及ぶ矩形領域は、プ
ラスチック製の封止ケース１５によって被われている。On the other hand, a rectangular area covering the entire main surface of the wiring board 3 is covered with a plastic sealing case 15.
この封止ケース１５は、枠状の本体１６と、この本体１
６の上面に取り付けられる蓋１７とからなっている。前
記本体１６は前記配線基板３の周縁に沿うように設けら
れた外壁部１８と、前記一対の外壁部１日を連結する平
行な一対の内壁部１９と、この一対の内壁部１９を連結
する平行に延在する一対の隔壁２０とを有する枠構造と
なっている。また、前記一対の内壁部１９および隔壁２
０で囲まれる領域の上部は天井板２１で塞がれ、中空部
２２が形成されている。そして、この本体１６は、シリ
コーン樹脂系の接着樹脂によって配線基板３の主面に密
着状態で固定されている。This sealed case 15 includes a frame-shaped main body 16 and a main body 1
6 and a lid 17 attached to the top surface of the device. The main body 16 has an outer wall section 18 provided along the periphery of the wiring board 3, a pair of parallel inner wall sections 19 that connect the pair of outer wall sections, and a pair of inner wall sections 19 that connect the pair of inner wall sections 19. It has a frame structure having a pair of partition walls 20 extending in parallel. Further, the pair of inner wall portions 19 and the partition wall 2
The upper part of the area surrounded by 0 is closed with a ceiling plate 21, and a hollow part 22 is formed. The main body 16 is fixed to the main surface of the wiring board 3 in close contact with a silicone resin-based adhesive resin.
前記本体１６の中空部２２は、第１図に示されるように
、前記パワーチップ８およびワイヤ１０等を非接触状態
で被うようになっている。また、残りの枠領域部分には
前記電子部品１１が位置している。そして、これらの領
域には、シリコンレジンからなる保護レジン（封止レジ
ン）２３が充填されている。したがって、前記中空部２
２に臨む領域以外は保護レジン２３で被われて保護され
ている。As shown in FIG. 1, the hollow portion 22 of the main body 16 covers the power chip 8, the wire 10, etc. in a non-contact manner. Further, the electronic component 11 is located in the remaining frame area. These areas are filled with a protective resin (sealing resin) 23 made of silicone resin. Therefore, the hollow part 2
The area other than the area facing 2 is covered and protected with a protective resin 23.
前記本体１６の内壁部１９の上面には、その中央に沿っ
て嵌合溝２４が設けられているとともに、前記部１７の
下面には、前記嵌合溝２４に対応して突条２５が設けら
れている。したがって、前記蓋１７は、蓋１７の突条２
５を本体１６の嵌合溝２４に嵌合させることによって本
体１６に取り付けられている。この場合、接着剤を使用
して、蓋１７を本体１６に固定してもよい。A fitting groove 24 is provided on the upper surface of the inner wall portion 19 of the main body 16 along the center thereof, and a protrusion 25 is provided on the lower surface of the portion 17 in correspondence with the fitting groove 24. It is being Therefore, the lid 17 has a ridge 2 on the lid 17.
5 is attached to the main body 16 by fitting into the fitting groove 24 of the main body 16. In this case, the lid 17 may be fixed to the main body 16 using an adhesive.
また、第２図に示されるように、前記封止ケース１５の
一側から４本のリード端子２６が突出している。このリ
ード端子２６は、その内端が前記配線基板３の所定の配
線層５に電気的に接続するように固定されている。Further, as shown in FIG. 2, four lead terminals 26 protrude from one side of the sealing case 15. This lead terminal 26 is fixed such that its inner end is electrically connected to a predetermined wiring layer 5 of the wiring board 3.
このような実施例によれば、つぎのような効果が得られ
る。According to such an embodiment, the following effects can be obtained.
（１）本発明の混成集積回路装置は、電子部品は保護レ
ジンによって保護され、パワーチップは封止ケースの中
空部で被われていることから、耐湿性が高いという効果
が得られる。(1) In the hybrid integrated circuit device of the present invention, the electronic components are protected by the protective resin, and the power chip is covered by the hollow part of the sealing case, so that the effect of high moisture resistance can be obtained.
（２）本発明の混成集積回路装置にあっては、パワーチ
ップは封止ケースの中空部で被われ、従来のような保護
レジン（アンダーコートレジン等）による密着状態によ
る封止構造と異なっていて、ワイヤやチップには応力が
加わらない構造となっているため、ヘッダと配線基板の
熱膨張係数が大幅に異なっていても、これらのものによ
る熱膨張係数の違いに起因する熱応力が直接ワイヤやチ
ップに加わらず、ワイヤ破断やチップクランクの発生が
抑止できるという効果が得られる。(2) In the hybrid integrated circuit device of the present invention, the power chip is covered with the hollow part of the sealing case, which is different from the conventional sealing structure in which the seal is in close contact with a protective resin (undercoat resin, etc.). The structure is such that no stress is applied to the wires or chips, so even if the thermal expansion coefficients of the header and wiring board are significantly different, the thermal stress caused by the difference in the thermal expansion coefficients of these items is directly absorbed. This has the effect of preventing wire breakage and chip crank from occurring without damaging the wire or chip.
（３）上記（２）により、本発明の混成集積回路装置は
、温度サイクル試験に対して優れたものとなるという効
果が得られる。(3) Due to the above (2), the hybrid integrated circuit device of the present invention has the effect of being excellent in temperature cycle tests.
（４）本発明の混成集積回路装置は、その製造において
パワーチップをアンダーコートレジンで被う必要がなく
なるため、工数が低減されるという効果が得られる。(4) In the hybrid integrated circuit device of the present invention, there is no need to cover the power chip with an undercoat resin during its manufacture, so that the number of man-hours can be reduced.
（５）上記（４）により、本発明によれば、混成集積回
路装置の製造において、パワーチップをアンダーコート
レジンで被わないことから、材料の低減が達成できると
いう効果が得られる。(5) According to the above (4), according to the present invention, in manufacturing a hybrid integrated circuit device, the power chip is not covered with an undercoat resin, so that the amount of material can be reduced.
（６）上記（４）および（５）により、本発明の混成集
積回路装置は、その製造において、材料の低減および工
程の軽減からコストの低減が達成できるという効果が得
られる。(6) According to (4) and (5) above, the hybrid integrated circuit device of the present invention has the effect that cost can be reduced by reducing the number of materials and steps in manufacturing the device.
（７）上記（１）〜（６）により、本発明によれば、温
度サイクル試験に強い信頼性の高い混成集積回路装置を
安価に提供することができるという相乗効果が得られる
。(7) According to the above (1) to (6), according to the present invention, a synergistic effect can be obtained in that a highly reliable hybrid integrated circuit device that is resistant to temperature cycle tests can be provided at a low cost.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない、たとえば、第４１！Ｉに
示されるように、前記封止ケース１５の中空部２２の天
井板２１上に、導電性のメツキ層３０を設ければミシー
ルド効果を有するようになる。また、このシールド効果
を得るために、前記天井板２１部分にシールド材質を埋
め込むようにしても同様な効果が得られる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. No, for example, the 41st! As shown in FIG. 1, if a conductive plating layer 30 is provided on the ceiling plate 21 of the hollow part 22 of the sealing case 15, a mishield effect can be obtained. Further, in order to obtain this shielding effect, a similar effect can be obtained even if a shielding material is embedded in the ceiling plate 21 portion.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である混成集積回路装置の
製造技術に適用した場合について説明したが、それに限
定されるものではない。In the above description, the invention made by the present inventor is mainly applied to the technology for manufacturing hybrid integrated circuit devices, which is the background field of application, but the invention is not limited thereto.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明の混成集積回路装置にあっては、発熱量の多いパ
ワーチップは封止ケースの中空部で封止されるため、パ
ワーチップは単に放熱板上に載る構造であるとともに、
ワイヤはその両端をそれぞれ別々にパワーチップの電極
または配線基板の配線層に接続する構造となっていて、
従来のように保護レジンで密着状態で被われるようなこ
とはないので、熱変動に伴うヘッダと配線基板との相互
の位置変化が生じても、両者に起因する応力がパワーチ
ップやワイヤに作用することもなく、ワイヤ破断やチッ
プクランクが発生しなくなり、温度サイクルに対して強
い製品となる。In the hybrid integrated circuit device of the present invention, since the power chip that generates a large amount of heat is sealed in the hollow part of the sealing case, the power chip is simply placed on the heat sink, and
The wire has a structure in which both ends are connected separately to the electrodes of the power chip or the wiring layer of the wiring board.
Since the header and wiring board are not tightly covered with protective resin as in the past, even if the relative position of the header and wiring board changes due to thermal fluctuations, the stress caused by both will not be applied to the power chip or wires. This eliminates wire breakage and chip crank, making the product resistant to temperature cycles.
第１図は本発明の一実施例による混成集積回路装置の要
部を示す断面図、
第２図は同じく平面図、
第３図は同じく封止ケースの蓋を取り除いた状態の混成
集積回路装置の平面図、
第４図は本発明の他の実施例による混成集積回路装置の
要部を示す断面図であるや
１・・・基板、２・・・ヘッダ、３・・・配線基板、４
・・・取付溝、５・・・配線層、６・・・スルーホール
、７・・・＜す抜き部、８・・・パワー半導体素子（パ
ワーチップ）、９・・・放熱板、１０・・・ワイヤ、１
１・・・電子部品、１５・・・封止ケース、１６・・・
本体、１７・・ＩＬ１８・・・外壁部、１９・・・内壁
部、２０・・・隔壁、２１・・・天井板、２２・・・中
空部、２３・・・保護レジン、２４・・・嵌合溝、２５
・・・突条、２６・・・リード端子、３０・・・メツキ
層。FIG. 1 is a sectional view showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view of the same, and FIG. 3 is a hybrid integrated circuit device with the lid of the sealed case removed. FIG. 4 is a sectional view showing the main parts of a hybrid integrated circuit device according to another embodiment of the present invention.
...Mounting groove, 5...Wiring layer, 6...Through hole, 7...< hollow part, 8... Power semiconductor element (power chip), 9... Heat sink, 10...・Wire, 1
1... Electronic component, 15... Sealing case, 16...
Main body, 17...IL18...Outer wall part, 19...Inner wall part, 20...Partition wall, 21...Ceiling plate, 22...Hollow part, 23...Protection resin, 24... Fitting groove, 25
... protrusion, 26 ... lead terminal, 30 ... plating layer.
Claims (1)
の一部が封止された混成集積回路装置であって、前記封
止ケースはレジンが充填される領域以外にレジンが充填
されない中空部が設けられていることを特徴とする混成
集積回路装置。 ２、前記中空部は前記基板に固定された高出力電子部品
を被っていることを特徴とする特許請求の範囲第１項記
載の混成集積回路装置。 ３、前記基板は熱伝導性の良好なヘッダと、このヘッダ
の主面に重ね合わされた配線基板とからなるとともに、
前記高出力電子部品はヘッダに固定されていることを特
徴とする特許請求の範囲第２項記載の混成集積回路装置
。[Scope of Claims] 1. A hybrid integrated circuit device in which a part of a substrate is sealed with a sealing case having a structure in which the inside is filled with resin, wherein the sealing case has an area other than the area filled with resin. 1. A hybrid integrated circuit device, characterized in that a hollow portion is provided which is not filled with resin. 2. The hybrid integrated circuit device according to claim 1, wherein the hollow portion covers a high-power electronic component fixed to the substrate. 3. The board consists of a header with good thermal conductivity and a wiring board overlaid on the main surface of the header,
3. The hybrid integrated circuit device according to claim 2, wherein said high-power electronic component is fixed to a header.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19939489A JPH0364049A (en) | 1989-08-02 | 1989-08-02 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19939489A JPH0364049A (en) | 1989-08-02 | 1989-08-02 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0364049A true JPH0364049A (en) | 1991-03-19 |
Family
ID=16407053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19939489A Pending JPH0364049A (en) | 1989-08-02 | 1989-08-02 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0364049A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594395A2 (en) * | 1992-10-20 | 1994-04-27 | Fujitsu General Limited | Semiconductor power module |
| KR20040032544A (en) * | 2002-10-10 | 2004-04-17 | 한영수 | Sealing structure of solid state relay |
-
1989
- 1989-08-02 JP JP19939489A patent/JPH0364049A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594395A2 (en) * | 1992-10-20 | 1994-04-27 | Fujitsu General Limited | Semiconductor power module |
| EP0594395A3 (en) * | 1992-10-20 | 1995-01-11 | Fujitsu General Ltd | Semiconductor power module. |
| CN1036043C (en) * | 1992-10-20 | 1997-10-01 | 富士通株式会社 | Power module |
| KR20040032544A (en) * | 2002-10-10 | 2004-04-17 | 한영수 | Sealing structure of solid state relay |
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