JPH03226850A - External auxiliary storage controller - Google Patents

Abstract

PURPOSE:To prevent the processing speed of a data transfer from becoming low by executing simultaneously the data transfer to a cache memory and a host interface from a buffer memory. CONSTITUTION:When a signal TM is active, when both transfer signals DRQ1 and DRG2 become active, an input signal to a DRG detecting circuit 42 of a first channel and a second channel becomes active, confirming signals DAK1, DAK2 and an address output become active, and a read-out signal IORD2, and write signals MWR and IOWR1 become active. As a result, data are transferred simultaneously to a cache memory 1 and a host interface control circuit 2 from a buffer memory 3 through a data bus D18. In such a way, it can be prevented that a data transfer speed extending from the buffer memory 3 to the host interface control circuit 2 becomes low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for controlling an external auxiliary storage device of an information processing device.

[Conventional technology]

Regarding conventional external auxiliary storage control devices (hereinafter referred to as control devices), magnetic storage devices (hereinafter referred to as storage devices)
will be explained using FIGS. 4 to 6 as an example.

FIG. 4 is a block diagram showing the configuration of a conventional control device.

The cache memory 1 functions as a cache for an external storage device (not shown), and stores part of the data stored in this storage device.

Now, when there is a data request from the host system (not shown), if the requested data is in the cache memory 1, the control device transfers the data to the cache memory 1.
The data is immediately transferred to the host system via the host interface control circuit 2.

On the other hand, if the requested data is not in the cache memory 1, the control device reads the child data from the external storage device to the buffer memory 3, and stores it in the cache memory 1 in preparation for another data request from the host system. After making it safe, it is transferred to the host system via the host interface control circuit 2.

In the above operation, the host interface control circuit 2
．． DMA (DMA) is used to transfer data at high speed by directly controlling the data bus and address bus without the intervention of the central processing unit, such as data transfer between the cache memory 1 and buffer memory 3. Di
rectMemory Access) transfer,
Based on the instructions of the microprocessor 5, the DMA controller 1
- control roller 4a;

51''!I is a block diagram showing the configuration of main parts of the I) MA controller 4a in the conventional control device shown in FIG. 4.

These DMA controllers 1 to roller 4a are 2-channel DM
A transfer is being performed from 1 to 1.

Now, the first channel side of the DMA controller 4a is controlling the interface to the host 1 i? Supports 82 and 2nd
Assuming that the channel side supports buffer memory 3, let's take the second channel as an example.
The control of DMA transfer by the roller 4a will be described (the first channel also operates in the same way).

When the microprocessor 5 specifies the transfer mode of the second channel of the DMA controller 4a as "rJQ-memory transfer mode", when the signal DRQ2 requesting DMA transfer (hereinafter referred to as transfer signal) becomes active. , a signal DAK2 indicating that this transfer signal has been accepted (hereinafter referred to as a confirmation signal) and an address output indicating the transfer destination on the cache memory 1 become active.

Furthermore, the read signal l0RD to the buffer memory 3 and the write signal MWR to the cache memory 1 become active, and the data from the buffer memory 3 to the cache memory 1-
Data is transferred to.

When the data transfer of one word is completed by the above operation, the address counter 41 increments the address by one in preparation for the next data transfer.

The above operation is repeated the number of times set by the microprocessor 5, and the DMA transfer from the buffer memory 3 to the cache memory 1 is completed.

Based on the instructions from the microprocessor 5, the DMA controller 4a repeats the above-described operation for the first channel, so that the buffer memory 3. DMA transfer between the cache memory 1 and the host interface control circuit 2 is realized.

In this case, in a conventional DMA controller, the input signal (
Transfer signals DRQ and DRQ2> are input independently for each channel, but the output signal read signal ■
○R, D and write signal I OWR are not independent for each channel. Read signal I OR, D and write signal I OWR from each channel
are output to the signal line common to both channels.

Note that the confirmation signal DAK,
Or it can be determined by DAK2.

[Problem to be solved by the invention]

As described above, in the conventional control device, each output from the DMA controller 4a receives the read signal ■○RD.
The write signal OWR and the write signal OWR each use a signal line common to both channels.

For this reason, the conventional control device cannot transfer data from the buffer memory 3 to the cache memory 1 and the host interface control circuit 2 at the same time.

For example, when trying to realize simultaneous DMA transfer from buffer memory 3 to cache memory 1 and host interface control circuit 2 with a conventional control device, read signal l0RD to buffer memory 3 and write signal I0R to host interface control circuit 2 becomes active at the same time, and the confirmation signals DAK and D
Since AK2 is active for both channels, l0RD and I OWR are also applied to buffer memory 3 and host interface control circuit 2.
will be inserted, and operation will no longer be guaranteed.

Also, DM from buffer memory 3 to cache memory 1
If the A transfer and the DMA transfer from the cache memory 1 to the host interface control circuit 2 are performed in parallel and at the same time, the following inconvenience will occur.

Transfer signal DRQ2 for the second channel of the DMA controller 4a and transfer signal DR for the first channel
Q1 becomes active on its own, data is transferred from the buffer memory 3 to the cache memory 1 on the second channel side, but at the same time, data is transferred from the cache memory 1 to the host interface control circuit 2 on the first channel side.
Hepta is transferred.

In other words, writing and reading operations are performed simultaneously on the same cache memory 1.

At this time, there is a difference in writing speed and reading speed, and the data transfer speed from cache memory 1 to host interface control circuit 2 is faster than the data transfer speed from buffer memory 3 to cache memory 1. In this case, the contents of the DMA transfer will not be consistent between the two, so the above operation cannot be used in practice.

In the conventional control device, due to the above-mentioned disadvantages, DMA transfer cannot be performed from the buffer memory 3 to the cache memory 1 and the host interface control circuit 2 at the same time.

Therefore, in the conventional control device, when data is transferred from the buffer memory 3 to the host interface control port B2 via the cache memory 1, the data is first transferred from the buffer memory 3 to the cache memory 1 on the second channel side. However, after this operation is completed, a two-step operation is required to transfer data from the cache and memory 1 to the host interface control circuit 2 on the first channel side.

FIG. 6 shows the timing relationship of each signal regarding the above-mentioned DMA transfer operation.

4, 5 and 6, when the control device receives a data request signal from the host system, the microprocessor 5 analyzes this request and sends the data to the format controller 6 via the data bus D27. Issues a command to read data from an external storage device.

When data enters the buffer memory 3 through this operation, the transfer signal DRQ2 becomes active, and the confirmation signal DAK2 becomes active.
, address output, read signal ORD and write signal MWR become active, and data is transferred to data bus D1.
8, from buffer memory 3 to cache memory 1
will be forwarded to.

When the transfer of the desired data is completed, the microprocessor 5 then issues a command to transfer the data from the cache memory 1 to the host interface control circuit 2 to the DMA controller 4a via the data bus D27.

As a result, the address output, confirmation signal DAKl, write signal l0WR, and read signal MRD become active, and data is transferred from the cache memory 1 to the host interface control circuit 2 via the data buses D and 8, and a series of DMA transfers is performed. finish.

As explained above, in conventional control devices, when there is a data request from the host system and the data is not in the cache memory, the requested data is transferred from the external storage device to the buffer. A two-step operation is performed in which the data is read out to the memory, and in preparation for another data request, the data is first transferred from the buffer memory to the cache memory, and then transferred from the cache memory to the host interface control circuit.

Therefore, there is a drawback that the data transfer processing speed becomes slow.

[Means to solve the problem]

The external auxiliary storage control device according to the present invention has a first memory that operates as a buffer, a second memory that operates as a cache, and a controller that controls an interface with an external post system, and the controller that controls the interface with an external post system. The present invention is characterized in that data read from an external auxiliary storage device in response to a data request from a host system is simultaneously transferred from the first memory to the second memory and the controller.

Further, the external auxiliary storage control device according to claim 2 recognizes this when both the data request signal from the host system and the data transfer request borrow from the first memory become active, and - a data read signal to the second memory, a data write signal to the second memory, and a data write signal to the controller are simultaneously activated.

〔Example〕

The present invention will be explained using FIGS. 1 to 3.

FIG. 1 is a block diagram showing the configuration of a control device according to an embodiment of the present invention.

In the control device shown in FIG. 1, the write signal l0WR, which is the output from the roller 4a, and the read signal
D and the like are both input to the host interface control circuit 2 and the buffer memory 3 via a common signal line, whereas the write signal to the host interface control circuit 2 WR1 and the read signal IORD 1 and a write signal to the buffer memory 3 WR2 and a read signal I0RD2, which are independent.

FIG. 2 is a diagram showing the configuration of the main parts of the DMA controller 4b in the control device according to the embodiment of the present invention, which is not shown in FIG. 1.

The DMA controller 4b shown in FIG. 2 is different from the conventional DMA controller 1 to roller 4a shown in FIG.
They have the differences listed below.

(1) Write signal I OWR and read signal ■OR
D are independent for the first channel and the second channel, l0WR,, l0WR2, l0RDI and l0WR, respectively.
It has become 0RD2.

(21D MA controller 1 to roller 4b control mode,
A signal TM is provided for specifying "DMA transfer mode from buffer memory to cache memory and host interface control circuit."

(3) The input to the DRQ detection circuit of the second channel is a signal expressed by the following logical formula.

3 DRQ2 ・(TM+TM DRQ+)(4
) The confirmation signal DAKI of the first channel contains the confirmation signals D , A K 2 of the second channel.

FIG. 6 shows the timing relationship of each signal in the data transfer operation of the control circuit according to the embodiment of the present invention configured as described above.

In FIGS. 1, 2, and 3, when the control mode of this control device is set to "DMA transfer mode from buffer memory to cache memory and host l-interface control circuit," that is, when the signal TM is When the transfer signals D RQl and D R,Q 2 are both active, the input signals to the DRQ detection circuit 42 of the first channel and the second channel become active, and the confirmation signals DAK and DAK2 and the address output are activated. A1 becomes active, read signal IORD2, write signals MWR and I0WRI become active, and data is transferred at once from the buffer memory to the cache memory and host interface control circuit via data buses D and 8. be done.

The above-described operation is repeated to transfer data from the buffer memory to the cache memory and host interface control circuit.
MA transfer is performed.

In the above description, a magnetic disk storage device was used as an example of an external auxiliary storage device, but as is clear from the above description, the present invention is not limited to this, and the present invention can be applied to an external storage device using a cartridge magnetic tape or an optical disk. It can also be applied to auxiliary storage devices.

[Effects of the Invention] As described above, according to the present invention, data can be transferred from the buffer memory to the cache memory and the host interface control circuit simultaneously.

Therefore, when the data requested by the host system is not in the cache memory, data to be read from an external storage device is first transferred from the buffer memory to the cache memory, and then from the cache memory to the host system. In contrast to the one-step process of transferring the data to the interface control circuit, the present invention requires only one operation.

Therefore, according to the present invention, it is possible to prevent the data transfer speed from the buffer memory to the host interface control circuit from becoming slow.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an external auxiliary storage control device according to an embodiment of the present invention, and FIG. 2 is a DM shown in FIG.
Block diagram showing the internal configuration of the A controller 4, 3rd
4 is a timing diagram showing the timing relationship of each signal in the data transfer operation of the external auxiliary storage control device according to the embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of the external auxiliary storage control device according to the conventional technology, Figure 5 shows the fourth
FIG. 6 is a block diagram showing the internal configuration of the DMA controller 4 shown in the figure. FIG. 6 is a timing diagram showing the timing of each signal in the data transfer operation of the external auxiliary storage control device according to the conventional technology. DESCRIPTION OF SYMBOLS 1... Cache memory, 2... Host interface control circuit, 3... Buffer memory, 4a, '4b.
・DMA controller, 5... microprocessor,
6...Format controller 1 to roller, 7...Data bus D2.8...Data bus D1.41...Address counter, 42...DRQ detection circuit.

Claims (1)

[Scope of Claims] 1. A first memory that operates as a buffer, a second memory that operates as a cache, and a controller that controls an interface with an external host system, and which stores data from the host system. An external auxiliary storage control device characterized in that data read from an external auxiliary storage device is simultaneously transferred from the first memory to the second memory and the controller upon request. 2. The external auxiliary storage control device according to claim 1, wherein when a data request signal from the host system and a data transfer request signal from the first memory are both activated, this is recognized; An external auxiliary storage control device characterized in that a data read signal to the second memory, a data write signal to the second memory, and a data write signal to the controller are simultaneously activated.