JPH0210446A - Buffer storage device - Google Patents

Abstract

PURPOSE:To shorten the waiting time of an MPU by providing a data buffer (block buffer), where one-block components of data can be stored at a time, between the internal data bus and the data memory part of a cache memory. CONSTITUTION:A block buffer 18 where one-block components of data can be stored at a time is provided between an internal data bus 17b and a data memory 12 of a cache memory 1, and data is transferred between the block buffer 18 and the data memory 12 with a unit larger than that for data transfer between the cache memory 1 and a main memory. Thus, one-block components of data to be transferred to the main memory or data transferred from the main memory are collectively stored in the bloc buffer 18, and the MPU can access the data memory 12 even during the block transfer between the cache memory 1 and the main memory to shorten the waiting time of the MPU.

Description

Detailed Description of the Invention 3. Field of Industrial Application [Field of Industrial Application] The present invention relates to a storage management technology and a technology that is particularly effective when applied to a control method for a buffer storage device, such as a buffer storage method. This invention relates to a technology that is effective for use in cache memory in information processing systems that employ .

[Prior Art] Conventionally, in a microcomputer that employs a buffer storage method, frequently used information in a main storage device such as a dynamic RAM is stored in a cache memory, and this information is stored in a cache controller. There are some devices that are controlled by a storage management device called . . . to improve throughput.

Cache memory is a microprocessor unit (
When the desired data is accessed by the address output from the MPU (hereinafter referred to as MPU) and is in the cache memory, that is, when the cache is hit, the MPU can immediately obtain the data, improving system throughput. be done. The cache controller compares the address output from the MPU with an internal address (tag), and if it determines that the desired data is not in the cache memory, outputs a signal indicating a miss. Then, the MPU accesses the main memory and obtains data from the main memory.

By the way, since the data in the cache memory is rewritten immediately when the cache is hit during data writing, a mismatch with the data in the main memory occurs at this time. Therefore, when the data in the cache memory is rewritten, the data in the main memory must also be rewritten.

In this case, the main memory rewriting method is the copy pack method, which updates the main memory when replacing a written block in the cache memory, or the copy pack method, which updates the main memory as soon as there is a write to the cache memory. There is one type of light through. Among these, in the copy pack method, updating of the main memory is performed by transferring a block of data from the cache memory to the main memory. In addition, block replacement at the time of a miss is also performed by transferring the block from the main memory to the cache memory (see Nikkei Electronics J, November 16, 1987 issue, pages 170 and 170, published by Nikkei McGraw-Hill).

[Problems to be Solved by the Invention] The size of the block, which is the unit of transfer when updating and replacing blocks in the two-layer main memory, is based on the data that can be transferred at one time (1 word or 4 bytes on a 32-bit microcontroller). unit) is set to a unit larger than 1, for example, 32 bytes.

Therefore, block transfer is completed by multiple data transfers. However, in the conventional cache memory, block transfer to and from the main memory is only performed via a one-word buffer. Therefore,
During block transfer, the data memory section is occupied by the main memory, and even if the MPU needs the data in the data memory section, it cannot read it and is forced to wait until the transfer is completed, reducing system throughput. There was a problem.

An object of the present invention is to reduce the waiting time of the MPU by allowing the MPU to access the data memory section even during block transfer between the cache memory and the main memory, thereby improving the throughput of the system.

Another object of the present invention is to improve system throughput by allowing the MPU to obtain desired data faster than reading data from the data memory section of the cache memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a data buffer (hereinafter referred to as a block buffer) that can store one block of data at a time is provided between the internal data bus of the cache memory and the data memory section.
is provided, and the data transfer between the block buffer and the data memory section is configured to be performed in a larger unit than the data transfer between the cache memory and the main memory.

Furthermore, the block buffer is constructed of dual-port registers, and determining means is provided for determining whether data requested by the MPU is present in the block buffer.

[Operation] According to the above-mentioned means, by storing one block of data that should be transferred to the main memory or that has been transferred from the main memory in a block buffer, block transfer between the cache memory and the main memory is performed. Among other things, it is possible to achieve the above-mentioned object of making the data memory section accessible by the MPU, reducing the waiting time of the MPU, and thereby improving the throughput of the system.

In addition, it is possible to know whether there is data in the block buffer before a cache fill/miss is determined, and since the cache memory has a dual-port configuration, there is no data between the cache memory and main memory. The MPU can now read data from the block buffer even during data block transfer.
The above objective of improving throughput can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a cache memory with a built-in cache controller.
The figure shows an example of the configuration of a microprocessor unit system using this cache memory.

The cache memory 1 in FIG. 1 is composed of one chip,
A directory memory 11', a data memory 12, and an LRU (Least Recently
A block direct exchange control circuit 13 of the ``Used'' type, a tag comparator 14, a write buffer 15 for temporarily holding a write address and write data, a control logic 16 for controlling these circuits, and the like are formed.

This cache memory 1 is connected between a memory bus 21 to which the main memory 3 is connected and an MPU bus 22, as shown in FIG. In this embodiment, a block buffer 18 is provided between the data memory 12 and the internal data bus 17b. The block buffer 18 is comprised of a dual-baud 1-register capable of storing data in which one block consists of, for example, 16 bytes. There is. A bus 19 is also provided for outputting data read from the data memory 12 directly onto the internal data bus 17b.

In the directory memory 11, there is a data memory 12.
The upper ten or so bits of the address on the main memory of data stored in the same column position are stored as a tag. When the column address part CLM of the address AD given to the cache memory 1 by the MPU 2 is supplied to the common decoder of the directory memory 11 and the data memory 12, the address tough and data are simultaneously read from the same column of each memory. . Of these, 16 bytes of data are read out from the data memory 12 at a time, and the read data is temporarily stored in the block buffer 18. Data transfer between the data memory 12 and the block buffer 18 is not particularly limited, but is performed in units of 16 bytes.

On the other hand, the address tough read from the directory memory 11 is supplied to the tag comparator 14.

This tag comparator 14 is also supplied with the data of the tag part TAG of the address AD given from the MPU 2, and compares it with the tag read out from the directory memory 11 to determine -R (catch hit) or mismatch (mishit). ) is output.

When the cache hits here, one word (4 bytes) of the 16 bytes of data read from the corresponding column position in the data memory 12 and held in the block buffer 18 is specified by the lower 2 bits of the address. data is selected by a selector (not shown) and supplied to the MPU via the data bus 17b. On the other hand, when the error 1- occurs, the MPU bus 22 and the memory bus 21 are connected via the internal address bus 17a and the internal data bus 17b, and the MPU 2 uses the memory bus 21 to access the main memory 3. It is designed to be accessed directly. Furthermore, if a mishit occurs during data writing, the address and data held in the write buffer 15 are output onto the memory bus 21.

In addition, in the system shown in FIG. 2, the ROM 5 is connected to the memory bus 21.
and the I10 register 6 5 and the frame buffer 31 for image data via the system bus adapter 7. A file controller 32, a DMA controller 33, etc. are connected. Further, a main storage controller 1-roll circuit 4 is provided to control data transfer between the cache memory 1 and the main memory 3.

Furthermore, in the cache memory of this embodiment, one bit is stored for each column of the directory memory 11.
A transfer bit BT is provided to indicate whether data requested by the main memory is being transferred as a block from the main memory to the cache memory. Also, in the block buffer 18, there is a bit BB indicating whether or not the data corresponding to each word is valid.
V is provided.

The states of the bits I3T and BBV are monitored by the control logic 16 and reflected in data transfer control, and the control logic 16 rewrites the bits BT and BBV in accordance with the data flow.

Specifically, as a result of comparing the tag part of the address given by the MPU, if a cache hit is found, the bit BT in the corresponding column position is checked, and if BT is II OII, the desired data is stored in the data memory 12. Therefore, the data in the data memory is output onto the data bus 17b,
Returns the catch signal to the MPU.

Also, even if the cache is hit, the transfer bit BT is “1”.
If ``'', the desired data is in the block buffer 18, so check the bit BBV in the block buffer 18 to find out whether the desired word data is valid or not.
At t 1 #, the data is output onto the data bus 17b and a cash hit signal is returned to the MPU.

When BBV is ``0'', wait until BBv becomes It 171 due to data transfer from main memory, and then change to ``1''.
'', the word data is transferred to the data bus 17b.
output to MPU and return the catch signal to MPU.
PU takes it in.

At the same time, when a block transfer factor occurs, the control logic 16 first sets the corresponding bit BT in the directory memory 11 to 11" and then starts data transfer, and depending on the transfer state, the control logic 16
Set II I 11 to bit BBV in
When the BV bit becomes 1'', block buffer 1
8 to main memory 3 or data memory 12
Transfer to. Then, when the transfer is finished, the bit BBV
and the corresponding bit BT in data memory 11 as jt
Reset to OIT.

FIG. 3 shows the flow of addresses and data according to the control procedure when a cache miss occurs during data reading. However, here, a case is shown in which one block, that is, the amount of data that is continuously transferred is 16 bytes.

When a cache miss occurs, an address is passed from the MPU to the main memory MM (FIG. 3(A)).

The data specified by this address is in a certain block Bi.
If it is the third data C, first, that data C is read from the main memory MM and stored in the block buffer BB, and the corresponding BBV bit is set to 11111.
is set, and the data read from the main memory MM is directly transferred to the main memory MM via the internal data bus 17b.
It is sent to the PU (Figure 3 (B)).

Thereafter, other data D, A, and B belonging to the same block Bi as the data C are sequentially read out from the main memory M and stored in the block buffer BB.

During this block transfer, for example, if the MPU requests data A that has already been transferred, data A is read from the block buffer BB and sent to the MPU regardless of the block transfer (see Figure 3 (C). )). Even when desired data is in the data memory 12, it can be read out regardless of block transfer.

Then, through a series of block transfers, when all the data A, B, C, and D for the block are collected in the block buffer BB, 16 bytes of data are simultaneously transferred to the data array (data memory) DA (the Figure 3 (D)).

In this way, in the above embodiment, even during block transfer, the MPU can read data in the cache memory whenever necessary.

Furthermore, in the cache memory of the above embodiment.

The user can exclude some cache areas from being replaced by the LRU method, that is, specify that certain data should always be kept in the cache memory. In this case, if the copy-pack method is used, there is no block replacement for the specified area, so the contents are sent to the main memory periodically or when the specified area is filled with data.

It is necessary to ensure data consistency.

In that case, a data block transfer request occurs asynchronously with MPU processing, but since the cache memory of the above embodiment has a block buffer, data block transfer requests in a predetermined area in the cache memory can be performed without reducing throughput. Data can be transferred in blocks to main memory.

Further, in the above embodiment, the directory memory is provided with a bit BT indicating that a block of data is being transferred from the main memory to the cache memory. A bit indicating that the directory exists may be provided in the directory memory.

As explained above, in the above embodiment, a block buffer capable of storing one block of data at a time is provided between the internal data bus of the cache memory and the data memory section, and the block buffer and the data array section are connected to each other. Since the data transfer between the cache memory and the main memory is configured to be performed in larger units than the data transfer between the cache memory and the main memory, the data that should be transferred to the main memory or has been transferred from the main memory is By storing one block in the block buffer, the MPU can access the data memory section even during block transfer between the cache memory and main memory, which reduces MPU waiting time and improves system performance. This has the effect of improving throughput.

In addition, the block buffer is configured with dual-port registers, and a determination means is provided to determine whether or not the data requested by the MPU is in the block buffer, so it is possible to determine whether the cache is hit or miss. In addition, since the cache memory is dual-ported, the MPU can read data from the block buffer even while data blocks are being transferred between the cache memory and the main memory. As a result, the MPU can obtain desired data faster than reading data from the data array section of the cache memory, which has the effect of improving system throughput.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the lines 1 to 1 buffer in the cache memory may be omitted, or various functional circuits such as a parity checker or a buffer for holding data read/written to the data memory in units of blocks may be added.

In the above explanation, the invention made by the present inventor was mainly applied to cache memory, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and includes communication buffer memory and image field memory. Other buffer storage devices are generally available.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, the MPU can access the data array section even during block transfer between the cache memory and main memory, thereby reducing the MPU's waiting time and allowing the MPU to access the desired data faster than the MPU reads data from the data array section of the cache memory. data can be obtained, thereby improving system throughput.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a cache memory; FIG. 2 is a system configuration diagram showing an example of the configuration of a microprocessor unit system using the cache memory; The figure is an explanatory diagram showing the order of addresses and data flow after a cache memory miss occurs. 1...Cache memory, 2...MPU (microprocessor unit), 3...Main memory, 11...Directory memory, 12...Data memory, 14... Tag comparator, 15... write buffer, 17a... internal address bus. 17b...Internal data bus, 18...Block buffer, 21...Memory bus, 22...M
P Agent Patent Attorney Tomio Ohinata 7-゛1 Figure

Claims (1)

[Claims] 1. A buffer storage device comprising a directory memory section in which address tags are stored and a data memory section in which data corresponding to the address tags stored in the directory memory section is stored, A data buffer capable of storing one block of data transferred simultaneously in a series of operations is provided between the data memory section and the internal data bus. A buffer storage device characterized by being configured to transfer data in units larger than data transfer between a data memory section and a main memory. 2. The buffer storage device according to claim 1, wherein the data buffer is comprised of a dual port register. 3. The directory memory section has a bit indicating whether the data corresponding to each address tag is being transferred in a block, and the data buffer has a bit indicating whether the stored data is valid or not. 3. The buffer storage device according to claim 1, wherein a buffer storage device is provided for each register.