JPH03201036A - Microcomputer - Google Patents

Abstract

PURPOSE:To realize an evaluation mode capable of performing the correct evaluation of execution hourly by providing a memory access time control means. CONSTITUTION:An enable signal control circuit 3 sets a comparatively short period of an L level for an enable signal S3 based on an address to receive an access and performs an access at a high speed. Then the circuit 3 sets a long access time for access to an external memory 5. In such conditions, an automatic access time changing function is provided to set a comparatively long period of the L level for the signal S3 and to perform an access at a low speed. In an evaluation mode, the automatic access time changing function of the circuit 3 is set and an access is given at a high speed to the area 5a of the memory 5 allocated to an address where an access is given to an internal memory 2 which is capable of a high speed access in a real application state. Thus, it is possible to perform the correct evaluation of execution hourly for a program which is carried out in an evaluation mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer that has an internal memory and can also access an external memory.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional microcomputer.

As shown in the figure, a microcomputer 1 includes an internal memory 2 such as a ROM. A CPU (not shown) in the microcomputer 1 is an enable signal control circuit 3.
The enable signal S3 output from the internal memory 2 is accessed during the L level period. Further, the CPU can also access the external memory 5, and similarly to the internal memory 2, the enable signal S3 applied via the external terminal P2 is low.
Access the external memory 5 during the level period.

The mode register 4 stores mode data D4, and this mode data D4 can be set by inputting an external input signal S4 from the outside via the external terminal P1.

The enable signal control circuit 3 normally determines whether the memory to be accessed is the internal memory 2 or the external memory 5 based on the address to be accessed in the actual use state, and if the memory to be accessed is the internal memory 2 , the low-level period of the enable signal S3 is relatively short to perform high-speed access; on the other hand, when the memory to be accessed is the external memory 5, the low-level period of the enable signal S3 is relatively long to perform low-speed access. It has a time change function.

This automatic access time changing function allows connection of the external memory 5, which operates at relatively low speed, to the CPU, which operates at high speed.

The microcomputer 1 also has an evaluation mode that is used when developing a program to be written into the internal memory 2 such as a ROM. In the evaluation mode, all memories accessed by the CPU are set to the external memory 5. Therefore, in actual use, the address assigned to the internal memory 2 is also assigned to the area 5a of the external memory 5. Then, the automatic access time changing function of the enable signal control circuit 3 described above becomes disabled, and memory access is forced to be performed at low speed by making the L level period of the enable signal S3 relatively long.

Here, assuming that the microcomputer 1 uses the internal memory 2 during actual use and also connects the area 5b of the external memory 5 to a free address space, we will develop a program using the evaluation mode. Consider the case where you do this.

First, a predetermined external input signal S4 is applied to the mode register 4, and mode data D4 instructing the evaluation knee mode is stored in the mode register 4. Then, C.P.
When the U memory is accessed, the enable signal control circuit 3 always outputs the enable signal S3 in which the L level period of the enable signal S3 is relatively long.

Under this situation, programs are written in the areas 5a and 5b of the external memory 5, and the program is developed while causing the CPU to execute the programs stored in the external memory 5 at any time. That is, program development is performed by replacing the area 5a of the external memory 5 with the address space of the internal memory 2, such as a ROM, used for actual use.

[Problem to be solved by the invention]

Conventional microcomputers are configured as described above, and have an evaluation knowledge mode for program development.
All memories accessed by the CPU are set to the external memory 5, and the automatic access time change function of the enable signal control circuit 3 is disabled, and the access time is always set to a relatively long L level period of the enable signal S3. This will force it to run at a slower speed.

Therefore, in the actual use state, access to the area 5a of the external memory 5 allocated to the address for accessing the internal memory 2, which can be accessed at high speed, is also performed at low speed in the every-changing mode. For this reason, there is a problem in that the temporal execution evaluation of a program executed in the evaluation knowledge mode cannot be performed correctly.

This invention was made to solve the above-mentioned problems, and it is possible to correctly perform temporal execution evaluation.
The purpose of this invention is to obtain a microcomputer with an evaluation mode for program development.

[Means to solve the problem]

A microcomputer according to the present invention has an internal memory, a first mode register that can be accessed from an external memory, can be inputted from the outside, and stores first mode data instructing an evaluation mode. a second mode register that stores second mode data instructing the access time to the memory adapted to the actual usage state during the evaluation mode; CPU to access
and a memory access time control means for controlling the access time of the CPU to the memory in accordance with the actual usage state based on the second mode data.

[Effect]

The memory access time control means in the present invention controls the access time of the CPU to the memory during the evaluation mode, based on the second mode data, in accordance with the actual usage state. On the other hand, the CPU accesses external memory based on the first mode data.

Therefore, even if the CPU accesses external memory during evaluation mode, the CPU
access time to memory is controlled.

〔Example〕

FIG. 1 is a block diagram showing a microcomputer which is an embodiment of the present invention.

As shown in the figure, the microcomputer 1 has a mode register 6 in addition to a mode register 4'. Mode data D6 is stored in the mode register 6, and this mode data D6 can be set by causing a CPU (not shown) to execute a predetermined program. Then, the enable signal S3 of the enable signal control circuit 3
The L level period of is determined based on mode data D6 stored in mode register 6.

Further, mode data D4' is stored in the mode register 4', and this mode data D4' is stored at the external terminal PL.
It can be set by inputting an external input signal S4' from the outside via '.

The enable signal control circuit 3 determines that the memory to be accessed in the actual use state is the internal memory 2 based on the address to be accessed, and relatively shortens the L level period of the enable signal S3 to perform high-speed access or It has an automatic access time changing function that determines that the memory to be accessed during use is the external memory 5 and makes the L level period of the enable signal S3 relatively long to perform low-speed access. This automatic access time changing function is executed when the mode data D6 in the mode register 6 is set to a predetermined value. Note that the other configurations are the same as those of the prior art, so explanations will be omitted.

As before, the microcomputer 1 has an evaluation mode that is used when developing a program to be written into the internal memory 2.

In the evaluation mode, all memories accessed by the CPU are set to the external memory 5. Therefore, in actual use, the address assigned to the internal memory 2 is also assigned to the area 5a of the external memory 5.

However, as described above, even if the evaluation mode is set, the automatic access time change function of the enable signal control circuit 3 is not disabled, and the automatic access time change function of the enable signal control circuit 3 is not disabled, and the automatic access time change function of the enable signal control circuit 3 is not disabled. can do.

Here, assuming that the microcomputer 1 uses the internal memory 2 during actual use and also connects the area 5b of the external memory 5 to a free address space, we will develop a program using the evaluation mode. Consider the case where you do this.

First, a predetermined external human input signal S4' is input to the mode register 4'.
The mode data D4' indicating the evaluation knee mode is stored in the mode register 4'. Then, the CPU accesses the external memory 5 for all addresses. On the other hand, by writing an instruction to store mode data 6 instructing the automatic access time change function in the mode register 6 into the program under development, the automatic access time change function is set when the program is executed. .

Under this situation, programs are written in the areas 5a and 5b of the external memory 5, and the program is developed while causing the CPU to execute the programs stored in the external memory 5 at any time. That is, program development is performed by replacing the area 5a of the external memory 5 with the address space of the internal memory 2, such as a ROM, used for actual use.

At this time, the automatic address change function works, so that when the memory to be accessed is the external memory area 5a corresponding to the internal memory 2 in the actual usage state, the L level period of the enable signal S3 is relatively shortened to allow high-speed access. On the other hand, when the memory to be accessed during actual use is the external memory 5, that is, when accessing the area 5b of the external memory, the L level period of the enable signal S3 is made relatively long to perform low-speed access.

Even in the evaluation mode, in actual use, the area 5a of the external memory 5 is allocated to the address that accesses the internal memory 2, which can be accessed at high speed.
Access will be performed at high speed. the result,
It is possible to correctly perform temporal execution evaluation of a program executed in evaluation knowledge mode.

A mode register 4' that stores mode data D4' that instructs the evaluation mode, and a mode register 6 that stores mode data D6 that instructs the access time to the memory that is suitable for the actual usage state are installed in this column. By providing this independently, even in the evaluation knowledge mode, memory access can be performed assuming the actual usage state, so that the temporal execution evaluation of the executed program can be performed correctly.

Note that when developing a program using the evaluation mode, assuming that only the internal memory 2 is used during actual use, a predetermined external human input signal S4' is given to the mode register 4', and the evaluation The mode data D4' instructing the knee mode is stored in the mode register 4'.
The mode data D6 indicating the access time for the internal memory 2, which is suitable for the actual usage state, may be written in the program under development so as to be stored in the mode register 6.

Furthermore, when developing a program using the evaluation mode, assuming that only the external memory 5 is used during actual use, a predetermined external human power signal S4' is given to the mode register 4', and the evaluation The mode data D4' indicating the knee mode is stored in the mode register 4', and the mode data D6 indicating the access time for the external memory 5, which is suitable for the actual usage condition, is stored in the mode register 6.
You can write it in the program you are developing so that it is stored in .

〔Effect of the invention〕

As described above, according to the present invention, the memory access time control means controls the access time of the CPU to the memory in accordance with the actual usage state based on the second mode data. On the other hand, the CPU, based on the first mode data,
Access external memory.

As a result, even when the CPU is in the evaluation mode for program development in which the CPU accesses external memory, when accessing internal memory during actual use, the access time can be adjusted according to the internal memory. Therefore, it is possible to realize an evaluation knowledge mode that can correctly perform temporal execution evaluation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a microcomputer as an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional microcomputer. 1 is a microcomputer, 2 is an internal memory, 3 is an enable signal control circuit, 4'6 is a mode register, and 5 is an external memory. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A microcomputer that has an internal memory and can also access an external memory, a first mode register that can be input from the outside and stores first mode data that instructs an evaluation mode; a second mode register that stores second mode data indicative of memory access time adapted to actual usage conditions during the evaluation mode; and a CPU that accesses external memory based on the first mode data. and a memory access time control means for controlling the access time of the CPU to the memory in accordance with the actual usage state based on the second mode data.