JP2731618B2 - emulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator that emulates the function of a program executed by a single-chip microcomputer when the program is developed, and more particularly, to an evaluation device that is integrated into a single chip. The present invention relates to an emulator including a chip (evaluation chip; hereinafter, referred to as an evaluation chip).

[Prior Art] An EVA chip has a function of emulating a central processing unit (hereinafter referred to as a CPU) built in a single-chip microcomputer, and a peripheral control device (hereinafter referred to as an I / O) built in a single-chip microcomputer. O)
, A function to output the execution status of the CPU, a break function to temporarily suspend the execution of the CPU, and the like.

By the way, in a single-chip microcomputer, a CPU is used as a core, and I / Os are configured according to application fields, thereby expanding product types. For this reason, recently, this kind of evaluation chip is configured by a CPU evaluation chip that emulates a CPU and an I / O evaluation chip that emulates an I / O.

FIG. 8 is a block diagram showing a configuration of a conventional CPU evaluation chip.

The micro ROM 1 stores a micro program for controlling execution of instructions in order to emulate a CPU function. The instruction code fetched from outside via the input terminal 2 is stored in the instruction register 4 via the input buffer 3. The instruction code stored in the instruction register 4 is supplied to the micro sequence unit 5. The micro-sequence unit 5 stores the micro ROM 1 in accordance with the given instruction code.
Generates an entry address that activates the microprogram of. The address from the micro sequence unit 5 is given to the address decoder 6. The address decoder 6 decodes an address from the micro sequence unit 5 and selects a micro code stored in the micro ROM 1. The selected microcode is input to the control signal generation circuit 7. The control signal generation circuit 7 decodes the input microcode to generate various control signals, and converts these control signals into an instruction fetch control circuit 11, a bus control circuit 12,
It is supplied to the arithmetic control circuit 13, the I / O / memory control circuit 14, and the like. Thereby, the function of the instruction code is executed.

As shown in FIG. 9, the micro ROM 1 includes a general-purpose instruction microprogram A for controlling the execution of general-purpose instructions such as calculation, transfer, storage, and branching of instruction processing of processing data of a CPU incorporated in the evaluation chip, and I Microprogram B for dedicated instructions that controls the execution of dedicated instructions that handle / O data processing
Bets is stored in each address 0000 _H ~03FF _H and 0400 _H ~05FF _H.

[Problems to be Solved by the Invention] However, in the above-described conventional emulator, since the general-purpose instruction microprogram and the dedicated instruction microprogram are stored in one microROM,
Only the functions of a single-chip microcomputer having an I / O corresponding to the stored dedicated instruction microprogram can be emulated. For this reason, when emulating the functions of a single-chip microcomputer having an I / O different from the above-mentioned I / O when developing a variety of single-chip microcomputers, share the CPU evaluation chip and use only the I / O evaluation chip.
There was a problem in that it was not possible to take measures to change according to the type of I / O, and a CPU evaluation chip had to be newly developed for each type.

The present invention has been made in view of such a problem, and has as its object to provide an emulator that can support a plurality of types of single-chip microcomputers having a common CPU and different I / Os.

[MEANS FOR SOLVING THE PROBLEMS] An emulator according to the first invention of the present application is a microprogram for general-purpose instructions relating to control of a central processing unit of a single-chip microcomputer to be emulated and a dedicated instruction relating to control of a peripheral controller. First storage means for storing a microprogram, at least one second storage means for storing dedicated instruction microprogram information related to control of a peripheral control device different from the peripheral control device, One of a dedicated instruction microprogram output from the first storage unit and a dedicated instruction microprogram based on information output from the second storage unit is selected and executed based on a given selection signal. And means for performing the following.

The emulator according to the second invention of the present application stores a general-purpose instruction microprogram related to control of a central processing unit of a single-chip microcomputer to be emulated and a dedicated instruction microprogram related to control of a peripheral control device. Storage means, input means for externally inputting microprogram information for a dedicated command relating to control of a peripheral control device different from the peripheral control device, and information input via the input means based on a selection signal given from the outside And a means for selecting and executing one of a dedicated instruction microprogram based on the above and a dedicated instruction microprogram output from the storage means.

Here, the dedicated instruction microprogram information supplied from the second storage means or from the outside means not only the dedicated instruction microprogram itself but also a logical operation with another dedicated instruction microprogram. It also includes information for synthesizing the dedicated instruction microprogram.

[Operation] According to the first invention of the present application, the I / O of a specific type of single-chip microcomputer is stored in the first storage means.
A micro-program for exclusive instructions for controlling the
The second storage means stores a dedicated instruction microprogram corresponding to another type of single-chip microcomputer having an I / O different from that of the single-chip microcomputer or information defining the same. Then, in response to an external selection signal, the dedicated instruction microprogram from the first storage means and the dedicated instruction microprogram output from the second storage means or information output from the second storage means And the dedicated instruction microprogram synthesized is switched and executed.

According to the second aspect of the present invention, a dedicated instruction microprogram or information for generating the dedicated instruction microprogram is supplied from an external memory or the like instead of the second storage means, and the dedicated instruction microprogram stored in the storage means is provided. And executed.

Therefore, according to the present invention, it is possible to emulate not only the function of the specific single-chip microcomputer but also the function of the single-chip microcomputer having a different I / O from the specific single-chip microcomputer by selecting the selection signal. . Therefore, even when developing a single-chip microcomputer, only one kind of CPU evaluation chip is required, and the cost for developing the evaluation chip can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a CPU evaluation chip according to a first embodiment of the present invention. In FIG. 1, the same components as those of the conventional circuit shown in FIG. 8 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

This CPU evaluation chip is provided with two micro ROMs 1 and 21. Micro ROM1, as shown in FIG. 2 (a), 1024 controlling the address 0000 _H ~03FF _H, arithmetic processing data of the internal CPU, transfer, running generic instruction at the branch, such as storage and instruction processing stores the microprogram a for a general-purpose instruction, the address 0400 _H ~05FF _H,
Those obtained by storing only instructions for the microprogram B ₁ of 512 controlling the execution of the dedicated instruction handling data I / O processing for a particular single-chip microcomputers. As shown in FIG. 2 (b), the micro ROM 21 controls execution of a dedicated instruction for handling I / O data processing of another single-chip microcomputer.
The dedicated instructions for the microprogram B ₂ of 12 steps, is made and stored in the address 0400 _H ~05FF _H.

Address decoders 6 and 22 are provided corresponding to these micro ROMs 1 and 21, respectively. Address decoder 6,
A decoder 22 decodes the address supplied from the micro sequence unit 5 and selects a micro code stored in the micro ROMs 1 and 21.

On the other hand, the evaluation chip is provided with a selection terminal 23 for switching the dedicated instruction microprogram.
The selection signal S _S input from the selection terminal 23 is supplied to the address decoder 22 via the input buffer 24, and further supplied to the address decoder 6 via the inverter 25.

Microcode M supplied from microROM1,21 respectively
C ₁ and MC ₂ are input to the control signal generation circuit 26. Further, the selection signal S _S input via the input buffer 24 is also input to the control signal generation circuit 26.

The control signal generating circuit 26 is configured, for example, as shown in FIG. That is, the microcodes MC ₁ and MC ₂ output from the micro ROMs ₁ and 21, respectively, are AND gates 31 and 3 respectively.
Entered in 2. The output of the AND gate 31 is the selection signal S
A is selected by a signal obtained by inverting _S by the inverter 33, and A
The output of the ND gate 32 is selected by selection signal S _S. The selected microcode is supplied to the decoder 35 via the OR gate 34. The decoder 35 decodes the input microcode to control various control signals S _C1 , S _C2 ,
, _SCn are generated, and these control signals are supplied to an instruction fetch control circuit 11, a bus control circuit 12, an arithmetic control circuit 13, an I / O / memory control circuit 14 and the like built in the evaluation chip.

Next, the operation of the thus configured CPU evaluation chip according to the present embodiment will be described.

If the instruction code inputted from the input terminal 2 is the universal instruction from microsequence unit 5, the address 0000 because either _{H ~03FF H} is outputted, by the address decoder 6 generic instruction of the microprogram A for Microcodes are selected, and these codes are supplied to the control signal generation circuit 26. Thus, the control signal generation circuit 26 outputs various control signals S _C1 based on the execution of the general-purpose instruction.
To S _Cn are output.

Next, a case where the instruction code input from the input terminal 2 is a dedicated instruction will be described.

When the selection signal S _S input from the selection terminal 23 is set to L level, the selection signal S _S is selected from the address decoder 6 and the micro RO is selected.
Microcode MC ₁ of M1 address 0400 _H ~05FF microprogram dedicated instructions from _H B ₁ is selected, the codes are applied to the control signal generating circuit 26. In the control signal generation circuit 26, since the selection signal S _S is at the L level,
Microcode MC ₁ from ND gate 31 is selected and inputted to the decoder 35. Thereby, the control signal generation circuit 26
From the various control signals S ₁ to S _n based on the execution of the dedicated instruction for a particular I / O is output.

On the other hand, when the selection signal S _S is input from the selection terminal 23 to H level, the address decoder 22 is selected, microcode MC ₂ dedicated instruction for microprogram B ₂ from the address 0400 _H ～05FF _H micro ROM21 is selected These codes are supplied to the control signal generation circuit 26. The control signal generating circuit 26, is input from the fact selection signal S _S is H level, the microcode MC ₂ is selected and the decoder 35 from the AND gate 32. Thus, from the control signal generating circuit 26, various control signals S ₁ to S _n based on the execution of the dedicated instruction for different I / O from the above specific I / O is output.

As described above, according to the CPU evaluation chip of the present embodiment, by controlling the level of the selection terminal 23, even if the same instruction code is input for the dedicated instruction, the two micro ROMs
It is possible to execute different microprograms stored respectively in the first and the second.

FIG. 4 is a block diagram showing a configuration of a CPU evaluation chip according to a second embodiment of the present invention. In FIG. 4, the same components as those in the circuits shown in FIGS. 1 and 8 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

In this embodiment, a PROM (programmable ROM) 41 is used as second storage means for storing another dedicated instruction microprogram. Therefore, the evaluation chip is provided with a write control circuit 42 for writing a program in the PROM 41. The write control circuit 43 is connected to a write control terminal 43 and a data input terminal 44. Further, this circuit is provided with an address input terminal 45, and an address input through the address input terminal 45 is given to the address decoder 22.

In this embodiment, the selection terminal 23 is set to the H level, the write control terminal 43 is set to the write state, and the address 0400 _{H to} 05F
While sequentially supplying F _H, by the data input terminal 44 and writes the microprogram, micro ROM1
And the PROM 41 store different dedicated instruction microprograms, respectively, and can execute different I / O dedicated instructions by inputting the same instruction code.

FIG. 5 is a block diagram showing a configuration of a CPU evaluation chip according to a third embodiment of the present invention. This embodiment is similar to the fourth embodiment.
In this example, a RAM (random access memory) 51 is used in place of the PROM 41 shown in FIG.
By writing a special instruction microprogram different from the contents of the micro ROM 1 in the M51, it is possible to execute different I / O dedicated instructions by inputting the same instruction code.

According to the second and third embodiments, since the writing of the second dedicated instruction microprogram is easy, it is possible to more flexibly cope with the variety of single-chip microcomputers.

FIG. 6 is a block diagram showing a configuration of a CPU evaluation chip according to a fourth embodiment of the present invention. This embodiment is an example in which another dedicated instruction microprogram is input from the external memory 61 instead of providing the second storage means inside the chip.

The address output from the micro sequence unit 5 is provided to the external memory 61 from the address output terminal 63 via the output buffer 62. The external memory 61, to the address 0400 _H ~05FF _H, are stored different dedicated instructions for the microprogram as stored in the micro ROM 1. Then, the microcode read from the external memory 61 is given to the control signal generating circuit 26 via the data input terminal 64.

According to this embodiment, the micro sequence unit 5
The dedicated instruction microprogram read from the external memory 61 and the dedicated instruction microprogram read from the micro ROM 1 are selected according to the address designated by the selection signal _SS , and used.
Dedicated instructions for different I / Os can be executed by inputting the same instruction code.

In each of the above-described embodiments, another dedicated instruction microprogram different from the microROM 1 is stored in the ROM, PROM, RAM, external memory, or the like. May be stored.

Figure 7 includes information D _I stored in another memory and micro ROM 1, by logically combining the microcode MC ₁ for the dedicated instruction from the micro ROM 1, microcode MC ₂ for different dedicated instruction , And shows the configuration of a control signal generation circuit. This circuit is different from the circuit of FIG. 3 in that an exclusive OR gate 71 is provided before the AND gate 32 so that the microcode MC ₁
And an exclusive OR result between the information D _I as microcode M ₂ lies in that then supplied to the AND gate 32.

According to this embodiment, when only a part of the two types of dedicated instruction microprograms is different, there is an advantage that data only needs to be written to an address corresponding to the part.

[Effects of the Invention] As described above, according to the present invention, a plurality of types of dedicated instruction microprograms executed for the same instruction code can be selectively executed by the selection signal. Emulation of multiple types of single-chip microcomputers with a common CPU and different I / Os can be executed using a common CPU evaluation chip. Therefore, even when developing a single-chip microcomputer, only one kind of CPU evaluation chip is required, and the cost for developing the evaluation chip can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a CPU evaluation chip according to a first embodiment of the present invention, FIG. 2 is a memory map diagram of a micro ROM in the chip, FIG. 3 is a block diagram of a control signal generation circuit in the chip, FIG. FIG. 4 is a block diagram of a CPU evaluation chip according to a second embodiment of the present invention, FIG. 5 is a block diagram of a CPU evaluation chip according to a third embodiment of the present invention, and FIG. 6 is a fourth embodiment of the present invention. FIG. 7 is a block diagram of a control signal generation circuit according to a fifth embodiment of the present invention, FIG. 8 is a block diagram of a conventional CPU evaluation chip, and FIG. FIG. 3 is a memory map diagram of a micro ROM. 1,21; Micro ROM, 2; Input terminal, 3,24; Input buffer,
4; instruction register, 5; micro sequence unit, 6, 22; address decoder, 7, 26; control signal generation circuit, 11; instruction fetch control circuit, 12; bus control circuit, 1
3; operation control circuit, 14; I / O / memory control circuit, 23; selection terminal, 25, 33; inverter, 31, 32; AND gate, 34; OR gate, 35; decoder, 41; PROM, 42; Write control terminal, 43; write control terminal, 44, 64; data input terminal, 45; address input terminal, 51; RAM, 61; external memory, 62; output buffer, 63; address output terminal, 71; exclusive logic Sum gate

Claims (2)

(57) [Claims] A single chip to be emulated.
A first storage unit storing a general-purpose instruction microprogram related to control of the central processing unit of the microcomputer and a dedicated instruction microprogram related to control of the peripheral control device; and control of a peripheral control device different from the peripheral control device. At least one second storage means for storing dedicated instruction microprogram information, a dedicated instruction microprogram output from the first storage means based on a selection signal given from the outside, and the second instruction means. Means for selecting and executing one of a dedicated instruction microprogram based on information output from the storage means. 2. A single chip to be emulated.
Storage means for storing a general-purpose instruction microprogram related to control of the central processing unit of the microcomputer and a dedicated instruction microprogram related to control of the peripheral control device; and a dedicated instruction related to control of a peripheral control device different from the peripheral control device. Input means for externally inputting microprogram information for use, a dedicated instruction microprogram output from the storage means based on a selection signal given from the outside, and a dedicated instruction microprogram based on information input via the input means. Means for selecting and executing one of the programs.