JPH0319221A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0319221A JPH0319221A JP15344289A JP15344289A JPH0319221A JP H0319221 A JPH0319221 A JP H0319221A JP 15344289 A JP15344289 A JP 15344289A JP 15344289 A JP15344289 A JP 15344289A JP H0319221 A JPH0319221 A JP H0319221A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- polycrystalline silicon
- silicon oxide
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 13
- 230000008018 melting Effects 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000000926 separation method Methods 0.000 abstract description 5
- 229920006254 polymer film Polymers 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WXANAQMHYPHTGY-UHFFFAOYSA-N cerium;ethyne Chemical compound [Ce].[C-]#[C] WXANAQMHYPHTGY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関し、特にその製造工
程における高融点金属ポリサイドの配線、または多結晶
シリコン膜の配線の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high melting point metal polycide wiring or a polycrystalline silicon film wiring in the manufacturing process.
従来の技術
近年、半導体装置の高密度集積化により微細化が進んで
きている。BACKGROUND OF THE INVENTION In recent years, semiconductor devices have been increasingly miniaturized due to higher density integration.
以下に従来の高融点金属ポリサイド配線の製造方法につ
いて説明する。第２図（ａ）に示すように、シリコン基
板１に、酸化技術゛などを用い第１シリコン膜であるゲ
ート絶縁膜２を形成する。次に、第２図（ｂ）に示すよ
うに、ゲート絶縁膜２上に、第１多結晶シリコン膜３、
高融点金属シリサイド膜４を堆積する。次に第２図（Ｃ
）に示すように、フォトレジストなどにより高融点金属
ポリサイド配線形成用マスクパターン７を形成し、続い
て、第２図（ｄ）のように、高融点金属シリサイド膜、
多結晶シリコン膜のエッチングを行う。前記マスクパタ
ンを除去すると第２図（ｅ）に示すように、高融点金属
ポリサイド配線が形成される。A conventional method for manufacturing high melting point metal polycide wiring will be described below. As shown in FIG. 2(a), a gate insulating film 2, which is a first silicon film, is formed on a silicon substrate 1 using an oxidation technique or the like. Next, as shown in FIG. 2(b), a first polycrystalline silicon film 3,
A high melting point metal silicide film 4 is deposited. Next, Figure 2 (C
), a mask pattern 7 for forming high melting point metal polycide wiring is formed using photoresist or the like, and then, as shown in FIG. 2(d), a high melting point metal silicide film,
Etching the polycrystalline silicon film. When the mask pattern is removed, a high melting point metal polycide wiring is formed as shown in FIG. 2(e).
発明が解決しようとする課題
従来の技術では、露光装置のもつ解像限界寸法以上のセ
パレーションを出すことができず、チップサイズ縮小化
の妨げとなるという問題点を有していた。Problems to be Solved by the Invention Conventional techniques have had the problem of not being able to produce a separation larger than the resolution limit dimension of the exposure apparatus, which hinders chip size reduction.
本発明は上記従来の問題点を解決するもので、露光装置
のもつ解像限界寸法以上のセパレーションを出すことの
できる半導体装置の製造方法を提供することを目的とす
る。The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can produce a separation larger than the resolution limit dimension of an exposure apparatus.
課題を解決するための手段
この目的を達威するために本発明の半導体装置の製造方
法は、高融点金属ポリサイド膜の一主面上に、シリコン
酸化膜を形成する工程と、前記一主面上に多結晶シリコ
ン膜を形成する工程から構威されている。Means for Solving the Problems In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes the steps of forming a silicon oxide film on one main surface of a high melting point metal polycide film, and The process starts from the step of forming a polycrystalline silicon film on top.
作用
この構成によって露光装置のもつ解像限界寸法以上のセ
パレーションを実現することができる。Function: With this configuration, it is possible to realize a separation larger than the resolution limit dimension of the exposure apparatus.
実施例
以下本発明の一実施例について、第１図に従って説明す
る。EXAMPLE An example of the present invention will be described below with reference to FIG.
第１図（ａ）に示すように、半導体基板１の一主面上に
、熱酸化技術などを用い第１シリコン酸化膜であるゲー
ト絶縁膜２を３０ｎｍ程度形成する。As shown in FIG. 1(a), a gate insulating film 2, which is a first silicon oxide film, is formed to a thickness of about 30 nm on one main surface of a semiconductor substrate 1 using a thermal oxidation technique or the like.
次に第１図（ｂ）に示すように、前記一主面上にＣＶＤ
技術などを用い第１多結晶シリコン膜３を１５０ｎｍ程
度、高融点金属シリサイド膜４を１５０ｎｍ程度堆積す
る。次に、第１図（ｅ）に示すように、前記一主面上に
熱酸化技術などを用い第２シリコン酸化膜５を５ｎｍ程
度形成する。次に、第１図（ｄ）に示すように、前記一
主面上に、ＣＶＤ技術などにより第２多結晶シリコン膜
６を２０ｎｍ程度堆積する。次に、第１図（ｅ）に示す
ように、前記一主面上にフォトレジストなどにより高融
点金属ポリサイド配線形戒用マスクパタン７を形戒する
。次に、第１図（ｆ）に示すように、ＥＣＲによるドラ
イエッチ技術でＳＦｅ，Ｃ２Ｃｅ ２Ｆ４，Ｈｅガスを
用い第２多結晶シリコン膜６をオーバーエッチすること
により、ボリマー８が形成される。次に、第１図（ｇ）
に示すように、ＥＣＨによるドライエッチ技術を用い、
ボリマーをマスクとして第２シリコン酸化膜５をＣ ４
Ｃ ｅ ａ Ｆ ８ｙ Ｈ ｅガスでエッチングし、
高融点金属シリサイド膜４、第１多結晶シリコン膜３を
ＳＦ６，Ｃ２Ｃｅ ２Ｆ４．Ｈｅガスでエッチングする
。次に、第１図（Ｗに示すように、プラズマエッチング
技術を用い高融点金属ポリサイド配線形成用マスクバタ
ン及びボリマーを除去する。Next, as shown in FIG. 1(b), CVD is applied onto the one main surface.
The first polycrystalline silicon film 3 is deposited to a thickness of about 150 nm, and the refractory metal silicide film 4 is deposited to a thickness of about 150 nm using a technique or the like. Next, as shown in FIG. 1(e), a second silicon oxide film 5 is formed to a thickness of about 5 nm on the one main surface using a thermal oxidation technique or the like. Next, as shown in FIG. 1(d), a second polycrystalline silicon film 6 of about 20 nm is deposited on the one main surface by CVD technology or the like. Next, as shown in FIG. 1(e), a refractory metal polycide wiring pattern mask pattern 7 is formed on the one main surface using a photoresist or the like. Next, as shown in FIG. 1(f), a polymer 8 is formed by overetching the second polycrystalline silicon film 6 using SFe, C2Ce2F4, and He gas using a dry etching technique using ECR. Next, Figure 1 (g)
As shown in , using dry etching technology by ECH,
The second silicon oxide film 5 is coated with C4 using the polymer as a mask.
Etching with Ce a F 8y He gas,
The high melting point metal silicide film 4 and the first polycrystalline silicon film 3 are made of SF6, C2Ce 2F4. Etch with He gas. Next, as shown in FIG. 1 (W), a plasma etching technique is used to remove the high melting point metal polycide wiring forming mask button and polymer.
なお、本実施例では、第２多結晶シリコン膜のエッチン
グ工程におけるエッチング技術及びガスの種類は上記実
施例に限るものではなく、これらを適当条件に設定する
ことにより実現できる。In this example, the etching technique and gas type in the etching process of the second polycrystalline silicon film are not limited to those in the above example, but can be realized by setting these to appropriate conditions.
発明の効果
本発明は、露光装置のもつ解像限界寸法以上のセパレー
ションを実現することができ、ゲート寸法または、配線
寸法が同じルールであれば、ピッチを狭くすることがで
き、よりチップサイズの縮小化をはかれ、チップ単価の
低減ができる。Effects of the Invention The present invention can realize a separation that is larger than the resolution limit dimension of the exposure equipment, and if the gate dimensions or wiring dimensions are the same, the pitch can be narrowed, and the chip size can be further reduced. It can be downsized and the chip unit price can be reduced.
第１図は本発明の一実施例における半導体装置の製造方
法の工程断面図、第２図は従来の半導体装置の製造方法
の工程断面図である。FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional method for manufacturing a semiconductor device.
Claims (1)
る工程と、前記一主面上に第１多結晶シリコン膜、ある
いは高融点金属ポリサイド膜を形成する工程と、前記一
主面上に第２シリコン酸化膜を形成する工程と、前記一
主面上に第２多結晶シリコン膜を形成する工程と、前記
一主面上にフォトレジストによりマスクパタンを形成す
る工程と、前記第２多結晶シリコン膜を前記マスクパタ
ンによりドライエッチングする工程と、第２シリコン酸
化膜および高融点金属ポリサイド膜あるいは、第１多結
晶シリコン膜をエッチングする工程を含むことを特徴と
する半導体装置の製造方法。a step of forming a first silicon oxide film on one main surface of a semiconductor substrate; a step of forming a first polycrystalline silicon film or a high melting point metal polycide film on the one main surface; forming a second polycrystalline silicon film on the one main surface; forming a mask pattern using photoresist on the one main surface; A method for manufacturing a semiconductor device, comprising the steps of dry etching a polycrystalline silicon film using the mask pattern, and etching a second silicon oxide film and a high melting point metal polycide film, or a first polycrystalline silicon film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15344289A JPH0319221A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15344289A JPH0319221A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319221A true JPH0319221A (en) | 1991-01-28 |
Family
ID=15562631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15344289A Pending JPH0319221A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319221A (en) |
-
1989
- 1989-06-15 JP JP15344289A patent/JPH0319221A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100376628B1 (en) | Conductive Interconnect Structure in Integrated Circuit and Method of Forming Conductive Interconnect | |
| US6001538A (en) | Damage free passivation layer etching process | |
| US5792672A (en) | Photoresist strip method | |
| US6211557B1 (en) | Contact structure using taper contact etching and polycide step | |
| JP3041972B2 (en) | Method for manufacturing semiconductor device | |
| JP2001230233A (en) | Method for manufacturing semiconductor device | |
| JP2907314B2 (en) | Method for manufacturing semiconductor device | |
| US6833232B2 (en) | Micro-pattern forming method for semiconductor device | |
| JPH0319221A (en) | Manufacture of semiconductor device | |
| JPH05121371A (en) | Method of manufacturing semiconductor device | |
| JPH05206083A (en) | Production of semiconductor device | |
| KR100228275B1 (en) | Manufacturing Method of Semiconductor Device | |
| JPH0484422A (en) | Formation of fine metal wiring | |
| KR100257770B1 (en) | Fine conductive film pattern formation method of semiconductor device | |
| JPH0497523A (en) | Manufacture of semiconductor device | |
| JPS6119132A (en) | Manufacture of semiconductor device | |
| JPH07135198A (en) | Etching | |
| KR100265842B1 (en) | Semiconductor device manufacturing method | |
| JPH03125427A (en) | Manufacture of semiconductor device | |
| JPS59175124A (en) | Manufacture of semiconductor device | |
| JPS583244A (en) | Manufacture of semiconductor device | |
| JPH0294439A (en) | Manufacture of semiconductor device | |
| JPH06295888A (en) | Fabrication of semiconductor device | |
| JP3211634B2 (en) | Method for manufacturing semiconductor device | |
| JPH05283378A (en) | Manufacture of semiconductor device |