JPH03156977A - Vertical mosfet - Google Patents

Abstract

PURPOSE:To protect a MOS cell from breakdown due to parasitic transistors by providing an N-type diffused region in contact with a well region, the avalanche withstand voltage is lower than that of the MOS cell. CONSTITUTION:A MOS cell is surrounded by a P-type well 25, which is in contact with a source electrode 32. An N-type diffused region 33 is formed between the well region 25 and a guard ring 26 at the surface of an N- semiconductor layer 23. The diffused layer 33 provides a P-N junction that has a higher concentration than the P-N junction between the well region 25 and the semiconductor layer 23. Accordingly, the avalanche withstand voltage of the well region 25 is lower than that of the MOS cell. In this device, therefore, the avalanche breakdown occurs in the well region 25, and the breakdown current (i) is allowed to flow through the well region 25 to a source electrode 32. This structure thus protects the MOS cell from breakdown due to parasitic transistors.

Description

Detailed description of the invention (a) Industrial application field The present invention provides a vertical MO8FET with increased avalanche resistance.
Regarding.

(Note) A conventional vertical MOS FET, as shown in Fig. 3, consists of an N- type silicon substrate (2
) is used as a drain, and gate electrodes (poly-Si gates) (3) are arranged on the surface thereof at predetermined distances of l--, and the substrate (2) is placed so as to form a channel section under the gate electrode (3). A P-type diffusion region (4) and an N+-type source region (5) are formed on the surface, and by applying a voltage to the gate, the drain current D8 passing through the P-type diffusion region (4) (channel part) under the gate is generated. MOSFET to control
(For example, Japanese Patent Application Laid-Open No. 63-260
Publication No. 176). (6) is an electrode, and (7) is a guard ring.

Such a vertical MO8FET is capable of high-speed switching of large currents, so it can be used in motor control, switching regulators, and C
It is widely used for RT deflection.

(c) Problems to be solved by the invention However, when switching the reactor load (8) with the MO8I-transistor (9>) as shown in FIG.
At the moment when the reactor load (8) is cut off, a large surge voltage (10) is generated with a high current change rate di/dt, and this surge voltage is applied between the source and drain of the MOS transistor (9). The MOS transistor (9) is easily applied to the avalanche region.

The MO9+- transistor (9) to which the voltage is applied up to the avalanche region is mainly connected to the P-type diffusion region (4) as shown in FIG.
and the N-type substrate (2) form a junction diode (11
) tries to absorb the current by avalanche breakdown. However, the MO3+- transistor (9) uses the N+ source region (5) as the emitter, the P-type diffusion region (4) as the base,
A parasitic transistor (with N-type substrate (2) as its collector)
12) is inevitably formed, and the bottom of the N+ source region (5) has a pinch structure, so the PN junction between the source region (5) and the P-type diffusion region (4) has a pinch resistance (13 ) easily reaches a forward biased potential difference, causing the parasitic transistor (12) to become conductive. - Once the parasitic transistor (12) becomes conductive, the blocking voltage of the MOS transistor is V of the parasitic transistor (12). 8o
As a result, avalanche current flows uncontrollably through the activated cell, resulting in destruction of the device.

4-(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems, and a P-type well region (25) that does not operate as a MOS cell is provided so as to surround the MOS cell portion. The source electrode (32) is brought into contact with the region (25), and the well region (25) and the N- −
By providing an N-type diffusion region (33) that forms a higher concentration junction than a PN junction with the type semiconductor layer (23), it is possible to prevent element destruction during avalanche breakdown.
It provides T.

(E) Function According to the present invention, since the N-type diffusion region (33) forms a higher concentration junction than the N-type semiconductor layer (32), the avalanche breakdown voltage of the well region (25) can be lowered by the avalanche breakdown voltage in the MOS cell. Therefore, avalanche breakdown of the device first occurs in the well region (25), and the breakdown current i is passed through the well region (25) to the source electrode (
32), so that the breakdown current i does not need to flow into the MOS cell.

(F) Example An example of the present invention will be described below in detail with reference to the drawings. FIG. 1 and FIG. 2 are a sectional view and a plan view, respectively, for explaining the present invention.

The silicon semiconductor substrate 21) serving as the common drain has a two-layer structure including an N+ type semiconductor layer (22) for forming a back electrode and an N type semiconductor layer (23). N-type semiconductor layer (2
3), a P-type diffusion region (24) is formed in a grid pattern as shown in FIG. 2, and a P-type well region (25) is separated from the P-type diffusion region (24) so as to surround it. It is formed by Further outside the well region (25),
P-type guard ring regions (26) are formed in multiple layers to surround the well region (25). (27)
is an N-type channel stopper, and (28) is a field electrode. Note that the patterns of the vertical MO8FET include a mesh gate type in which P-type diffusion regions (24) are dotted and the gate electrode is in a lattice shape, and a mesh gate type in which the P-type diffusion regions (24) are in a lattice shape and the gate electrode is dotted. There are two types of multi-gate type, and FIG. 2 shows the multi-gate type.

5-6 On the surface of the P type diffusion region (24), N+ type source regions (29) are formed so as to surround each of the lattices of the lattice pattern, and the source region (29) and the N− type semiconductor layer (23) surface are formed. The surface of the P-type diffusion region (24) sandwiched by The gate electrodes are arranged so as to cover each of the two meshes.Individually independent gate electrodes (
31) are commonly connected by a comb-shaped aluminum electrode and connected to a not-shown bonding pad for external connection. On the surface of the P-type diffusion region (24), a P-type diffusion region (
A source electrode (32) of Al1, i-5i, etc., which contacts both the N+ source region (24) and the N+ source region (29), is formed in a comb-like shape and connected to a source bonding pad (not shown).

An N+ source region (2) is formed on the surface of the P-type well region (25).
9) is not formed. The well region (25) is now in a floating state in which MO3 cannot operate regardless of the presence or absence of the gate electrode (31).The channel expansion introduced into the P-type diffusion region (24) also occurs in the well region ( 25) will not be introduced.

Then, on the surface of the N-type semiconductor layer (23) sandwiched between the well region (25) and the guard link 26), an N-type diffusion region (3) having a higher impurity concentration than the N-type semiconductor layer (23) is formed.
3) Form. It may also be introduced between the guard rings (26) and between the well region (25) and the P-type diffusion region (24), but the N-type diffusion region (33) is replaced with the P-type diffusion region (33). region (24) and its channel diffusion.As a result, the well region (25)
) and the N type diffusion region (33) are connected to the P type diffusion region (24) and the N type diffusion region (24).
Since a PN junction with a higher concentration than the PN junction of the - type semiconductor layer (23) is formed, the avalanche breakdown voltage of the well region (25) can be smaller than the avalanche breakdown voltage of the MOS cell.

In a vertical MOS FET with such a configuration, if a reverse voltage exceeding the avalanche region is applied between the source and drain due to the back electromotive force of the reactor load, the MOS
Since the withstand voltage in the well region (25) is lower than that in the cell region,
Breakdown current i flows through the well region (25) to the source electrode (
32). Since there is no source region (29) in the well region (25), there is no possibility that a parasitic transistor effect will occur, and the well region (25) and the P-type diffusion region (29)
4>, the breakdown current i will not flow into the MOS cell and make the parasitic transistor conductive. Therefore, by actively flowing the breakdown current i in the well region (25), the inside of the MOS cell can be protected from destruction caused by the parasitic transistor.

(g) Effects of the invention As explained above, according to the invention, the well region (25
) By providing an N-type diffusion region (33) adjacent to the well region (25), the avalanche breakdown voltage in the well region (25) can be reduced by MOS.
The well area (25) is made smaller than the one inside the cell.
As a result, the breakdown current can be actively applied to the MOS
The inside of the cell can be protected from destruction due to parasitic transistor effects.

Therefore, since the MO8 element has a large avalanche breakdown capacity, it is easy to design a protection circuit such as a snubber circuit when incorporating it into an electronic device, and the device can be simplified.

[Brief explanation of the drawing]

1 and 2 are a sectional view and a plan view, respectively, for explaining the present invention, and FIGS. 3 to 5 are a sectional view, a circuit diagram, and an enlarged sectional view, respectively, for explaining a conventional example. .

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type serving as a common drain, a diffusion region of an opposite conductivity type formed on the surface of the semiconductor substrate, and a diffusion region of the opposite conductivity type that is separated from the diffusion region and surrounds the diffusion region of the opposite conductivity type. a well region of opposite conductivity type formed in the well region, a guard ring of opposite conductivity type surrounding the outer side of the well region, a source region of one conductivity type formed on the surface of the diffusion region of the opposite conductivity type, and the source region. a gate electrode disposed on a channel portion sandwiched between the surface of the substrate via an insulating film; and a source electrode in contact with both the source region and the reverse conductivity type diffusion region and also in contact with the well region. , a diffusion region of one conductivity type provided on the surface of the substrate between the well region and the guard ring so as to form a PN junction with a higher impurity concentration than the substrate, and an avalanche breakdown voltage of the guard ring portion is set to MOS A vertical MOSFET characterized by being smaller than the avalanche breakdown voltage of the cell part. (2) The vertical MOSFET according to claim 1, wherein the one conductivity type diffusion region is also formed between the guard ring regions.