JPH0286150U - - Google Patents
Info
- Publication number
- JPH0286150U JPH0286150U JP16603088U JP16603088U JPH0286150U JP H0286150 U JPH0286150 U JP H0286150U JP 16603088 U JP16603088 U JP 16603088U JP 16603088 U JP16603088 U JP 16603088U JP H0286150 U JPH0286150 U JP H0286150U
- Authority
- JP
- Japan
- Prior art keywords
- channel fet
- switch control
- pnp transistor
- input signal
- vertical pnp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は、本考案に係るコンプリメンタリ出力
回路を有する半導体装置の一実施例を示す半導体
電子回路図である。第２図は、同実施例の判導体
形成構造を示す縦断面図である。第３図は、従来
のコンプリメンタリ出力回路を有する反導体装置
の一例を示す半導体電子回路図である。第４図は
、同従来例の改善例を示す半導体電子回路図であ
る。
１……入力端子、２，４……Ｎチヤネル型ＦＥ
Ｔ、３，４１……Ｐチヤネル型ＦＥＴ、５……出
力端子、１０……第１スイツチ回路、２０……第
２スイツチ回路、３０……第１スイツチ制御回路
、４０……第２スイツチ制御回路、２１……縦型
ＰＮＰトランジスタ、Ｒ１，Ｒ３……バイアス抵
抗、Ｒ２……電流制限抵抗、Ｃ０……ゲート・ド
レイン間静電容量、１０１……Ｐ型半導体基板、
１０２……アイソレイシヨン領域、１０３……Ｎ
型ベース領域、１０４……Ｐ型エミツタ領域、１
０５……Ｐ型ドレイン領域、１０６……Ｎ型ベー
スコンタクト領域、１０７……絶縁膜、１０８…
…ポリシリコンゲート、１０９……エミツタ電極
、１１０……ゲート電極、１１１……ドレイン・
ベース配線。
FIG. 1 is a semiconductor electronic circuit diagram showing an embodiment of a semiconductor device having a complementary output circuit according to the present invention. FIG. 2 is a longitudinal cross-sectional view showing the conductor forming structure of the same embodiment. FIG. 3 is a semiconductor electronic circuit diagram showing an example of a conventional anticonductor device having a complementary output circuit. FIG. 4 is a semiconductor electronic circuit diagram showing an improved example of the conventional example. 1...Input terminal, 2, 4...N channel type FE
T, 3, 41... P channel type FET, 5... Output terminal, 10... First switch circuit, 20... Second switch circuit, 30... First switch control circuit, 40... Second switch control Circuit, 21...Vertical PNP transistor, R1 , R3 ...Bias resistance, R2 ...Current limiting resistance, C0 ...Gate-drain capacitance, 101...P-type semiconductor substrate,
102...Isolation area, 103...N
Type base region, 104...P type emitter region, 1
05... P type drain region, 106... N type base contact region, 107... Insulating film, 108...
...Polysilicon gate, 109...Emitter electrode, 110...Gate electrode, 111...Drain
base wiring.
Claims (1)
ネル型ＦＥＴと、該出力端子に第２の電位を継断
すべき縦型ＰＮＰトランジスタと、入力信号の一
方のレベル期間に亘り該Ｎチヤネル型ＦＥＴを導
通させるスイツチ制御回路と、該入力信号の他方
のレベル期間に亘り該縦型ＰＮＰトランジスタを
導通させるスイツチ制御用Ｐチヤネル型ＦＥＴと
を有し、該縦型ＰＮＰトランジスタは該スイツチ
制御用Ｐチヤネル型ＦＥＴの分離領域内に形成さ
れていることを特徴とするコンプリメンタリ出力
回路を有する半導体装置。 (2) 前記スイツチ制御用Ｐチヤネル型ＦＥＴの
ソース領域又はドレイン領域がアイソレイシヨン
領域に形成されていることを特徴とする請求項第
１項に記載のコンプリメンタリ出力回路を有する
半導体装置。[Claims for Utility Model Registration] (1) An N-channel FET whose output terminal is to be connected to and disconnected from a first potential, a vertical PNP transistor whose output terminal is to be connected to and from which a second potential is connected, and an input signal. a switch control circuit that makes the N-channel FET conductive over one level period of the input signal; and a P-channel FET for switch control that makes the vertical PNP transistor conductive over the other level period of the input signal, A semiconductor device having a complementary output circuit, wherein the vertical PNP transistor is formed within an isolation region of the switch control P-channel FET. (2) A semiconductor device having a complementary output circuit according to claim 1, wherein the source region or drain region of the switch control P-channel FET is formed in an isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16603088U JPH0286150U (en) | 1988-12-22 | 1988-12-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16603088U JPH0286150U (en) | 1988-12-22 | 1988-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0286150U true JPH0286150U (en) | 1990-07-09 |
Family
ID=31453053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16603088U Pending JPH0286150U (en) | 1988-12-22 | 1988-12-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0286150U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8878219B2 (en) | 2008-01-11 | 2014-11-04 | Cree, Inc. | Flip-chip phosphor coating method and devices fabricated utilizing method |
| US9024349B2 (en) | 2007-01-22 | 2015-05-05 | Cree, Inc. | Wafer level phosphor coating method and devices fabricated utilizing method |
-
1988
- 1988-12-22 JP JP16603088U patent/JPH0286150U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9024349B2 (en) | 2007-01-22 | 2015-05-05 | Cree, Inc. | Wafer level phosphor coating method and devices fabricated utilizing method |
| US8878219B2 (en) | 2008-01-11 | 2014-11-04 | Cree, Inc. | Flip-chip phosphor coating method and devices fabricated utilizing method |
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