JPH0571145B2 - - Google Patents
Info
- Publication number
- JPH0571145B2 JPH0571145B2 JP60057815A JP5781585A JPH0571145B2 JP H0571145 B2 JPH0571145 B2 JP H0571145B2 JP 60057815 A JP60057815 A JP 60057815A JP 5781585 A JP5781585 A JP 5781585A JP H0571145 B2 JPH0571145 B2 JP H0571145B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- output
- mosfet
- gate electrode
- protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本考案はMOSFETを含む半導体装置に関し、
特に半導体装置の出力端子に印加されるサージ電
圧に対する保護回路に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device including a MOSFET,
In particular, the present invention relates to a protection circuit against surge voltage applied to an output terminal of a semiconductor device.
従来、MOS型半導体装置の出力端子は、出力
端子を駆動する出力段MOSFETが十分大きなチ
ヤネル幅を有するので、外部からのサージ電圧に
対する保護は特に必要とされていなかつた。
Conventionally, the output terminal of a MOS type semiconductor device has not particularly required protection against external surge voltage because the output stage MOSFET that drives the output terminal has a sufficiently large channel width.
しかし、近年の半導体装置の高集積化に伴なつ
て、拡散層の接合が浅くなり、チヤネルが短かく
なつている。そのため、出力段MOSFETの耐圧
が低下し、外部サージ電圧による破壊が起り易く
なつている。
However, as semiconductor devices have become more highly integrated in recent years, junctions in diffusion layers have become shallower and channels have become shorter. As a result, the breakdown voltage of the output stage MOSFET decreases, making it more likely to be destroyed by external surge voltage.
本発明の目的は、外部サージ電圧の対する耐圧
を向上させた出力段MOSFETを含む半導体装置
を提供することにある。 An object of the present invention is to provide a semiconductor device including an output stage MOSFET with improved withstand voltage against external surge voltage.
本発明の半導体装置は、半導体基板の一主面の
連続した活性領域に形成された出力用MOSFET
および保護用MOSFETからなる出力段
MOSFETを含み、前記出力用MOSFETおよび
前記保護用MOSFETの出力端子が共通接続さ
れ、かつ前記保護用MOSFETのゲート電極が前
記保護用MOSFETを非導通状態とする一定電位
に接続されている。
The semiconductor device of the present invention includes an output MOSFET formed in a continuous active region on one main surface of a semiconductor substrate.
and a protection MOSFET.
The output terminals of the output MOSFET and the protection MOSFET are commonly connected, and the gate electrode of the protection MOSFET is connected to a constant potential that makes the protection MOSFET non-conductive.
第１図は本発明の一実施例の半導体基板部分を
示す平面図、第２図は本実施例の等価回路図であ
る。
FIG. 1 is a plan view showing a semiconductor substrate portion of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the embodiment.
はじめに第２図に示すように、出力段
MOSFETは出力用MOSFETQ1、出力用
MOSFETQ2、および保護用MOSFETQ3とから
構成されている。 First, as shown in Figure 2, the output stage
MOSFET is output MOSFETQ 1 , output
It consists of MOSFETQ 2 and protection MOSFETQ 3 .
保護用MOSFETQ3は、ゲート電極が接地電位
に接続されているので、常に非導通状態となつて
いる。 The protection MOSFET Q 3 is always in a non-conducting state because its gate electrode is connected to the ground potential.
出力用MOSFETQ1の入力信号端２３がしきい
値電圧を越えたハイレベルになると、導通状態と
なつて出力信号端２１にロウレベルを出力する。 When the input signal terminal 23 of the output MOSFET Q 1 reaches a high level exceeding the threshold voltage, it becomes conductive and outputs a low level to the output signal terminal 21 .
また、もう１つの出力段MOSFETQ2はゲート
が入力信号端子２２、ドレインが電源VCCソース
が出力用MOSFETQ1のドレインおよび出力端子
２１に接続されている。この出力段MOSFETQ2
は入力信号端子２２がしきい値電圧を越えたハイ
レベルになると、導通状態となつて出力信号端子
２１にハイレベルを出力する。 Another output stage MOSFET Q 2 has a gate connected to the input signal terminal 22 and a drain connected to the power supply V CC source to the drain of the output MOSFET Q 1 and the output terminal 21 . This output stage MOSFETQ 2
When the input signal terminal 22 reaches a high level exceeding the threshold voltage, it becomes conductive and outputs a high level to the output signal terminal 21.
ここで、出力用MOSFETQ1が導通状態から非
導通状態に切り替つて、出力端子２１に接続され
たモーターやリレーなどの誘導性負荷からサージ
電圧が発生すると、出力端子２１に接続された金
属配線１４から出力段MOSFETQ1，Q3にサージ
電圧が印加される。 Here, when the output MOSFET Q 1 switches from a conductive state to a non-conductive state and a surge voltage is generated from an inductive load such as a motor or relay connected to the output terminal 21, the metal wiring 14 connected to the output terminal 21 A surge voltage is applied to the output stage MOSFETs Q1 and Q3 .
このとき出力段MOSFETQ1，Q3のドレインに
加わつた電荷は、出力用MOSFETQ1を駆動する
ゲート電極１２のチヤネル部分を通じてソースに
流入するが、同時に接地電位に固定された保護用
MOSFETQ3のゲート電極１３のチヤネル領域に
も流れるので、出力用MOSFETQ1に流れる電流
量が減少し、より大きなサージ電圧に対して出力
端子２１が耐え得るようになる。 At this time, the charges added to the drains of the output stage MOSFETs Q 1 and Q 3 flow into the source through the channel portion of the gate electrode 12 that drives the output MOSFET Q 1 , but at the same time, the charges added to the drains of the output MOSFETs Q 1 and 3 flow into the source through the channel portion of the gate electrode 12 that drives the output MOSFET Q 1, but at the same time
Since the current also flows to the channel region of the gate electrode 13 of MOSFET Q 3 , the amount of current flowing to the output MOSFET Q 1 is reduced, and the output terminal 21 can withstand even larger surge voltages.
つぎにこの出力段MOSFETの一例として、ス
トライプ型MOSFETについて、第１図を参照し
て説明する。 Next, as an example of this output stage MOSFET, a striped MOSFET will be explained with reference to FIG.
ここで、１１はＮ型ソース・ドレイン拡散層か
らなる連続した活性領域でありゲート電極１２，
１３とともにストライプ型のMOSFETQ1，Q3を
構成している。 Here, 11 is a continuous active region consisting of an N-type source/drain diffusion layer, and a gate electrode 12,
Together with 13, they constitute striped MOSFETs Q 1 and Q 3 .
出力段MOSFETは、４本のストライプ状ゲー
ト電極１２を有する出力用MOSFETQ1および２
本のストライプ状ゲート電極１３を有する保護用
MOSFETQ3から構成されている。保護用
MOSFETQ3の２本のストライプ状ゲート電極１
３はコンタクトホール１７を通してソース電極に
接続された接地電位の金属配線１５に接続されて
いる。また、MOSFETQ1，Q3の出力端子である
４本のストライプ状ドレイン電極は金属配線１４
に共通接続されている。 The output stage MOSFETs are output MOSFETs Q 1 and 2 each having four striped gate electrodes 12.
For protection with striped gate electrodes 13
Consists of MOSFETQ 3 . for protection
Two striped gate electrodes 1 of MOSFETQ 3
3 is connected through a contact hole 17 to a metal wiring 15 at ground potential connected to the source electrode. In addition, the four striped drain electrodes that are the output terminals of MOSFETQ 1 and Q 3 are connected to the metal wiring 14.
are commonly connected.
なお、以上の実施例はMOSFETとしてＮチヤ
ネルMOSFETを含む半導体集積回路について説
明したが、本発明はこれに限定されることなく、
ＰチヤネルMOSFETを含む半導体集積回路や、
さらにバイポーラトランジスタおよびMOSFET
を含むBi−CMOS集積回路にも適用することが
できる。 Although the above embodiments have been described with respect to semiconductor integrated circuits including N-channel MOSFETs as MOSFETs, the present invention is not limited thereto.
Semiconductor integrated circuits including P-channel MOSFETs,
Additionally bipolar transistors and MOSFETs
It can also be applied to Bi-CMOS integrated circuits including.
以上説明したように本発明は、出力段
MOSFETを出力用MOSFETと保護用MOSFET
とに分割して、保護用MOSFETのチヤネルを非
導通状態とする一定電位にゲート電極を接続して
いるので、過渡的に誘導性負荷からサージ電圧が
発生して、出力端子にサージ電圧が印加しても、
保護用MOSFETにバイパスする分だけ、出力用
MOSFETの負荷を軽減できる。また、出力段
MOSFETの入力容量を増やすことなく、出力端
子の保護能力を向上させることができた。
As explained above, the present invention
MOSFET for output MOSFET and protection MOSFET
Since the gate electrode is connected to a constant potential that makes the channel of the protection MOSFET non-conductive, transient voltage surges are generated from the inductive load and surge voltage is applied to the output terminal. Even if
Only the amount bypassed to the protection MOSFET is used for output.
The load on MOSFET can be reduced. Also, the output stage
We were able to improve the protection ability of the output terminal without increasing the input capacitance of the MOSFET.
第１図は本発明の一実施例における半導体基板
を示す平面図、第２図は本発明の一実施例の半導
体装置を示す等価回路図である。
１１……Ｎ型ソース・ドレイン拡散層、１２，
１３……ゲート電極、１４，１５……金属配線、
１６……入力信号線、１７……コンタクトホー
ル、２１……出力端子、２２，２３……入力信号
端子、Q1……出力用MOSFET、Q2……出力段
MOSFET、Q3……保護用MOSFET、VCC……電
源、GND……接地電位。
FIG. 1 is a plan view showing a semiconductor substrate according to an embodiment of the invention, and FIG. 2 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the invention. 11... N-type source/drain diffusion layer, 12,
13... Gate electrode, 14, 15... Metal wiring,
16...Input signal line, 17...Contact hole, 21...Output terminal, 22, 23...Input signal terminal, Q 1 ...Output MOSFET, Q2 ...Output stage
MOSFET, Q 3 ...Protection MOSFET, V CC ...Power supply, GND...Ground potential.
Claims (1)
力端子に接続された逆導電型の第１領域と、前記
第１領域の両側に前記第１領域から離間して設け
られかつ電源端子にそれぞれ接続された前記逆導
電型の第２及び第３領域と、前記第１領域と前記
第２領域との間の前記半導体活性領域部分上にゲ
ート絶縁膜を介して設けられかつ出力すべき信号
の伝達線に接続された第１のゲート電極と、前記
第１領域と前記第３領域との間の前記半導体活性
領域部分上にゲート絶縁膜を介して設けられかつ
前記第１領域と前記第３領域との間を非導通状態
とする一定電位に接続された第２のゲート電極と
を有することを特徴とする半導体装置。1. A first region of an opposite conductivity type provided in a semiconductor active region of one conductivity type and connected to an output terminal, and a first region of an opposite conductivity type provided on both sides of the first region spaced apart from the first region and connected to a power supply terminal, respectively. the semiconductor active region portion between the second and third regions of opposite conductivity types, and the first region and the second region, via a gate insulating film, and transmitting a signal to be output; a first gate electrode connected to a line; and a gate insulating film provided on a portion of the semiconductor active region between the first region and the third region, and a first gate electrode connected to the first region and the third region. a second gate electrode connected to a constant potential to bring non-conductivity between the semiconductor device and the second gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057815A JPS61216477A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057815A JPS61216477A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61216477A JPS61216477A (en) | 1986-09-26 |
| JPH0571145B2 true JPH0571145B2 (en) | 1993-10-06 |
Family
ID=13066412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60057815A Granted JPS61216477A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61216477A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060048A (en) * | 1986-10-22 | 1991-10-22 | Siemens Aktiengesellschaft & Semikron GmbH | Semiconductor component having at least one power mosfet |
| KR940004449B1 (en) * | 1990-03-02 | 1994-05-25 | 가부시키가이샤 도시바 | Semiconductor device |
| JP3237110B2 (en) * | 1998-03-24 | 2001-12-10 | 日本電気株式会社 | Semiconductor device |
| JP2000357695A (en) | 1999-06-16 | 2000-12-26 | Nec Corp | Semiconductor device, semiconductor integrated circuit and method for manufacturing the semiconductor device |
| JP2001144097A (en) | 1999-11-11 | 2001-05-25 | Nec Corp | Semiconductor device |
| US6934136B2 (en) * | 2002-04-24 | 2005-08-23 | Texas Instrument Incorporated | ESD protection of noise decoupling capacitors |
| JP2004304136A (en) * | 2003-04-01 | 2004-10-28 | Oki Electric Ind Co Ltd | Semiconductor device |
| JP6099985B2 (en) * | 2013-01-18 | 2017-03-22 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device |
| JP6099986B2 (en) * | 2013-01-18 | 2017-03-22 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device |
| JP2016021530A (en) * | 2014-07-15 | 2016-02-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1985
- 1985-03-22 JP JP60057815A patent/JPS61216477A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61216477A (en) | 1986-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |