JPH0276044A - Memory constitution setting system - Google Patents

Abstract

PURPOSE:To eliminate a hardware such as a signal line and a switch, etc., for the recognition of memory constitution and to obtain high reliability with the simple constitution by referring a register at the time of a memory access in a memory extending mechanism and judging the propriety of the access. CONSTITUTION:When data are set to a memory card RAS control register 100, under the control of a CPU11, the check of an extension memory area is executed with a prescribed processing routine just after a power source is applied. For this check, an RAS signal is outputted successively from an A-slot and the presence and absence of memory connection is judged by the writing/ reading of the data. According to the result of the judgement, a value is respectively set to bits 7, 5, 4, 3 and 2 of the memory card RAS control register 100. Thus, the hardware such as the signal line or switch, etc., for the recognition of the memory constitution is eliminated and the high reliability can be obtained with the simple constitution.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a personal computer, a personal workstation, etc., which is equipped with a memory expansion structure having a plurality of memory expansion slots. The present invention relates to a memory configuration setting method used in a computer system.

(Prior Art) When a computer system such as a personal computer or a personal workstation is provided with a memory expansion mechanism having a plurality of memory expansion slots, conventionally, each expansion memory card (board) has a means for setting the memory configuration by providing a dip switch and operating the switch for each expanded memory card to be installed to manually set the address and memory size, or
A means for setting the memory configuration by providing each expansion memory card with a unique signal line indicating the mounting state was used.

(Problems to be Solved by the Invention) The memory configuration setting means in the conventional memory expansion mechanism described above has a problem in that the configuration is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory configuration setting method that can eliminate the complexity of hardware for memory configuration settings and realize a simple and highly reliable memory configuration setting mechanism.

(Means and effects for solving the problems) The present invention provides a memory expansion Ii! having a plurality of memory expansion slots! a
m, a means for outputting a RAS signal to each of the slots in a fixed order to recognize the memory mounting state of each slot, and a register for holding the memory mounting state recognized by the same means. This eliminates the need for signal lines, switches, and hardware for memory configuration recognition, and provides a highly reliable memory configuration setting mechanism with a simple configuration. realizable.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart in one embodiment of the present invention, and Section 2 is a system block diagram in the same embodiment.

In Figure 2, 11 is a CP that controls the entire system.
U, 12 is a 32-bit wide CPU bus (031-24,
023-16, 015-8, 07-01, 13 are latch circuits (B-LAT), 14 is a 32-bit wide memory bus (8031-24, HD23-16, 8015-8
.

NO7-0'), 15 is latch time R (C-LAT)
, 16 are 16-bit wide and 7-bit wide address buses (
SA19-0, LA23-17) and a 16-bit wide data bus (8015-8, SO7-0) 16a, 17 and 18 are internal RAMs, respectively.
(DRAM), 19 is cache memory (SRAM)
, 20 is an internal ROM (BIO3-ROM).

The internal RAM 17 is provided with a plurality of memory expansion slots (here, for convenience of explanation, a 3-slot configuration of A slot/B slot/C slot) is provided, and each slot is provided with a memory expansion slot as shown in FIG. An expansion memory card of a predetermined type (memory capacity) is mounted in each slot as shown. That is, here, 2MB is placed in slot A.
(MB), 2MB/4MB/8M in B slot
2MB/4MB memory cards are selectively installed in the B and C slots.

21 is a timing controller (TC) that controls the timing of the entire system including memory control; 22
is a bus controller (BtJ) that performs system bus control.
S-CNT), 23 is a cache memory controller (CMC).

FIG. 3 is a diagram showing the configuration of the memory card RAS control register 100 in the above embodiment. Here, bit 7 is a bit (“0” = RAS Signal output prohibited, “1”
=RASRAS signal output enable bits 5 and 4 control the RAS signal output to the B slot connector (“
O, O” = RAS signal output prohibited, “0, 1” = 4MB
- Enable RAS signal output when accessing 6MB memory, “
1゜0” = RA when accessing 4MB-8MB memory
S signal output enabled, “1.1” = RAS signal output enabled when accessing 4MB-12MB memory), bit 3.2
is the bit that controls the RAS signal output to the C slot connector (“0.0” = RAS signal output, “0.
1” = RAS signal output enabled when accessing 6MB-8MB memory, “1°0” = RAS signal output enabled when accessing memory 8MB-12MB, “1,1” = 12M
(RAS signal output is enabled when accessing B-14MB memory).

Figure 4 shows the expanded memory size and the above memory card RAS$
1 is a diagram showing the relationship with the value to be set in the 1Jll register 100. FIG.

Data setting to the memory card RAS control register 100 is executed according to the flowchart shown in FIG.

At this time, under the control of the CPU 11, the expanded memory area is checked in a predetermined processing routine immediately after power is turned on. In this check, according to the flow shown in FIG. 1, the RAS signal is output in order from the A slot to determine whether memory is connected by writing/reading data, and according to the result of the determination, the memory card RAS control register 100 is
The above-mentioned values are set in bits 7°5.4 and 3.2, respectively.

The relationship between the expanded memory size and the set value of the memory card RAS control register 100 at this time is shown in FIG.

[Effects of the Invention] As detailed above, according to the memory configuration setting method of the present invention, in a computer system equipped with a memory expansion mechanism having a plurality of memory expansion slots, a certain number of It has a means for outputting RAS signals in the order of , and for recognizing the mounting state of memory for each slot, and a register for holding the memory mounting state recognized by the same means, and a register for holding the memory mounting state recognized by the same means. By using a configuration that refers to the above register to determine whether or not it can be accessed, hardware such as signal lines and switches for memory configuration recognition is unnecessary, allowing for highly reliable memory configuration settings with a simple configuration. realizable.

[Brief explanation of the drawing]

Fig. 1 is a flowchart in one embodiment of the present invention, Fig. 2 is a system block diagram in the same embodiment, and Fig. 3 is a memory card RAS control register 1 in the above embodiment.
4 is a diagram showing the relationship between the expanded memory size and the set value of the memory card RAS control register 100. 11...CPU, 12...CPU bus (1) 31-
24. [)23-16.015-8, O7-0
), 13... latch circuit (B-LAT), 14.
...Memory bus (8031-24, 8023-1f3.
8015-8, 807-0), 15-・Latch circuit (C-LAT), 16... System bus (SA19
-0. L^23-17.8015-8, SO7-0
), 17.18... Internal RAM (DRAM),
19... Cache memory (SRAM), 20
---Internal ROM (BI O3-ROM), 21
... timing controller (TC), 22 ... bus controller (BUS-CNT), 23 ... cache memory controller (CMC), 100 ... memory card RAS control register.

Claims (1)

[Claims] In a computer system equipped with a memory expansion mechanism having a plurality of memory expansion slots, means for outputting a RAS signal to each slot in a fixed order and recognizing the mounting state of memory in each slot. , and a register for holding the memory implementation state recognized by the same means, and when the memory expansion mechanism accesses the memory, the memory configuration setting method is characterized in that the memory expansion mechanism refers to the register to determine whether access is possible.