JPS6336450A - Lsi for cache - Google Patents

Abstract

PURPOSE:To constitute the circuit of an optimum control at an LSI external part and to improve the flexibility of a function when a terminal from a comparator is used by providing a comparator and a control circuit in which the coincidence of an address inputted from the external part and the address stored into a memory is obtained. CONSTITUTION:An address 100 sent from a CPU side compares all addresses in plural address memories 10 to store the main memory address of cache data with a comparator 11. There are the first output terminal 13 which receives the checking of the coincidence at the comparator 11, is controlled to output logical conditions and a timing and outputs a coincident signal to the external part, and the second output terminal 14 to output the coincident result only from the comparator 11 to the external part, and both can be used in accordance with the response speed request of the cache.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a cache LSIK.

[Conventional technology]

Conventionally, cache LSIs have integrated a cache control circuit consisting of a large number of memory chips and small to medium-sized logic chips into a single chip.

In order to significantly reduce the IC mounting area, lower the cost of the cache function circuit, and increase the speed, the address of the data stored in the cache part and the address where the cache is accessed from the CPU side have been changed. The time when the CPU side is notified of the result of the comparison and whether it matches or does not match
Met.

[Problem that the invention seeks to solve]

Although the above-mentioned conventional cache LSI incorporates many cache functions, it also has the drawback of lacking functional flexibility. Particularly important was the flexibility of the match detection function for address comparison, which takes into account the performance of Cache. With the remarkable increase in speed of recent microprocessors, an increase in cache performance has been inevitable. Conventional large-scale LSI
is often realized with a CMO3, but the circuit that controls the address comparison match signal f according to the logical conditions and output timing to be notified to the CPU side is implemented in the LSI for the purpose of reducing the IC mounting area. was realized. However, if the CMO8 circuit cannot satisfy the speed required by the CPU, it is possible to use a high-speed TTL circuit outside the LSI and devise the logic of the control circuit to increase the speed. The cache LSI had the disadvantage that the control circuit was self-selected, leaving no room for choice.

[Failure to solve the problem]

The cache LSI of the present invention includes a memory that stores a plurality of addresses, a comparison circuit that checks whether an address input from the outside matches an address stored in the memory, and
A terminal for outputting a match signal generated from the comparison circuit to the outside; and a control circuit that receives the match signal and controls output of the match signal to the outside based on logic conditions, output typing, etc.

and a terminal for outputting a coincidence signal outputted from the control circuit to the outside.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

Only the parts related to the present invention are shown. 1 is a cache LSI. 1 and 10 are multiple fixed address memories, which store the memory addresses of data stored in the cache. The memory that stores cache data is in the cache LSII. Or it is outside but not shown in Figure 1.

11 is an external address signal group 100 and an address memory 10
This circuit inputs and compares the storage address signal group 200 from . Reference numeral 12 denotes a control circuit that receives the address match signal 300 output from the circuit 11 and controls the logic conditions and timing for outputting it to the outside. The first output terminal 13 is for outputting the output signal 400 of the output control circuit 12 to the outside. The second output terminal 14 is for outputting the output signal 300 of the comparator circuit 11 to the outside.

Next, the operation will be explained in detail. The cache is a memory that stores part of the data in the main memory and responds quickly to accesses from the CPU side. The response is to determine whether or not the address from the CPU side is stored in the cache, and notify the CPU side of this, and then send the data corresponding to that address from the cache to the CPU side. This completes the process. In the present invention, the address 100 sent from the CPU side is compared with all addresses in a plurality of address memories 10 storing in-memory addresses of gear data in a comparison circuit 11. Here, there is no particular problem with the main memory address storage configuration and the reading method to the comparison circuit 11 (C). After the comparison circuit 11 checks for a match, the match signal is output externally under the control of the logic conditions and timing. A first output terminal 13 that outputs only the matching result from the comparison circuit 11 to the outside.
4, and either one can be used depending on the cache response speed requirements.

〔Effect of the invention〕

As explained above, the present invention uses a match signal from a comparator circuit for the cache according to the cache access time requirements of the accessing CPU, and
If the speed requirements are sufficiently satisfied, the coincidence signal output from the control circuit can be used, and if the terminal from the comparison circuit is used, an optimal control circuit can be configured outside the LSI, and the control circuit can The use of the output signal terminal has the effect of reducing the external circuitry.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention. 1... LSI for cache, l O... Address memory. 11... Comparison circuit, 12... Output control circuit, 13.
...First output terminal, 14...Second output terminal, 10
0... External address signal group, 200... Address memo IJ storage signal group, 300... Match signal, 400...
...Controlled coincidence signal.

Claims (1)

[Claims] 1) A memory that stores a plurality of addresses, a comparison circuit that checks the match between an address input from the outside and an address stored in the memory, and a terminal that outputs a match signal generated from the comparison circuit to the outside. , comprising a control circuit that receives the coincidence signal and controls output of the coincidence signal to the outside according to logic conditions, output timing, etc., and a terminal that outputs the coincidence signal output from the control circuit to the outside. LSI for cache.