JPH02296336A - Manufacture of semiconductor circuit bump - Google Patents
Manufacture of semiconductor circuit bumpInfo
- Publication number
- JPH02296336A JPH02296336A JP11690989A JP11690989A JPH02296336A JP H02296336 A JPH02296336 A JP H02296336A JP 11690989 A JP11690989 A JP 11690989A JP 11690989 A JP11690989 A JP 11690989A JP H02296336 A JPH02296336 A JP H02296336A
- Authority
- JP
- Japan
- Prior art keywords
- nickel
- palladium
- solder
- metal
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 11
- 239000000956 alloy Substances 0.000 claims abstract description 11
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000007772 electroless plating Methods 0.000 claims abstract description 5
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000003475 lamination Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 15
- 150000002739 metals Chemical class 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical group Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 abstract 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 abstract 1
- ACVYVLVWPXVTIT-UHFFFAOYSA-M phosphinate Chemical compound [O-][PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-M 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 1
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
- 229910010277 boron hydride Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- ACVYVLVWPXVTIT-UHFFFAOYSA-N phosphinic acid Chemical compound O[PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- -1 solder Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Other Surface Treatments For Metallic Materials (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、半導体集積回路の外部端子である半導体回路
バンプの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing semiconductor circuit bumps, which are external terminals of semiconductor integrated circuits.
［従来の技術］
半導体集積回路の製造において、回路のポンディングパ
ッドに電気的な接続を与えるため各種技術が従来開発さ
れた。例えば、フリップチップボンディングやＴＡＢな
どのようにポンディングパッド上に突起した金属バンプ
を形成し、直接回路パターンやパターン化されたテープ
キャリアーへ熱圧着する方法や、回路チップにバンプを
加工したリードフレームをボンディングする方法がある
。BACKGROUND OF THE INVENTION In the manufacture of semiconductor integrated circuits, various techniques have been developed in the past for providing electrical connections to bonding pads of circuits. For example, methods such as flip-chip bonding and TAB, in which protruding metal bumps are formed on a bonding pad and thermocompression bonded directly to a circuit pattern or patterned tape carrier, and lead frames in which bumps are processed on circuit chips. There is a way to bond.
また従来はんだなど低融点金属を使った金属バンプは、
金属拡散防止金属と金をスパッタリング法などにより成
膜して導電化処理を行ない、次にポンディングパッド予
定領域部分なパターン化した後、はんだなどの電解メッ
キ浴によりはんだなどを厚付けする方法が知られている
。In addition, conventional metal bumps using low melting point metals such as solder,
A method is to form a film of metal diffusion prevention metal and gold using a sputtering method, conductive treatment, pattern the area where the bonding pad is to be formed, and then apply a thick layer of solder, etc., using an electrolytic plating bath. Are known.
しかしこのような従来の技術では、半導体集積回路の表
面すべてを導電化処理する成膜プロセスが必要であり、
さらにポンディングパッド予定部域をパターン化する必
要があるため、半導体集積回路製造プロセスが長くなり
、製造コストが低減できないという課題がある。そこで
プロセスを簡素化するため、選択的なメタライズができ
る無電解ニッケル系メッキ法とはんだ超音波浸漬法を併
用したはんだバンプの製造方法が知られている。However, such conventional technology requires a film formation process that makes the entire surface of the semiconductor integrated circuit conductive.
Furthermore, since it is necessary to pattern the area where the bonding pad is to be planned, the semiconductor integrated circuit manufacturing process becomes long, and there is a problem that manufacturing costs cannot be reduced. Therefore, in order to simplify the process, a method for manufacturing solder bumps is known that uses a combination of an electroless nickel plating method that allows selective metallization and a solder ultrasonic immersion method.
（発明が解決しようとする課題１
しかしながらニッケル合金の表面酸化膜を超音波により
破壊しながらはんだを積層する従来の技術では、その酸
化膜が比較的強固なため、はんだの積層旨さがばらつき
、フリップデツプボンデインクができないという課題が
ある。(Problem to be Solved by the Invention 1) However, with the conventional technique of laminating solder while destroying the surface oxide film of a nickel alloy using ultrasonic waves, the oxide film is relatively strong, so the solder lamination quality varies. There is a problem that flip-deep bonding is not possible.
本発明は以上の課題を解決するものでその目的は、はん
だの積層高さを均一にしてボンディング不良を発生させ
ない半導体回路バンプの製造方法を提供することである
。The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method for manufacturing a semiconductor circuit bump by making the stacked height of solder uniform and preventing bonding defects from occurring.
〔課題を解決するだめの手段１
本発明の半導体回路バンプの製造方法は、半導体集積回
路の配線金属上へ選択的にパラジウム、ニッケル系合金
を順に積層した外部端子において、その上へ金と融点が
３５０℃以下の金属を積層することを特徴とする。[Means for Solving the Problems 1] The method for manufacturing a semiconductor circuit bump of the present invention comprises forming an external terminal in which palladium and a nickel-based alloy are sequentially laminated selectively on the wiring metal of a semiconductor integrated circuit, and gold and a melting point layer are added thereon. It is characterized by laminating metals whose temperature is 350°C or less.
またその製造方法は、ニッケル系合金を無電解ニッケル
・リンメッキ液または無電解ニッケルほう素メッキ液に
より成膜することを特徴とする。Further, the manufacturing method is characterized in that a nickel-based alloy is formed into a film using an electroless nickel-phosphorus plating solution or an electroless nickel-boron plating solution.
またその製造方法は、金を無電解メッキ法により成膜す
ることを特徴とする。Further, the manufacturing method is characterized in that a gold film is formed by electroless plating.
またその製造方法は、融点が３５０℃以下の金属を溶融
浴に浸漬することにより積層することを特徴とする。Further, the manufacturing method is characterized in that metals having a melting point of 350° C. or lower are laminated by immersing them in a molten bath.
またその製造方法は、融点が３５０℃以下の金属を溶融
浴中で超音波を照射することにより積層することを特徴
とする。Further, the manufacturing method is characterized in that metals having a melting point of 350° C. or lower are laminated by irradiating ultrasonic waves in a molten bath.
本発明で用いる金は、酸化膜を形成しにくいｔ：め、？
８融浴から均一に融点が３５０℃Ｕ、下の金属を積層で
きる動きがある。Gold used in the present invention is difficult to form an oxide film.
8. The melting point is 350℃U from the melting bath, and there is a movement that allows the underlying metal to be laminated.
また金の上に積層する金属の融点は３５０℃以下が望ま
しい。３５０℃よりも高温の金属を使うと、ハンプを形
成するための溶融浴浸漬時に半導体自身が破壊されると
いう問題がある。Further, the melting point of the metal layered on the gold is preferably 350° C. or lower. If a metal with a temperature higher than 350° C. is used, there is a problem that the semiconductor itself is destroyed during immersion in a molten bath to form the hump.
［実 施 例１ 次に、本発明の実施例を図面にもとすいて説明する。[Implementation Example 1] Next, embodiments of the present invention will be described with reference to the drawings.
（実施例１）
第１図の（ａ）〜（ｃ）は、本実施例の工程順断面図で
ある。(Example 1) FIGS. 1(a) to 1(c) are sectional views in the order of steps of this example.
第１図の（ａ）に示すように、ポンディングパッドの形
成まで終了した半導体基板（１）を塩化パラジウムが主
成分の処理液に浸漬することによりポンディングパッド
であるアルミニウム層（２）の上へパラジウム層（４）
を成膜する。次に第１図（１〕）に示すように、ｒａ酸
ニッケルと次亜リン酸を使った無電解メッキ浴でニッケ
ル・リン層（５）を２μｍメッキする。次に第１図（ｂ
）に示すように、市販の無電解金メッキ液により金層（
６）をＱ、１．ｇｍメッキする。最後に第１図（Ｃ）に
示すように、３２０℃に加熱されたはんだン谷（′錫
１ｗｔ％、６’９：９７．５ｗｔ％、銀 １．．５ｗｔ
％）、２９０℃に加熱された（まんだン谷（６８：１０
ｗｔ％、＆９ ： ８８ ｗ ｔ％、１艮２ｗｔ％）、
２２０℃（こ加熱されたけんだ浴（錫 ６３ｗｔ％、鉛
３７ｗｔ％）の順に浸してはんだ層（７）を積層して
バンプを製造する。As shown in FIG. 1(a), the aluminum layer (2), which is the bonding pad, is formed by immersing the semiconductor substrate (1) on which the bonding pad has been formed into a treatment solution containing palladium chloride as the main component. Palladium layer on top (4)
Deposit a film. Next, as shown in FIG. 1 (1), a nickel-phosphorus layer (5) of 2 μm thickness is plated in an electroless plating bath using nickel RA and hypophosphorous acid. Next, Figure 1 (b
), the gold layer (
6) as Q, 1. GM plated. Finally, as shown in Figure 1 (C), the solder valley ('tin) heated to 320°C is
1wt%, 6'9:97.5wt%, silver 1. ．． 5wt
%), heated to 290°C (Mandan Valley (68:10
wt%, &9: 88 wt%, 1 wt%, 2 wt%),
A solder layer (7) is laminated by immersion in a heated solder bath (tin: 63 wt%, lead: 37 wt%) at 220° C. to produce a bump.
（実施例２）
実施例１のニッケル・リン層（５）をニッケル塩と水素
化ほう素層を使った無電解メッキ浴によりニッケル・ほ
う素にかえた以外、実施例１と同様の方法によりバンプ
を製造する。(Example 2) The same method as in Example 1 was used except that the nickel/phosphorus layer (5) in Example 1 was changed to nickel/boron using an electroless plating bath using a nickel salt and a boron hydride layer. Manufacture bumps.
（比較例）
第２図の（ａ）〜（ｂ）は、従来の技ｆ！ｉの工程順断
面図である。(Comparative Example) (a) to (b) in FIG. 2 are the conventional technique f! It is a sectional view of process order of i.
第２図（ａ）に示すように、実施例１と同様にニッケル
・リン層（５）まで成膜する。最後に第２図（ｂ）に示
すように、実施例１と同様の方法にＪ：りはんだ層（７
）を積層してバンプな製造する。As shown in FIG. 2(a), films are formed up to the nickel-phosphorus layer (5) in the same manner as in Example 1. Finally, as shown in FIG. 2(b), J: resolder layer (7
) to produce bumps.
以上、実施例１．２と比較例の方法により製造したハン
グ（−１き半導体を金メッキしたリードバタンへ熱圧着
によりボンディングし、密着強度、接触抵抗、耐環境性
などの品質を調べた。その結果、本実施例のバンプは比
較例に比べてポンディング品質が良好である。As described above, hang (-1) semiconductors manufactured by the methods of Example 1.2 and Comparative Example were bonded to gold-plated lead batons by thermocompression bonding, and the qualities such as adhesion strength, contact resistance, and environmental resistance were examined. As a result, the bump of this example has better bonding quality than that of the comparative example.
尚、ニッケル・リン層（５）と金層（６）の膜厚は、本
実施例に示した値から外れても効果は変わりがない。Note that even if the thicknesses of the nickel-phosphorous layer (5) and the gold layer (6) deviate from the values shown in this example, the effect remains the same.
［発明の効果１
以」二連へたように本発明の半導体回路バンプの製造方
法は、はんだなどの積層高さを均一にすることによって
、ポンディング品質を良好にする効果が有る。[Effects of the Invention 1 and Below] As stated above, the method of manufacturing a semiconductor circuit bump of the present invention has the effect of improving the bonding quality by making the stacking height of the solder and the like uniform.
シリコン半導体基板 ２・・・アルミニウム層 ３ ・・二酸化けい素層 ４ ・・パラジウム層 ５・ ・ニッケル・リン層 ６・ ・金層 ７・・・はんだ層 以 」二 出願人 セイコーエプソン株式会社silicon semiconductor substrate 2...Aluminum layer 3...Silicon dioxide layer 4...Palladium layer 5. Nickel/phosphorous layer 6. Gold layer 7...Solder layer 2. Applicant: Seiko Epson Corporation
Claims (6)
ム、ニッケル系合金を順に積層した外部端子において、
その上へ金と融点が３５０℃以下の金属を積層すること
を特徴とする半導体回路バンプの製造方法。(1) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
A method for manufacturing a semiconductor circuit bump, which comprises laminating gold and a metal having a melting point of 350° C. or lower thereon.
ム、ニッケル系合金を順に積層した外部端子において、
ニッケル系合金を無電解ニッケル・リンメッキ液により
成膜することを特徴とする請求項１記載の半導体回路バ
ンプの製造方法。(2) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
2. The method of manufacturing a semiconductor circuit bump according to claim 1, wherein the nickel-based alloy is formed into a film using an electroless nickel-phosphorus plating solution.
ム、ニッケル系合金を順に積層した外部端子において、
ニッケル系合金を無電解ニッケル・ほう素メッキ液によ
り成膜することを特徴とする請求項１記載の半導体回路
バンプの製造方法。(3) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
2. The method of manufacturing a semiconductor circuit bump according to claim 1, wherein the nickel-based alloy is formed into a film using an electroless nickel/boron plating solution.
ム、ニッケル系合金を順に積層した外部端子において、
金を無電解メッキ法により成膜することを特徴とする請
求項１または請求項２または請求項３記載の半導体回路
バンプの製造方法。(4) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
4. The method of manufacturing a semiconductor circuit bump according to claim 1, wherein the gold film is formed by electroless plating.
ム、ニッケル系合金を順に積層した外部端子において、
融点が３５０℃以下の金属の溶融浴に浸付することによ
り積層することを特徴とする請求項１または請求項２ま
たは請求項３または請求項４記載の半導体回路バンプの
製造方法。(5) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
5. The method of manufacturing a semiconductor circuit bump according to claim 1, wherein the lamination is performed by immersing the bumps in a molten bath of a metal having a melting point of 350° C. or less.
ム、ニッケル系合金を順に積層した外部端子において、
少なくとも３回以上融点が３５０℃以下の金属を、融点
の高い金属から順に重ねて積層することを特徴とする請
求項１または請求項２または請求項３または請求項４ま
たは請求項５記載の半導体回路バンプの製造方法。(6) In an external terminal in which palladium and nickel-based alloys are selectively laminated in order on the wiring metal of a semiconductor integrated circuit,
The semiconductor according to Claim 1, Claim 2, Claim 3, Claim 4, or Claim 5, characterized in that the metals having a melting point of 350° C. or less are stacked at least three times in order from the metal with the highest melting point. Method of manufacturing circuit bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11690989A JPH02296336A (en) | 1989-05-10 | 1989-05-10 | Manufacture of semiconductor circuit bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11690989A JPH02296336A (en) | 1989-05-10 | 1989-05-10 | Manufacture of semiconductor circuit bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02296336A true JPH02296336A (en) | 1990-12-06 |
Family
ID=14698648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11690989A Pending JPH02296336A (en) | 1989-05-10 | 1989-05-10 | Manufacture of semiconductor circuit bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02296336A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455195A (en) * | 1994-05-06 | 1995-10-03 | Texas Instruments Incorporated | Method for obtaining metallurgical stability in integrated circuit conductive bonds |
| EP0869548A1 (en) * | 1997-03-31 | 1998-10-07 | Nec Corporation | Resin-sealed wireless bonded semiconductor device |
| EP1006576A1 (en) * | 1998-11-30 | 2000-06-07 | Sharp Kabushiki Kaisha | Semiconductor device |
| US7732935B2 (en) | 2004-08-12 | 2010-06-08 | Ricoh Company, Ltd. | Wiring board, electronic circuit board, electronic apparatus and manufacturing method of electronic circuit board |
-
1989
- 1989-05-10 JP JP11690989A patent/JPH02296336A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455195A (en) * | 1994-05-06 | 1995-10-03 | Texas Instruments Incorporated | Method for obtaining metallurgical stability in integrated circuit conductive bonds |
| EP0869548A1 (en) * | 1997-03-31 | 1998-10-07 | Nec Corporation | Resin-sealed wireless bonded semiconductor device |
| EP1006576A1 (en) * | 1998-11-30 | 2000-06-07 | Sharp Kabushiki Kaisha | Semiconductor device |
| US7732935B2 (en) | 2004-08-12 | 2010-06-08 | Ricoh Company, Ltd. | Wiring board, electronic circuit board, electronic apparatus and manufacturing method of electronic circuit board |
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