JP3846948B2 - Bare chip mounting parts - Google Patents
Bare chip mounting parts Download PDFInfo
- Publication number
- JP3846948B2 JP3846948B2 JP31030596A JP31030596A JP3846948B2 JP 3846948 B2 JP3846948 B2 JP 3846948B2 JP 31030596 A JP31030596 A JP 31030596A JP 31030596 A JP31030596 A JP 31030596A JP 3846948 B2 JP3846948 B2 JP 3846948B2
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- JP
- Japan
- Prior art keywords
- bare chip
- electroless plating
- plating film
- alloy
- electroless
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000000758 substrate Substances 0.000 claims description 34
- 238000007772 electroless plating Methods 0.000 claims description 29
- 239000011347 resin Substances 0.000 claims description 19
- 229920005989 resin Polymers 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052718 tin Inorganic materials 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- 229910001020 Au alloy Inorganic materials 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 4
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
- 239000003353 gold alloy Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- 229910000570 Cupronickel Inorganic materials 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- AFVFQIVMOAPDHO-UHFFFAOYSA-N Methanesulfonic acid Chemical compound CS(O)(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- UMGDCJDMYOKAJW-UHFFFAOYSA-N thiourea Chemical compound NC(N)=S UMGDCJDMYOKAJW-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- TXUICONDJPYNPY-UHFFFAOYSA-N (1,10,13-trimethyl-3-oxo-4,5,6,7,8,9,11,12,14,15,16,17-dodecahydrocyclopenta[a]phenanthren-17-yl) heptanoate Chemical compound C1CC2CC(=O)C=C(C)C2(C)C2C1C1CCC(OC(=O)CCCCCC)C1(C)CC2 TXUICONDJPYNPY-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910021626 Tin(II) chloride Inorganic materials 0.000 description 1
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229940098779 methanesulfonic acid Drugs 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 235000011150 stannous chloride Nutrition 0.000 description 1
- 239000001119 stannous chloride Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【0001】
【産業上の利用分野】
この発明はベアチップ搭載用の樹脂基板及びそれを用いたベアチップ実装部品関する。
【0002】
【従来の技術】
最近、限られた面積の基板上に多くの機能を詰め込みたいという要求に応じるため、半導体チップをパッケージに含まずに、そのまま基板に搭載する「フリップチップ」と称されたベアチップが知られている。このベアチップのパッド(電極)には、リードの代わりに、金属製のバンプ(突起)が形成され、そのバンプを基板の表面に形成したパッド(電極)へ加熱処理により接合している。
【0003】
基板の表面にパッドを形成する方法としては、印刷法、蒸着法、めっき法などがあるが、近年の配線パターンの微細化に伴い、印刷法では微細なパターン精度が得られず、また蒸着法ではコストがかかるため、現在ではめっき法が用いられている。しかも、導通の引回しが不要な無電解めっき法が主流となっている。そして、従来の無電解めっきとしては、ベアチップ側のパンプとの接続強度を得るために、自己触媒型のハンダめっきが一般的に用いられている。
【0004】
【発明が解決しようとする課題】
しかしながら、このような自己触媒型の無電解ハンダめっき法にしても、基板を樹脂で形成する場合は適用が困難である。すなわち、樹脂製の基板上にベアチップを搭載する場合は、樹脂製の基板の方が、半導体製のベアチップよりも、熱膨張率が大きく(約5倍)、ベアチップと基板の間で大きな応力が生じることとなるため、この応力を緩和すべく、ベアチップのバンプや基板のパッドを厚く形成して、ベアチップと基板との距離を十分に確保する必要があるが、従来のような自己触媒型のハンダめっきでは、微細なパターン精度を維持したたま、厚く形成することが困難である。ベアチップ側のバンプは電解めっきが可能なため、十分に厚く形成することが可能であるが、基板側のパッドを形成するための無電解めっきは、薄く形成する場合には微細パターンを精度良く維持できるものの、厚く形成する場合は、微細パターンの精度がどうしても低下してしまう。
【0005】
この発明はこのような従来の技術に着目したもので、応力を確実に緩和できるベアチップ搭載用の樹脂基板及びそれを用いたベアチップ実装部品を提供するものである。
【0006】
【課題を解決するための手段】
この発明の樹脂基板は、表面に、銅、銅合金、ニッケル、ニッケル合金の群から選ばれた自己触媒型無電解めっき液にて20μm以上の第1無電解めっき膜を形成し、この第1無電解めっき膜の上に、金、金合金、銀、銀合金、錫、錫合金の群から選ばれた置換型無電解めっき液により第2無電解めっき膜を形成したものである。
【0007】
ここで「基板」とは、一般的な意味での基板の他に、パッケージ等、ベアチップが搭載され得る全ての物を総称する意味である。
【0008】
銅、銅合金、ニッケル、ニッケル合金の群から選ばれた自己触媒型無電解めっき液を用いれば、基板が樹脂製であっても、「パッド」としての微細パターンを維持したまま、20μm以上の厚い第1無電解めっき膜を形成することができる。これは、銅やニッケル等の無電解めっきにおける触媒活性が、従来の無電解ハンダめっきよりも高いためである。
【0009】
また、第1無電解めっき膜の上に、金、金合金、銀、銀合金、錫、錫合金の群から選ばれた置換型の無電解めっき液による第2無電解めっき膜が形成されているため、前記第1無電解めっき膜(パッド)と、ベアチップのバンプとの必要な接合強度を得ることができる。
【0010】
尚、第2無電解めっき膜の厚さは、ベアチップのバンプと、樹脂基板の第1無電解めっき膜とを確実に接合できる程度であれば良く、例えば0.1〜20μm程度の厚さで良い。
【0011】
第1無電解めっき膜を形成する「銅合金」の相手金属としてはニッケルが好適で、「ニッケル合金」の相手金属としては錫が好適である。
【0012】
更に、第2無電解めっき膜を形成するための「金合金」の相手金属としては錫が好適で、「銀合金」の相手金属としてはビスマスが好適で、「錫合金」の相手金属としてはインジウムが好適である。
【0013】
ベアチップのバンプは、金、銀、銅、白金、パラジウム、錫、インジウム、及びそれらの各合金の群から選ばれた一種の電解めっき液による電解めっきにより形成される。バンプを形成するための電解めっき膜は20μm以上の厚さで形成される。電解めっきの場合は、基板側の無電解めっきに比べて、厚く形成することが容易である。バンプを形成する金属として、金、銀、銅、白金、パラジウム、錫、インジウム、及びそれらの各合金を用いたのは、電気的な特性に優れ、接合性も良いからである。
【0014】
このようにして形成されたベアチップのバンプは、前記樹脂基板の第2無電解めっき膜上に載せられ、加熱処理により接合される。このようにしてベアチップが搭載された実装部品は、ベアチップと樹脂基板との間に十分な距離が確保されるため、樹脂基板とベアチップとの間に熱膨張率の差による応力が発生しても、その応力を確実に緩和することができる。
【0015】
【実施例】
材質がエポキシである樹脂製の基板に、自己触媒型の無電解銅めっき液を用いて、該基板の表面に「パッド」としての無電解銅めっき膜(第1無電解めっき膜)を形成した。
【0016】
使用した無電解銅めっき液は、荏原ユージライト社のインタープレートプロセスにおけるPB−570(商品名)で、この無電解銅めっき液を利用して、レジストによりパターンニングされた基板上に微細パターンの無電解銅めっき膜を形成した。
【0017】
無電解銅めっき膜の厚さは30μmで、「パッド」としての微細パターンの精度も保たれていた。
【0018】
そして、この無電解銅めっきされた樹脂基板を置換型の錫めっきに浸漬して、無電解銅めっき膜の微細パターン上にのみ、「接合層」としての無電解錫めっき膜(第2無電解めっき膜)を形成した。得られた無電解錫めっき層の厚さは12μmであった。
【0019】
また、この無電錫めっき液は、以下のような組成及び条件である。
・メタンスルホン酸 …………………………… 100ml/l
・塩化第一錫 …………………………………… 45g/l
・チオ尿素 ……………………………………… 100g/l
・浴温 …………………………………………… 70℃
・時間 …………………………………………… 3時間
【0020】
次に、「ベアチップ」としてのフリップチップの金属製のパッド上に、金の電解めっき液を利用して、「バンプ」としての電解金めっき膜を形成した。得られた、電解金めっき膜の厚さは20μmであった。
【0021】
また、電解金めっき液は、日本エレクトロプレイテイング・エンジニヤース社製のミクロファブAu100(商品名)を用いた。
【0022】
バンプを形成したフリップチップを、前記の樹脂基板上に搭載して、該フリップチップのバンプと、前記基板の無電解錫めっき膜とを、加熱処理により接合した。加熱は日本アルファメタルズ社製のフラックスR5003(商品名)を使用して、大気中において、加熱温度230℃、加熱時間3分で行った。
【0023】
このようにして接合されたフリップチップと基板との距離は40μmもあり、両者間の熱膨張率の差により生じる応力を確実に緩和することができる。
【0024】
【発明の効果】
この発明によれば、ベアチップと樹脂基板との間に十分な距離を確保することができ、樹脂基板とベアチップとの間に熱膨張率の差による応力が発生しても、その応力を確実に緩和することができる。[0001]
[Industrial application fields]
The present invention relates to a bare chip mounting resin substrate and a bare chip mounting component using the same.
[0002]
[Prior art]
Recently, a bare chip called “flip chip” is known in which a semiconductor chip is not included in a package and is mounted on a substrate as it is in order to meet a demand to pack many functions on a substrate having a limited area. . Metal pads (projections) are formed on the bare chip pads (electrodes) instead of the leads, and the bumps are bonded to the pads (electrodes) formed on the surface of the substrate by heat treatment.
[0003]
There are printing methods, vapor deposition methods, plating methods, etc. as methods for forming pads on the surface of the substrate. However, with the recent miniaturization of wiring patterns, fine pattern accuracy cannot be obtained with printing methods, and vapor deposition methods are also available. However, because of the cost, the plating method is currently used. In addition, electroless plating methods that do not require conduction are the mainstream. As conventional electroless plating, autocatalytic solder plating is generally used in order to obtain connection strength with the bump on the bare chip side.
[0004]
[Problems to be solved by the invention]
However, even such an autocatalytic electroless solder plating method is difficult to apply when the substrate is formed of a resin. That is, when a bare chip is mounted on a resin substrate, the resin substrate has a larger coefficient of thermal expansion (about 5 times) than the semiconductor bare chip, and a large stress is generated between the bare chip and the substrate. Therefore, in order to relieve this stress, it is necessary to form a thick bump on the bare chip and a pad on the substrate to ensure a sufficient distance between the bare chip and the substrate. In solder plating, it is difficult to form a thick film while maintaining fine pattern accuracy. The bumps on the bare chip side can be electroplated, so it can be formed thick enough, but the electroless plating to form the pads on the substrate side maintains a fine pattern with high precision when forming thinly. Although it can be formed, when it is formed thick, the precision of the fine pattern is inevitably lowered.
[0005]
The present invention pays attention to such a conventional technique, and provides a resin substrate for mounting a bare chip that can surely relieve stress and a bare chip mounting component using the same.
[0006]
[Means for Solving the Problems]
In the resin substrate of the present invention, a first electroless plating film of 20 μm or more is formed on the surface with an autocatalytic electroless plating solution selected from the group consisting of copper, copper alloy, nickel and nickel alloy. A second electroless plating film is formed on the electroless plating film with a substitutional electroless plating solution selected from the group consisting of gold, gold alloy, silver, silver alloy, tin, and tin alloy.
[0007]
Here, the “substrate” is a generic term for all things on which a bare chip can be mounted, such as a package, in addition to a substrate in a general sense.
[0008]
If a self-catalyzed electroless plating solution selected from the group of copper, copper alloy, nickel, nickel alloy is used, even if the substrate is made of resin, the fine pattern as a “pad” is maintained while maintaining a fine pattern of 20 μm or more. A thick first electroless plating film can be formed. This is because the catalytic activity in electroless plating such as copper and nickel is higher than that of conventional electroless solder plating.
[0009]
Further, a second electroless plating film is formed on the first electroless plating film with a substitutional electroless plating solution selected from the group of gold, gold alloy, silver, silver alloy, tin, and tin alloy. Therefore, the required bonding strength between the first electroless plating film (pad) and the bare chip bump can be obtained.
[0010]
The thickness of the second electroless plating film may be a thickness that can reliably bond the bump of the bare chip and the first electroless plating film of the resin substrate, for example, a thickness of about 0.1 to 20 μm. good.
[0011]
Nickel is preferable as the counter metal of the “copper alloy” forming the first electroless plating film, and tin is preferable as the counter metal of the “nickel alloy”.
[0012]
Furthermore, tin is preferred as the partner metal of the “gold alloy” for forming the second electroless plating film, bismuth is preferred as the partner metal of the “silver alloy”, and the partner metal of the “tin alloy” is Indium is preferred.
[0013]
The bump of the bare chip is formed by electrolytic plating with a kind of electrolytic plating solution selected from the group of gold, silver, copper, platinum, palladium, tin, indium, and their respective alloys. The electrolytic plating film for forming the bump is formed with a thickness of 20 μm or more. In the case of electrolytic plating, it is easier to form a thicker film than in the case of electroless plating on the substrate side. The reason why gold, silver, copper, platinum, palladium, tin, indium, and their respective alloys are used as the bump forming metal is that they have excellent electrical characteristics and good bonding properties.
[0014]
The bare chip bumps thus formed are placed on the second electroless plating film of the resin substrate and bonded by heat treatment. The mounting component on which the bare chip is mounted in this way ensures a sufficient distance between the bare chip and the resin substrate. Therefore, even if stress due to the difference in thermal expansion coefficient occurs between the resin substrate and the bare chip. The stress can be surely relieved.
[0015]
【Example】
An electroless copper plating film (first electroless plating film) as a “pad” was formed on the surface of the substrate using a self-catalyzed electroless copper plating solution on a resin substrate made of epoxy. .
[0016]
The electroless copper plating solution used was PB-570 (trade name) in the Interplate process of EBARA Eugene Corporation. Using this electroless copper plating solution, a fine pattern was formed on the resist-patterned substrate. An electroless copper plating film was formed.
[0017]
The thickness of the electroless copper plating film was 30 μm, and the precision of the fine pattern as the “pad” was maintained.
[0018]
Then, the electroless copper-plated resin substrate is immersed in substitutional tin plating, and only on the fine pattern of the electroless copper plating film, an electroless tin plating film (second electroless film) as a “bonding layer”. (Plating film) was formed. The thickness of the obtained electroless tin plating layer was 12 μm.
[0019]
The electroless tin plating solution has the following composition and conditions.
・ Methanesulfonic acid …………………………… 100ml / l
・ Stannous chloride …………………………………… 45g / l
・ Thiourea ……………………………………… 100g / l
・ Bath temperature ……………………………………………… 70 ℃
・ Time ……………………………………………… 3 hours 【0020】
Next, an electrolytic gold plating film as a “bump” was formed on a flip-chip metal pad as a “bare chip” using a gold electrolytic plating solution. The thickness of the obtained electrolytic gold plating film was 20 μm.
[0021]
The electrolytic gold plating solution used was Microfab Au100 (trade name) manufactured by Nippon Electroplating Engineers.
[0022]
The flip chip on which the bump was formed was mounted on the resin substrate, and the bump of the flip chip and the electroless tin plating film of the substrate were joined by heat treatment. Heating was performed in the atmosphere using a flux R5003 (trade name) manufactured by Nippon Alpha Metals Co., Ltd., at a heating temperature of 230 ° C. and a heating time of 3 minutes.
[0023]
The distance between the flip chip and the substrate bonded in this way is as much as 40 μm, and the stress caused by the difference in thermal expansion coefficient between them can be surely alleviated.
[0024]
【The invention's effect】
According to the present invention, a sufficient distance can be ensured between the bare chip and the resin substrate, and even if a stress due to a difference in thermal expansion coefficient is generated between the resin substrate and the bare chip, the stress is reliably ensured. Can be relaxed.
Claims (1)
表面に、銅、銅合金、ニッケル、ニッケル合金の群から選ばれた自己触媒型無電解めっき液にて20μm以上の第1無電解めっき膜を形成し、この第1無電解めっき膜の上に、金、金合金、銀、銀合金、錫、錫合金の群から選ばれた置換型無電解めっき液により第2無電解めっき膜を形成したベアチップ搭載用の樹脂基板上に搭載して、
樹脂基板の第2無電解めっき膜と、ベアチップのバンプとを加熱処理により接合し、
ベアチップと樹脂基板との熱膨張率の差により生じる応力を緩和できる距離が確保されたことを特徴とするベアチップ実装部品。On the bare chip pad, bumps of 20 μm or more are formed with a kind of electrolytic plating solution selected from the group of gold, silver, copper, platinum, palladium, tin, indium, and their respective alloys.
On the surface, a first electroless plating film of 20 μm or more is formed with an autocatalytic electroless plating solution selected from the group consisting of copper, copper alloy, nickel, and nickel alloy, and the first electroless plating film is formed on the first electroless plating film. Mounted on a bare chip mounting resin substrate on which a second electroless plating film is formed with a substitutional electroless plating solution selected from the group consisting of gold, gold alloy, silver, silver alloy, tin, and tin alloy,
The second electroless plating film of the resin substrate and the bump of the bare chip are joined by heat treatment,
A bare chip mounting component characterized in that a distance that can relieve stress caused by a difference in thermal expansion coefficient between a bare chip and a resin substrate is secured .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31030596A JP3846948B2 (en) | 1996-11-21 | 1996-11-21 | Bare chip mounting parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31030596A JP3846948B2 (en) | 1996-11-21 | 1996-11-21 | Bare chip mounting parts |
Publications (2)
Publication Number | Publication Date |
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JPH10150121A JPH10150121A (en) | 1998-06-02 |
JP3846948B2 true JP3846948B2 (en) | 2006-11-15 |
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JP31030596A Expired - Fee Related JP3846948B2 (en) | 1996-11-21 | 1996-11-21 | Bare chip mounting parts |
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JP2006179656A (en) * | 2004-12-22 | 2006-07-06 | Toshiba Corp | Flexible circuit |
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1996
- 1996-11-21 JP JP31030596A patent/JP3846948B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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JPH10150121A (en) | 1998-06-02 |
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