JPH02226356A - Release of blocking in multibus multiple processor system - Google Patents

Abstract

PURPOSE: To gradually cancel a multi-bus system by the repetition of operations by sending out a single congestion mitigation signal for negating an allocation result relating to all the processors of a module and cancelling a bus possession right signal. CONSTITUTION: All processing modules are provided with the plural processors 14 and the respective processors are arbitrarily connected through a local bus 16 to a local memory 15. The terminal bus connection module of a switching bus 13 cooperates with the processor 18 and manages a terminal transmission bus 19 for connecting a transmission/reception line 10. Also, the system board 20 of a management bus 11 monitors the entire system. Then, a function for detecting the block of the module and the function for releasing the bus from the module are imparted to a block cancellation board and a bus releasing function sends out the single congestion mitigation signal for negating the allocation result and cancelling the bus possession right signal relating to all the processors of the module. Thus, the multi-processor system is excellently cancelled.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system of the type that includes at least one processing module consisting of a plurality of processors connected to a main bus. The invention more generally includes:
The present invention relates to a multi-bus system in which a plurality of processing modules are connected to each other via a bus coupling module.

This type of configuration is particularly available under the trade name "^1" by the applicant.
Catel 8300'' switches are found in data switching systems such as those commercially available.

Building 9F and Building 1 - This type of multiprocessor system provides two-phase access to the main bus for the corresponding module for each processor.
+o-phase) process. For example, in the first phase, which corresponds to one clock cycle, all bus access requests from all processors of the module are processed by the priority logic to identify the "winner" of the allocation process. . This "winner 7" becomes the next owner or "master" of the bus. In the second phase, when the bus for the immediate module becomes available, the bus capture circuit connected to the processor named VI issues a bus ownership signal, ensuring that only this processor can access the bus. become.

In the case of a multi-bus system, bus coupling modules interconnecting the various processing modules connected to different buses work together in pairs for each bus to satisfy general access requests to the corresponding destination bus. Establish a two-way link accordingly.

Data transfer between modules may involve passing through multiple consecutive buses to reach the destination processor.

As is well known, signals on the bus may be damaged as a result of a defect (failure) in the transmitting or receiving circuits on the board connected to the bus, or as a result of a short circuit in the backplane, or due to other reasons. Disturbances can result in blocking of the hoard's allocation module or bus capture logic and bus management logic present on the bus.

If such blocking occurs when a bus coupling module is connected to a remote module, the blocking condition may be propagated to another bus. In the worst case, the entire configuration may be completely blocked.

Methods already exist for unblocking multipath multiprocessor systems.

Among these methods is a known method of sending a bus reset signal from the system board.

The purpose of this reset signal is to act on the registers connecting each module's processor and the bus coupling module to maintain each board's ability to receive signals carried by the bus, while The purpose is to prevent transmission.

However, sending a reset signal is not suitable for multipath structures where loops are present. In fact, in closed sequence or closed loop circuits, where at least three buses are coupled in pairs, it is necessary to send a reset signal to the entire looped system. Therefore, the reset signal is neutralized (neutral 1zation)
self-retention as a result of specific mechanisms. This means that reset 1- needs to be performed bus by bus rather than a global reset.

Also, the system board may sometimes find itself in a situation where it has difficulty controlling the bus, either as a result of a conflict with the bus coupling module board or as a result of loss of priority access to the bus.

SUMMARY OF THE INVENTION In order to overcome these drawbacks, it is an object of the present invention to provide a bus unblocking system that uses a completely controlled method to gradually unblock a globally blocked multi-bus system through repeated operations. The method of the invention has the advantage that a defective module can be isolated from the remaining modules of the system without disturbing the system's software configuration or the running bus cycles.

The method of the present invention is also perfectly compatible with existing systems for managing conflicts of simultaneous mutual access requests between two buses.

The method of the invention can also be used to transmit over multiple consecutive cycles without releasing the bus.

The present invention provides a method for unblocking a multiprocessor system in order to achieve the above-mentioned and later-described objects. The multi-processor system includes at least one processing module consisting of a plurality of processors connected to a single main bus, each of the processors comprising a cell that manages access to the main bus l\ using two phases. , the cell includes a bus allocation system and a bus capture circuit, the bus allocation system in a first phase determining the negative or positive arbitration of access requests issued by the processors of the modules during the same cycle with respect to the corresponding processors; If a positive result signal is sent by the allocation system during the first phase, the bus acquisition circuit sends the bus ownership signal in a second phase to the corresponding processor. This is a type of system that allows people to access the bus. The feature of the unblocking method of the present invention is that the unblocking boat is provided with a function of detecting a block in a module and a function of releasing a bus from the module, and the bus releasing function includes a function for all processors of a module. Single congestion mitigation (decoBestiB) that makes the allocation result negative and cancels the bus ownership signal.
It consists of transmitting a signal.

The method of the invention is characterized in that a signal indicating the arbitration result of the allocation module is sent from an arbitration logic of the module, and the input of this arbitration logic receives the allocation participation signal of each processor that has requested access to the bus during the same cycle. It is advantageous for use in multiprocessor systems adapted to accommodate this.

In this case, in the present invention, the single congestion mitigation signal inhibits each of the processors of the module from participating in the allocation.

In one advantageous embodiment, the method of the invention provides that there is a processing module assembly comprising at least two processing modules, each processing module connecting to at least one other module via a pair of symmetrical main bus coupling modules. , and if each bus coupling module participates in an allocation and bus sequestration mechanism with respect to the destination bus, the congestion mitigation signal is transmitted from each of said coupling modules connected to the bus to be blocked to the allocation module and bus sequestration. The circuit is characterized in that it is supplied to the circuit.

In one advantageous embodiment of the method of the invention, the unblocking board sends congestion mitigation signals to the buses when a plurality of buses interconnected by the coupling module are blocked in cascade. to release the bus, instruct the bus coupling module of the released bus to send a congestion relief signal to the next bus, and/or to separate the next bus if it is out of order. In order to reduce the congestion of each bus, starting from the closest bus, the congestion reduction is iteratively performed by alternately sending a command to inhibit the assigned module of the combined module.

One of the preferred features of the invention is that when the bus coupling module is provided with means for managing collisions of mutual access requests issued by two adjacent buses during the same cycle, said bus congestion mitigation signal and collision The cancellation signal consists of one signal.

If the collision signal is sent by a bus coupling module, a reset signal may optionally be sent to the bus of the blocked corresponding module before sending the congestion relief signal.

Advantageously, said congestion mitigation board comprises means for identifying a defective board and/or a module of a defective board causing blocking, and means for neutralizing said board and/or for separating said module.

Advantageously, according to the invention, the congestion mitigation board is a system board for resetting said multiprocessor system and/or a monitoring board for monitoring one of the processing modules of said multiprocessor system.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the invention will become clearer from the following description of a non-limiting preferred embodiment based on the accompanying drawings.

Figure 1 schematically illustrates a multipath multiprocessor system when used as a data switch.

The data switch functions to receive digital signals sent over transmission lines 10, to screen and reconstruct this data with multiprocessor processing means, and to retransmit it over the appropriate transmission line 10.

In the simple multiprocessor multipath switch shown in FIG. 1, a management bus 11, a processing bus 12, and a switching bus 13 can be distinguished.

Each of these buses 11, 12, 13 corresponds to one processing module. Each processing module includes a plurality of processors 14, each optionally connected to a local memory 15 via a local bus 16. The switching bus 13 further includes a terminal bus coupling module 17.
, which in cooperation with the processor 18 manages the terminal transmission bus 19 connecting the transmitting/receiving lines 10 .

Management bus 11 includes a system board 20 that monitors the entire multipath multiprocessor system.

Lotus 11.12.13 is for example XB [IS (French painting Alc
It may be a product of atel CIT company) type. This type of bus mainly carries five signals:

address signal, two-way data signal, control signals for data exchange; control signals for bus assignment, Control signals for system management.

Each bus may receive, for example, up to 16 processors (master board), and the remaining locations may correspond to physical addresses to slave board 1 (eg, memory board).

Buses of various multiprocessor systems 11.12.13
are connected to each other via bus coupling modules 21 which are connected in pairs.

FIG. 2 shows the structure and function of a pair of bus coupling modules 22.23 connecting two buses 24.25.

Several types of bus coupling module structures are possible. An example of this is a binding module with "mailbox" type functionality.

The embodiment described here simulates the extension of a transmission bus.
1 to [Corresponds to functions including address selection 'J. Each coupling module 22.23 is connected to a respective bus 24.23.
Receiving module 26□, 26 that receives data from 25
3 and a transmission module 272.273 for transmitting data received from the remote coupling module 23.22, respectively, via the bus 24.25. The connections of the two coupling modules 22.23 are therefore between the receiving module 262 and the transmitting module 273 (data transfer from bus 24 to bus 25) and between the receiving module 263 and the transmitting module 272 (from bus 25 to data transfer to bus 24).

Each transmitting module 262.263 cooperates with a memory 282.283 containing a table of addresses dedicated to the remote bus.

The forwarding decisions made by each binding module 22.23 depend on the contents of said address table.

Each transmitting module 272.273 also has a bus 24.
292 and 293 for managing access to 25.

This type of bus coupling module is detailed, for example, in French Patent Application No. 8221401 of December 21, 1982.

FIG. 3 shows the bus access request logic corresponding to each mask processor of a processing module having a single bus 11.12.13. The access request logic includes a synchronous distributed access allocation system 31 that operates according to an arbitration process of access requests 30 issued by processors and a signal 33 that grants or disallows seizing the bus depending on the outcome of the distributed allocation operation. bus acquisition logic 32 connected to the allocation system by the bus capture logic 32;

The allocation system 31 receives access requests 47 from a bus request logic 34 consisting of a flip-flop synchronized with the clock signal of the allocation module, arbitrates these access requests, and sends an arbitration result 33 to the corresponding processor. It is composed of a so-called allocation circuit 35. Arbitration is conducted on the basis of fixed priority or circuit priority.

The 16 physical master board addresses connected to bus 12 are divided into two groups containing eight addresses, and one group is given priority (signal GP/). In either group, priority is given via priority signals PRI-PR7. Signals GP/, PRI, and PR7 are input/output as open collector signals on the main bus 12.

With fixed priority, priority increases in steps from 0 to 7, and is given one at a time to processors connected to physical addresses on the bus. The next owner or "master" of bus 12
The determination is made by overriding the signal PR with "1".
rwrite) logic. At the end of the allocation cycle, the processor that belongs to the active group CP and whose PR line is active becomes the "winner" of the arbitration.

In the case of cyclic priority, the priority position (
PRO to PR7) change.

The allocation circuit 35 further includes another line connected to the bus 12;
It includes, among other things, a line identifying the address of the physical location of the line connected to the current owner of the bus (with cyclic priority), a synchronization clock line for the allocation module 35, and a "bus busy" line.

Once the participating processors are determined after an allocation operation, the allocation module communicates this information to the bus acquisition logic 32 by an allocation result signal 33. This logic 32 monitors the bus 12, seizes the bus at the end of the cycle being executed, and sends a signal 36 to the allocation module 35. This signal is a signal that gives permission to newly allocate the next bus owner.

Bus capture circuit 32 also sends an address strobe signal indicating the presence of an address during a cycle or a data strobe signal indicating the presence of data during a cycle to bus 12 and receives a data acknowledge signal. The circuit 32 also sends out signals 37, 38 indicating ownership of the address and data buses.

The board is further configured to perform a reset command 40 upon issuance of a reset command 40 or an external inhibit command 41, e.g.
It also includes a line 39 that causes the allocation module 35 to cease functioning due to a disconnection command sent by the . Bus request logic 34 and bus capture logic 32 also include respective reset lines 42,43.

The operation and data transmission of the system of FIG. 1 is performed as follows.

Because the transmission cycle is asynchronous, the bus is blocked by the requesting master board until the addressed board responds.

If the destination board does not respond, the requesting board's watchdog timer j starts to release the bus and begin error handling.

The bus coupling module 21 analyzes the addresses on the corresponding bus and opens the path to the remote bus if necessary after address selection. As a result, the processor 14 connected to the bus 11 can address the processor 14 or the memory 15 connected to the bus 12.

In that case, first the bus 11 is blocked. bus 11
The coupling module 21 of bus 1 recognizes the requested address and
Open the passage to 2.

This bus is captured and blocked by the address if it is not in use. When a response is issued from the destination, the sending processor releases the two buses 11 and 12 upon receiving the response from the destination.

Transfers from bus 11 to bus 13 are performed by bus 11 and bus 1.
Since there is no coupling module pair that directly couples 3,
Requires the use of intermediate bus 12. The watchdog timer of each processor is calculated such that the transfer is performed using the cascade of the maximum number of buses involved in the transfer of the farthest location I\.

As mentioned at the beginning of this specification, any disturbance to the signals on a bus, as a result of a defect in the transmit or receive circuits on the board, or due to a short circuit in the backplane, The assigned board's allocation module 35 or bus capture logic 32 is blocked. If blocking occurs when code residing on an address bus corresponds to an address of a board residing on another bus, this blocking condition may propagate through the bus-coupled module board 21 to the other bus. In the worst case, the entire multi-bus system may be completely blocked. This is, for example, the first
The illustrated switching system deals with the case where a disturbance occurs during data transfer between bus 11 and bus 13.

As an example, if the following signals are permanently set to zero, disturbances may occur that may propagate to multiple adjacent buses.

Signals that, if disturbed, will cause allocation module 35 to block include:

Signals indicative of a block mode transmission (seizing the bus over multiple cycles), priority group signal cp, bus seize signal BBSYG.

Indicates that there is no address or data in the cycle on the bus to the strobe signal SG/and UDSG to the data acknowledge signal DTΔCKG, etc.

The signals listed here serve as non-limiting examples to explain the invention. If these signals are permanently set to 1, corresponding to a stopped or inactive state, unblocking of the system, where disturbances normally do not propagate to other buses, is accomplished by performing the functions described below.

Blocking detection function, function to sequentially execute congestion relief for each lotus, function to isolate defective lotuses or processors, and repair defective units at will.

The bus congestion alleviation function, which is one of the components of the present invention, consists of transmitting a unique and specific congestion alleviation signal 45 shown in bold line in FIG.

This single signal 45 performs two functions: it releases bus 12 and it prevents another mask board connected to bus 12 from interfering with this bus.

These two functions include an action on the bus request logic 34 and an allocation circuit 35 performed via the inhibit module 44.
and actions on bus capture logic 32.

Signal FINHAL 46 sent from inhibition module 44
occurs synchronously with the clock signal and is maintained for the entire duration of a single congestion relief signal 45. This signal is sent to the allocation module 3 in response to an external command 40.41.
It is sent via the same line as the inhibition signal 39 of No. 5.

The congestion relief signal acts on the allocation module as follows.

Prevents the request given to the allocation module 35 by the request logic 34 to: allow the allocation module 35 to participate in the allocation and send priority signals GP/and P to L to PA7 on the bus 12;
Causes a reset of the internal bistable circuit of: Causes a reset of a flip-flop that generates a signal BBSYG/ indicating the result of arbitration between access requests for the corresponding processor.

The congestion relief signal also resets the internal flip-flops of bus capture logic 32 that generate control signals 38 for the address and data buses.

In other words, such systematic action on the access management means of each processor on the bus releases the bus from the current bus owner, causes the future owner of the bus to deactivate the arbitration winner signal, and Neither allocation module will be able to participate in the access request arbitration operation.

The method can then reinstate the canceled request by acting on the hash request logic 34.

Therefore, the congestion relief signal 45,46 is assigned to the allocation module 3.
5 can be regarded as a "super priority °" signal. Therefore, this congestion mitigation method does not disturb either the software configuration or the running bus cycle.

FIG. 4 shows a method for unblocking when the blocked state extends to a plurality of buses.

The mask board 84 connected to the bus 81 is at the origin of blocking in the cycle towards the slave board connected to the bus 83. Therefore, the three buses 81, 82 and 83 are in a blocked state. This blocking is caused by a condition such as, for example, the strobe signal SG/, which indicates the presence of an address during the cycle, is set to zero on bus 81. This blocking propagates to bus 82 and bus 83 according to propagation direction 87 because the connections are made by bus coupling modules 8612 and 8623 due to the pass address selection state.

As soon as the mask board 88 or system board F (not shown) detects blocking of the configuration, the defective bus 88
bus coupling module board 86 providing access to 1
Steps are taken to isolate the defective bus by placing the allocation modules of 32.8627.8621 and 86,2 in the inhibited state.

This process is as follows.

Board 88 sends a decongestion signal to bus 83, resulting in the bus being released by bus coupling module 8632.

The board 88 then routes the congestion mitigation signal from the bus coupling module 8632 to the bus coupling module 8623 to the bus 8.
2, so that bus 82 is freed by unblocking of coupling module 8621.

Thereafter, the board 88 writes the inhibit bit of the assignment module of the bus coupling module 8621 to isolate the defective bus 81 .

Eventually, board 88 sequentially sends opposite (inactive) decongestion signals to buses 82 and 83 to reinstate the inhibited access request.

Single-signal congestion mitigation processing is advantageously used in multi-bus systems that include a bus coupling module with simultaneous mutual access request management means (conflict management means) as described below. In that case, a highly favorable cooperation exists between conflict management and congestion mitigation management due to the similar structural and functional characteristics of the corresponding systems.

The "collision phase-1i4→" state can be explained based on FIG.

Board 84 connects to bus 81 if it wants to reach board 91.
capture and block. At the same time, if board 90 wants to reach board 89, board 90 will seize bus 82 and block it. When the two buses 81 and 82 are blocked in this way, the coupling modules 8612 and 86□2 are unable to respond. This is a collision situation. Unless special unblocking equipment is provided,
The system remains blocked until the watchdog timer signal appears on master boards 84 and 90 and error handling is initiated.

To avoid this problem, a method can be used to provide a collision signal COLG to the bus. This signal may be sent from each bus coupling module 86 when a collision is detected by the coupling module. Typically, the priority binding module and non-priority binding module are determined for each pair of binding modules at the time of configuration initialization. When a collision occurs, the non-priority module issues a signal COL. This signal is received by all master boards connected to the corresponding bus and causes the following two operations to occur.

Acts on bus control signals to cause the bus to be released from the board that is capturing and blocking it. As a result, the board enters an inhibited state and waits for permission to recapture the bus and complete the cycle.

Acts on the remaining mask boards' allocation systems to prevent these master boards from seizing the bus.

In this way, only the coupling module that issues the conflict signal can seize the bus and establish a path to the destination that is considered a priority for the cycle. Once the path is established, this coupling module stops transmitting the signal COLG so that the remaining boards can again participate in the bus allocation phase and gain access to the bus depending on the arbitration result.

Thus, there is true cooperation between the mechanism for resolving conflicts between buses and the unblocking process of a multi-bus system. Therefore, it is advantageous to use the same congestion mitigation signal to implement these two mechanisms.

FIG. 5 briefly illustrates the functional modules that need to be included on the system board to manage the transmission of a single signal related to congestion mitigation and collisions.

To realize this configuration, a bistable circuit capable of sending out a single congestion relief signal must be added to the system board, the bus master board UTS, and the bus coupling module. This bistable circuit can be addressed by the program in the private area of the system board and the UTS board, as well as in the coupling area of the bus coupling module. This congestion mitigation/collision bistable circuit is set to 1 by a write cycle, for example, and then set to 0 by another write cycle.

The transmitted congestion relief signal affects all boards present on the bus except for the board 1~ that transmits it.

FIG. 6 briefly shows the structure used in the bus coupling module pair 61, 62 connecting the first bus 63 and the second bus 64. Although the mechanism is shown in a single direction in this figure, it can of course function symmetrically in other directions as well. The collision/congestion mitigation bistable circuit 65 of the coupling module 61 provides congestion mitigation/congestion mitigation bistable circuit 65.
A collision signal 66 is caused to be sent from the corresponding bus coupling module 62 to the remote bus 64.

Figures 5 and 7 briefly illustrate the logic modules that must be included on the system board and bus coupling module, respectively, to manage a single collision/congestion mitigation signal.

As shown in FIG. 5, in the case of a system board, an internal signal 51 that controls the sending of congestion/congestion mitigation signals is provided by software instructions 52 via a flip-flop 53. A single congestion/decongestion signal 55 is sent to the bus via a buffer circuit 54.

A buffer circuit 56 acknowledges receipt from the bus to acknowledge a single collision/congestion mitigation signal 55' that is not necessarily sent by the system board. internal signals 51 from software instructions involved in sending collision/congestion mitigation signals;
The signals 57 from the buffer register 56 relating to reception from the bus are sent to an enabling circuit that inhibits the board's bus acquisition logic and allocation module when collision/congestion mitigation signals are not sent from the system board.

FIG. 7 also briefly shows this same type of arrangement.

This configuration corresponds to the collision/congestion mitigation signal admission logic of the bus coupling module hoards.

Internal signals 71 related to collisions are generated by external software instructions 72 via flip-flops 73.

A software instruction to this software 1 is sent from a remote bus coupling module (flip-flop 65 of coupling module 61 in FIG. 6).

The collision internal signal 71 causes a collision/congestion mitigation signal 75 to be sent to the corresponding bus via the buffer register 74. If the bus coupling module does not have priority, the collision/congestion mitigation signal 75 is sent from the bus coupling module when it is detected that two mutual access requests 70 are issued simultaneously. This state corresponds to a situation in which a so-called collision has been detected in the bus pair. The non-priority bus binding module inhibits requesters on the corresponding bus during this conflict condition.

The bus coupling module also acknowledges collision/congestion mitigation signals 75' received from the bus. This is because this signal is not necessarily sent out from the coupling module. The received collision/congestion mitigation signal 75' is passed to a buffer register 76 so that an internal signal 77 output from this buffer register is provided to one of the inputs of an enabling circuit 78. A collision signal is provided from the output of circuit 78 and is sent to the allocation module and the bus capture logic of the combining module. The parameters that control the sending of signal 79 are as follows.

Internal signal 71 related to collision, internal signal 7 related to reception of collision/congestion mitigation signal on bus
7. Enabling signals 92 activated by congestion mitigation signals in response to software instructions 72 or by inhibiting signals to acknowledge collisions when two mutual access requests are issued simultaneously in a coupled module pair; , a signal that causes the line BBSYG (next owner of the bus) to be released at the end of a block mode transfer, a signal that acknowledges a collision on a remote bus.

The last two signals are sent via line 93, for example.

The final signal 93 (a signal acknowledging a collision on a remote bus) indicates a priority bus binding module that has been activated by a non-priority bus requestor (those inhibited by the non-priority bus binding module as described above). Required to free allocation modules.

[Brief explanation of the drawing]

FIG. 1 is a simplified explanatory diagram showing the overall structure of a multipath multiprocessor system to which the method of the present invention can be applied when used as a data switch, and FIG.
3 is a simplified illustration of the principle of the function of connecting two adjacent buses via a pair of bus coupling modules in the system of FIG. 1; FIG. 3 is a system of FIG. FIG. 4 is a simplified diagram illustrating the logic of access requests, bus allocation, and bus capture connected to one processor of FIG. 5 is a simplified diagram illustrating a functional module for generating the congestion mitigation signal of the present invention by a system board of a multipath multiprocessor system; FIG. 6 is a simplified diagram illustrating the functionality of the method of the present invention in a bus coupling module; FIG. 7 is a simplified diagram illustrating a functional module for processing congestion mitigation signals of the present invention in a bus coupling module with logic for resolving conflicts between mutual access requests issued simultaneously between two adjacent buses; . 20.28...Block release board, 31...
...Assignment module, 35...Arbitration logic.

Claims (7)

[Claims] (1) at least one processing module comprising a plurality of processors connected to a single main bus, each of the processors comprising a cell for managing access to the main bus using two phases; a bus allocation system and a bus capture circuit, wherein the bus allocation system, in a first phase, signals, with respect to a corresponding processor, a signal representing a negative or positive outcome of arbitration of access requests issued by the processors of the module during the same cycle; and if a positive result signal is sent by the allocation system in a first phase, the bus acquisition circuit sends a bus ownership signal in a second phase;
A method for unblocking a multiprocessor system of the type that allows a compatible processor to access a bus, the method comprising: providing an unblocking board with a function of detecting blocking of a module and a function of releasing the bus of the module; Blocking in a multiprocessor system, characterized in that the release function is implemented by sending a single congestion relief signal that makes the allocation result negative and cancels the bus ownership signal for all processors of the module. How to release it. (2) a signal indicating the arbitration result of the assignment module is sent from arbitration logic of the module, the input of the arbitration logic receiving the assignment participation signal of each processor that requested access to the bus during the same cycle; 2. The method of claim 1, wherein a single congestion relief signal inhibits allocation participation of each processor of a module. (3) at least two processing modules, each processing module connected to at least one other module via a pair of symmetrical primary bus coupling modules, each bus coupling module allocating and seizing a bus with respect to a destination bus; 2. In a multi-bus system such as that involved in the mechanism, the decongestion signal is sent to an allocation module and a bus capture circuit of each combination module connected to the bus to be unblocked. Or the method described in 2. (4) When a plurality of buses interconnected by the main bus coupling module are blocked in a cascade, the unblocking board sends a congestion mitigation signal to the bus to release the bus; and instructing the bus coupling module of a bus that has been connected to a bus to send a congestion relief signal to the next bus and/or inhibiting the allocation module of said coupling module to isolate this bus if the next bus is faulty. 4. The method of claim 3, further comprising: iteratively decongesting each bus, starting from the nearest bus, by alternating the operations of sending the command . (5) If the bus coupling module is equipped with means for managing conflicts between mutual access requests issued from two adjacent buses during the same cycle, the bus congestion mitigation signal and conflict resolution signal are integrated into one signal. 4. A method according to claim 3, characterized in that: (6) The congestion alleviation board includes means for identifying a defective board and/or a module of the defective board that causes blocking, and means for neutralizing the board and/or separating the module. The method according to claim 1, wherein: 7. The method of claim 1, wherein the congestion mitigation board is a system board that resets the multiprocessor system and/or a supervisory board that monitors one of the processing modules of the multiprocessor system.