JP2531657B2 - Bus control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bus control system in a multiprocessor system having a plurality of hierarchical buses that are in a superordinate and subordinate relationship.

[Conventional technology]

2. Description of the Related Art Conventionally, in a multiprocessor system having a plurality of hierarchical buses, when communication is performed between processing devices connected to different buses, the processing device obtains the right to use all buses that are transit routes. It is necessary. As a method to make this possible, conventionally, there is a bus controller that centrally manages the usage rights of all buses, and after the bus controller secures the usage rights of all buses that are transit routes in advance, A method has been considered in which the information of the processing device on the transmission side is made to reach the processing device on the reception side by opening the gate of the bus coupler existing between the buses.

However, in this method, the bus controller centrally manages all the buses and secures all buses that are transit routes in advance when transferring information. Besides, it is necessary to know the number of the processing device on the receiving side in advance.

[Problems to be solved by the invention]

For this reason, it has been extremely difficult to construct a practical large-scale multiprocessor system because the control of the bus controller is complicated and the amount of hardware and interface lines are increased.

It is an object of the present invention to propose a decentralized bus control method instead of a centralized bus control method to solve the above-mentioned drawbacks and enable the construction of an economical and efficient large-scale multiprocessor system. Especially.

[Means for solving problems]

To achieve the above object, in the present invention, in a multiprocessor system having a plurality of hierarchized buses that are in a higher-lower relationship, it is desirable to transfer information on the upper-layer bus to the lower-layer bus. Second request to transfer information on the lower layer bus to the upper layer bus.
When the bus requester and the request of the above request collide with each other in a bus coupler that connects the two buses, the collision detection means for detecting the collision and the first request are given priority over the second request. To the originator of the second request that is connected to the first request, and when the information transferred to the lower layer according to the first request is received by the intended transfer destination, the transfer request is temporarily stopped. Instructing means for instructing the source of the second request to stop the above-mentioned instruction and restart the transfer request.

[Action]

According to the present invention, as in the conventional case, the usage rights of all the buses to be the transfer route are secured in advance and then the usage rights are secured when two adjacent buses become available instead of transferring. Then, by using the method of starting the transfer partially, these are sequentially repeated to proceed the transfer sequentially, and the information is transferred to the intended receiving side processing device. At that time, each bus independently performs an operation of capturing an adjacent bus and transferring information in addition to the information transfer operation normally closed in its own bus.

Therefore, a transfer request from the lower bus to the upper bus may collide with a transfer request from the upper bus to the lower bus. The present invention makes it possible to resolve such a bus access conflict easily and economically, and is useful for realizing a distributed bus access control system.

Whereas the conventional technology centrally manages the busy status of all buses and various transfer requests, and uses a complicated bus controller to perform traffic control in advance to prevent such collisions, The point that such complicated control is not performed is fundamentally different from the prior art of the present invention.

〔Example〕

FIG. 1 is an explanatory view showing an embodiment of the present invention. In the figure, 1 is a processing device (each processing device is P _i1 , P _i2 , ...
,, P _in ), 2 is a bus combiner composed of ordinary wiring logic (each bus combiner is B _{(i-1) 1} , ..., B _{(i-1) k} ,
.. ₍ denoted by B _{(i-1) m} ) 3 is a bus of the i-th layer that connects the processing device 1 and the bus coupler 2.

Further, the i-th layer bus 3 has a bus combiner 4 of Bik
, And the bus 3 of the i-th layer via the bus combiner 4.
And the bus 7 of the (i + 1) th layer as the upper layer thereof are connected. Buses of other layers not shown are similarly connected to form a multiprocessor system having a plurality of hierarchical buses.

At this time, information transfer between arbitrary processing devices is performed by sequentially capturing a bus serving as a transfer path (a method of transmitting information while setting a transfer path, or after setting all transfer paths first,
(Any method of passing information is acceptable) (the above-mentioned collision problem of information transfer, which is a solution to the present invention, is not assumed in the method of centrally managing the vacancy of all buses).

Further, the bus combiner 4 (Bik) is a transfer interruption / restart instruction means (signal) to the processor 1 and the bus combiner 2 (both within the range of the i-th layer bus) connected to the i-th layer bus 3. It is equipped with 5.

The transfer suspend / resume instructing means 5 is specifically constituted by a signal line of a bus form different from the bus for information transfer, and the bus coupler 4 (Bik) broadcasts to the processing device 1 and the bus coupler 2. May be configured to give a transfer interruption instruction, or the bus coupler 4 (Bik) and the processing unit 1 and the bus coupler 2 may be individually connected by a lead wire to give a transfer interruption instruction. You may comprise.

Similar to the bus coupler Bik, other bus couplers also have the same transfer suspend / resume instruction means. At that time, transfer interruption
The restart instruction may be closed within one bus.

In the above-described configuration, the collision problem of information transfer as described above (information on the bus 3 of the i-th layer is
1) A request to transfer to the bus 7 of the hierarchical layer and a request to transfer information on the bus 7 of the (i + 1) th hierarchical layer to the bus 3 of the i-th hierarchical layer collide with each other at the bus combiner 4 (Bik)) The operation for solving the problem economically and economically will be described below.

First, on the bus combiner 4 (Bik), 2
Two information transfer collisions (eg, B _{(i + 1) k} as shown in Fig. 2 ₎
From B to Bik and B _{(i-1) 1} to Bik transfer)
Occurs, and the collision detection means (which is composed of general wiring logic) in the bus combiner Bik detects it, the bus combiner Bik determines the bus 7 of the (i + 1) th layer as an upper layer. All the devices (processors P _i1 , ..., P _in , bus combiner on the bus 3 of the i-th layer to prioritize the transfer request from
B _{(i-1) 1} , ..., All of B _{(i-1) m} ), a transfer interruption instruction signal is transmitted using the transfer interruption / restart instruction means 5. The device receiving the transfer interruption instruction signal is the i-th device.
If it is the information transfer source (B _{(i-1) 1 in} FIG. 2) on the bus 3 of the hierarchy, the information transfer is temporarily interrupted, and the bus 3 of the i-th layer is interrupted.
Is released (see FIG. 3). As a bus releasing method at this time, a device (B _{(i-1) 1} ) whose transfer is interrupted stops information transmission at a connection interface section with the bus 3, or a bus access control in the device is temporarily performed. Any of a variety of methods may be used, such as resetting and releasing the bus.

Although the transfer interruption instruction signal is received, the device which is not the transfer source does not need to perform any processing.

When the bus 3 of the i-th layer is released, the access right of the bus 3 of the i-th layer is given to the information transfer request from the bus 7 of the (i + 1) th layer, and the information transfer is performed (see FIG. 4). When this transfer information is received by the target transfer destination (for example, Pin _in FIG. 4) and the transfer ends, the transfer source device (B _{(i + 1) k} ) performs the transfer end processing (for example, the bus). Is released) and the transfer request from the bus 7 of the (i + 1) th layer to the i-th layer bus 3 is released. Bus combiner 4 (Bi
When k) detects the release of the transfer request, the device suspends the transfer suspend instruction signal being sent from the transfer suspend / resume instructing means 5 and accordingly suspends the information transfer (see FIG. 4). In this case, B _{(i-1) 1)} ) restarts the information transfer and returns to the transfer operation (in this embodiment, the stop of the transmission of the transfer interruption instruction signal is also used as the transfer restart instruction, but a separate signal line is provided. Method is also acceptable).

By the way, the information transfer destination from the bus 7 of the (i + 1) th layer is not the processor in the ith layer bus 3 but, for example, via the bus coupler B _{(i-1) 1)} and the further lower (i- 1) If it is after the hierarchical bus, a series of transfer operations to the lower bus are sequentially executed, and during that time, the transfer temporarily suspended due to the collision of the bus access remains waiting. The (i +
1) When the information transfer from the hierarchical bus is completed, the information transfer operation temporarily suspended by the transfer end processing is restarted, as described above. When a bus access collision occurs again during such a transfer to the lower bus, the problem of the collision can be solved and the information transfer can be normally performed by the same means as described above.

FIG. 5 is a circuit diagram showing a concrete configuration example of the bus coupler 4 described above. In the figure, 41 and 42 are transfer request detection circuits, D1 and D2 are 3-state drive gate circuits, and A1 to A4 are AND gates.

When the transfer request detection circuit 14 detects a transfer request from the (i + 1) layer bus to the i layer bus, the transfer request detection circuit 14 outputs "1" to the AND gates A1 and A3, indicating that there is a transfer request.
An i-layer bus use request is output to a bus arbiter (contention reduction circuit) not shown. Bus arbiter to use i-level bus
When the OK signal arrives, the AND gate A1 opens, so that the drive gate circuit D1 opens and the transfer from the (i + 1) layer bus to the i layer bus becomes possible.

Similarly, the transfer request detection circuit 42 uses (i
+1) When a transfer request to the hierarchical bus is detected, "1" is output to the AND gates A2 and A3 because there is a transfer request. At the same time, "1" is output to the AND gate A4 in an attempt to output the (i + 1) layer bus use request to the bus arbiter (contention reduction circuit) not shown, but before that, the transfer request detection circuit 41 issues a transfer request. If so, the AND gate A4 is closed because it has priority, and the (i + 1) layer bus use request is not output to the bus arbiter. But,
Otherwise it is output. When the bus arbiter sends a signal indicating that the (i + 1) layer bus can be used, the AND gate A2 opens, so that the drive gate circuit D2 opens and transfer from the i layer bus to the (i + 1) layer bus becomes possible.

When a transfer request signal is output from each of the transfer request detection circuits 41 and 42, the AND gate A3 detects that there is a collision and connects the transfer interruption instruction signal to the i layer bus (i + 1) layer. Send to the originator of the bus use request.

FIG. 5A is a conceptual diagram showing an outline of the configuration of the transfer request detection circuit 41 (42 is the same) in FIG.

In FIG. 5A, the device number of the transfer destination device from the (i + 1) layer bus to the i layer bus is fetched from the (i + 1) layer bus and registered in the memory circuit R1. In the memory circuit R2,
The numbers of the processing devices under the bus coupler 4 including the transfer request detection circuit 41 are registered in advance. When the comparison circuit CP receives an address strobe as a timing signal as an enable signal from a control unit (not shown), the comparison circuit CP compares the contents of both storage circuits R1 and R2 and outputs a signal indicating a transfer request if they match.

〔The invention's effect〕

As described above, according to the present invention, by providing the bus coupler with the means for transmitting the transfer interruption / resumption instruction signal closed in the bus, it becomes a problem between the hierarchical buses easily and economically. There are advantages that the problem of bus access collision can be solved, a complex centralized bus controller is not required, and a distributed large-scale multiprocessor system can be easily constructed.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of the present invention, FIGS. 2 to 4 are explanatory views showing an operation process of the embodiment of the present invention, and FIG. 5 is a concrete configuration example of a bus coupler. FIG. 5A is a conceptual diagram showing a schematic configuration of the transfer request detection circuit in FIG. DESCRIPTION OF SYMBOLS 1 ... Processor, 2 ... Bus combiner, 3 ... Bus of i-th layer, 4 ... Bus combiner for connection with upper bus,
5 ... Transfer interruption / restart instruction means (signal), 7 ...
+1) Hierarchical bus.

Claims (2)

(57) [Claims] 1. A multiprocessor system having a plurality of layered buses having a relationship of upper and lower levels, and a first request to transfer information being transferred on an upper layer bus to a lower layer bus. , When a second request to transfer information being transferred on the lower layer bus to the upper layer bus collides with a bus combiner connecting both buses,
Collision detection means for detecting this, and when the collision detection means detects a collision, it receives the detection output and interrupts the transfer on the lower layer bus to all the processing devices connected to the lower layer bus. Which is a suspending / resuming instruction means for instructing the
The processor that is the source of the request detects the transfer interruption instruction and temporarily interrupts the transfer being executed, and as a result, the bus combiner can pass the information of the upper bus to the lower bus, When it finishes, it will detect that and instruct all the processing units connected to the lower layer bus to restart the transfer on the lower layer bus, and thereby all processing units connected to the lower layer bus. Of these, the processing device which is the source of the second request detects the transfer restart instruction, and causes the transfer interrupt and restart instruction means to restart the interrupted transfer. A bus control method characterized in that 2. In a multiprocessor system having a plurality of layered buses having a relationship of upper and lower levels, a first request to transfer information being transferred on an upper layer bus to a lower layer bus. , When a second request to transfer information being transferred on the lower layer bus to the upper layer bus collides with a bus combiner connecting both buses,
Collision detecting means for detecting this, and when the collision detecting means detects a collision, the detection output is received and the source of the second request among all the processing devices connected to the lower layer bus is generated. Which is an interruption / restart instruction means for instructing a processing device which is the lower layer bus to interrupt the transfer, and the processing device which is the source of the second request detects the transfer interruption instruction and executes the transfer interruption instruction. Transfer is suspended, and as a result, the bus combiner can pass the information of the upper bus to the lower bus, and when the transfer is completed, this is detected and the transfer on the lower bus is stopped. Instructing the processing device that is the source of the second request to resume, thereby causing the second
Bus control, wherein the processing device, which is the source of the request for detecting the transfer resumption instruction, detects the transfer resumption instruction and restarts the interrupted transfer. method.