JPH0219456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-dimensional addressing device such as an image display device using liquid crystal, for example.

For example, it has been proposed to display television images using liquid crystals. In Fig. 1, 1 is an input terminal to which a television video signal is supplied, and the signals from this input terminal 1 are each transmitted through, for example, N channels.
Switching elements M ₁ , M ₂ ...M _n consisting of FETs
Lines L ₁ , L ₂ in the vertical (Y-axis) direction through...
supplied to L _n . Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Furthermore, an m-stage shift register 2 is provided, and a clock signal with m times the horizontal frequency is supplied to this shift register 2, and signals φ _H1 ,
φ _H2 ...φ _Hn are supplied to each control terminal of the switching elements M ₁ to _{M n} .

In addition, switching elements M ₁₁ , M ₂₁ . . . M _o1 , M 12 , M _{22 ,} M _o2 , . . . are provided in each line L ₁ to L _n , respectively.
...M _1n , M _2n ... One end of M _on is connected. Note that n is a number corresponding to the number of horizontal scanning lines. The other ends of the switching elements M ₁₁ to _{M on} are connected to the target terminal 3 through liquid crystal cells C ₁₁ , C ₂₁ . . . C _on , respectively.

Further, an n-stage shift register 4 is provided, a horizontal frequency clock signal is supplied to this shift register 4, and signal lines φ _V1 , φ _V2 . . . φ _Vo from each output terminal of this shift register 4 are connected to switching elements. Each row of M ₁₁ to _{M on} in the X-axis direction (M ₁₁ to _{M 1n} ),
(M ₂₁ to _{M 2n} )...(M _o1 to M _on ) are respectively supplied to control terminals.

That is, in this circuit, as shown in FIG. 2A and B, shift registers 2 and 4 output φ _V1 to φ _Vo every horizontal period, and the effective screen period T _HE during this period is , φ _H1 to φ _Hn are output from the shift register 2 for each pixel period. Further, the input terminal 1 is supplied with a signal as shown in FIG. 2C.

When φ _V1 and φ _H1 are output, switching elements M ₁ and M ₁₁ to _{M 1n} are turned on, and the current at input terminal 1 → M ₁ → L ₁ → M ₁₁ → C ₁₁ → target terminal 3 A path is formed, and the potential difference between the signal supplied to the input terminal 1 and the target terminal 3 is supplied to the liquid crystal cell _C11 . Therefore, the charge corresponding to the potential difference due to the signal of the first pixel is sampled and held in the capacitance of this cell _C11 . The light transmittance of the liquid crystal changes depending on the amount of charge. A similar process is performed sequentially for the cells C ₁₂ -C _on , and the amount of charge in each cell C ₁₁ -C _on is rewritten when the next field signal is supplied.

In this way, the light transmittance of the liquid crystal cells C ₁₁ to C _on is changed corresponding to each pixel of the video signal, and this is sequentially repeated to display a television image.

However, in this device, if the number of horizontal pixels is m, the shift register 2 must have m stages, and if a display device with high resolution is to be manufactured, the shift register 2 will become an extremely large circuit. For this reason, for example, when a circuit is integrated into an IC, an extremely large chip area is required.

Also, the on period of switching elements M ₁ to M _n is
T _HE /m, which is extremely short, results in insufficient charge accumulation in each liquid crystal cell C ₁₁ to C _on . Here, it is impossible to increase the amplitude of the input signal due to constraints such as the structure of the liquid crystal cell. Because of this, good image quality,
Especially contrast cannot be obtained.

Furthermore, since the charge is used in a state where the charge is insufficiently accumulated, the degree of insufficiency varies depending on changes in the level of the input signal, etc., and waveform distortion is likely to occur. It is also necessary to reduce the on-resistance of the switching element.
For this reason, the gate width of the switching element increases, and when integrated into an IC, a large chip area is required.

Conventional devices have these drawbacks.

In view of these points, the present invention is designed to eliminate the above-mentioned drawbacks with a simple configuration. An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, the lines L ₁ to _{L n} are grouped into groups of two, and the switching elements of each group are (M ₁ , M ₂ ), (M ₃ , M ₄ )...(M _n-1 , M _n ) control terminals are connected to each other. Further, the signal from input terminal 1 is supplied to a delay circuit 11 having a delay time of T _HE /m, and the signal from this delay circuit 11 and the signal from input terminal 1 are connected by switches 12 and 13.
They are alternately selected and taken out every T _HE /m period.

Then, the signal from the switch 12 is further transmitted through the delay circuit 14 of T _HE /m to the odd-numbered switching elements M ₁ , M _{3 .} . . M _n-1, and then to the lines L ₁ , L ₃ .
At the same _time , the signal from the switch 13 is supplied to the even-numbered switching elements M ₂ , M ₄ . . .
It is supplied to lines L ₂ , L ₄ ...L _n through M _n .

Therefore, in this circuit, when an input signal as shown in FIG. 4A is supplied, the delay circuit 11 outputs B.
A signal like this is output. and switch 1
By switching 2 and 13 in the same phase up and down as shown in the figure, a signal like D is taken out from the switch 12, and this signal is supplied to the delay circuit 14 to become a signal like E. . Further, a signal such as F is taken out from the switch 13.
That is, the signals of the odd-numbered pixels and the signals of the next pixel are simultaneously supplied to the lines L ₁ to _{L n} of each group.

Furthermore, by supplying a clock signal with half the frequency of the conventional one to the shift register 2,
Signals φ′ _H1 , φ′ _H2 ……φ′ _Hn/2 as shown in FIG. 4G
are formed and the switching elements M ₁ to 1 of each group are formed.
M _n is supplied. For this reason, the switching element M ₁
.about.M _n are turned on in turn for two pixel periods for each group, and the synchronized signals are supplied to odd-numbered lines and even-numbered lines, respectively.

When φ _V1 and φ′ _H1 are output, switching elements M ₁ , M ₂ and M ₁₁ to _{M 1n} are turned on,
Delay circuit 14 → M ₁ → L ₁ → M ₁₁ → C ₁₁ → Target terminal 3 and switch 13 → M ₂ → L ₂ → M ₁₂ → C ₁₂ →
A current path for the target terminal 3 is formed. Then, the first pixel and the second pixel are placed in liquid crystal cells C ₁₁ and C ₁₂ , respectively.
A charge corresponding to the potential difference due to the signal of the pixel is sampled and held, and the light transmittance of each liquid crystal is changed depending on the amount of this charge. Thereafter, the same process is performed sequentially for cells C ₁₃ -C _on , and the amount of charge in each cell C ₁₁ -C _on is rewritten by the signal of the next field.

According to the present invention, a signal is supplied to each liquid crystal cell C ₁₁ to _{C on} for two pixel periods, and a television image is displayed in this way.
Since the supply time is twice as long as in the conventional case, charge is sufficiently accumulated in each of the liquid crystal cells C ₁₁ to C _on . Therefore, there is no risk of the waveform distortion mentioned above, and
Images with good quality including contrast can be displayed.

Furthermore, since the number of stages of the shift register 2 is reduced to 1/2, the circuit configuration becomes extremely simple, and when integrated into an IC, the chip area and power consumption are reduced. That is, the power consumption of the shift register is proportional to the frequency of the clock signal and also proportional to the number of stages. Therefore, in the above example, both the frequency and the number of stages are halved, so the power consumption is reduced to 1/4.

Furthermore, since the signal supply time is long, the influence of the on-resistance of the switching element is reduced. Therefore, there is no need to increase the gate width, and the chip area occupied by the switching element is also reduced.

Note that the delay circuit may be a lumped constant circuit using L or C, a surface wave circuit, a CTD, or the like.

Also, in the above example, two delay circuits and switches are required, but compared to the fact that the number of stages of the shift register is halved and the power consumption is 1/4, there is no increase in chip area or power consumption. Very little.

Furthermore, the delay circuit 11 using CTD is shown in FIG.
14 and switches 12 and 13 will be shown below. In the figure, for the delay circuit 11, for example, a CTD ₁ such as a previous-stage signal processing circuit can be used. Here, CTD is, for example, the source of an n-channel FET,
The drains are connected in sequence, and a capacitor is connected between the drain and gate of each FET. Then, a clock signal φ ₁ as shown in FIGS. 6A and 6B,
φ ₂ is applied to the gates of every other FET, these FETs are turned on alternately, and the signal is
The data is transferred as shown in Figure C.

FETQ' _{o-2 is provided in parallel with FETQ o-2 two} stages before the final stage of CTD ₁ . Therefore, a signal as shown in FIG. 6D is taken out from FETQ'o _-2 , and a signal as shown in _FIG . 6E is taken out from the final stage FETQo.

Further, the drain of FETQ′ _o-2 is connected to switching elements M _a and M _b . Furthermore, the drain of the final stage FETQ _o is connected to switching elements M _a ′ and M _b ′. These switching elements M _a , M _{b '} are supplied with control signals _φ ' ₁ as shown in FIG _. A signal like H in FIG. 6 is taken out from _a and M _a ', and a signal like I is taken out from M _b and M _b '.

These signals are then supplied to CTD ₂ and CTD ₃ , and the connection point of FETQ _a3 and Q _a4 that constitute CTD _{2 and}
The signals at the connection point of Q _a4 and Q _a5 are FETQ _a and
By being supplied to the gate of Q _a ′,
A signal like this is extracted. This signal is supplied to the output terminal 31 connected to the odd-numbered switching elements M ₁ , M ₃ . . . M _n/2-1 . In addition, the signals at the connection point of FETQ _b1 and Q _b2 and the connection point of Q _b2 and Q _b3 that constitute CTD ₃ are supplied to the gates of FETQ _b and Q _b ', respectively, so that a signal as shown in Fig. 6 K is generated. taken out. This signal is supplied to an output terminal 32 connected to even-numbered switching elements M ₂ , M ₄ . . . Mm/2.

In this way, the delay circuits 11 and 14 and the switches 12 and 13 can be constructed.

Note that in the present invention, as described above, the lines L ₁ to L _n are
It is not limited to grouping each book. For example, if there are three shift registers, the number of stages of the shift register 2 will be reduced to 1/3, and the power consumption will be reduced to 1/9.

Note that the present invention is not limited to the above-described image display device, but can also be applied to a two-dimensional address storage device and the like.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining a conventional device, FIG. 3 is a configuration diagram of an example of the present invention, and FIGS. 4 to 6 are diagrams for explaining the same. 1 is the input terminal, 2 is the shift register, 11,1
4 is a delay circuit, and 12 and 13 are switches.

Claims (1)

[Claims] 1 A plurality of first signal lines provided in parallel to the vertical scanning direction, a plurality of second signal lines provided in parallel to the horizontal scanning direction, and a plurality of second signal lines provided in parallel to the horizontal scanning direction. a first scanning means that sequentially generates one switch signal; a plurality of switch means that are sequentially driven by the first switch signal and sequentially supply input video signals to the first signal line; a second scanning means for sequentially supplying a second switch signal according to vertical scanning to the second signal line; and a second scanning means arranged in a matrix at each intersection of the first and second signal lines; a circuit element driven by the second switch signal supplied to the second signal line and supplied with the input video signal via the first signal line, The first signal line and the corresponding switch means are divided into groups of N lines for the first signal line, and the corresponding relative delay amount between the input video signal and the adjacent first signal line is determined from each other. and sequentially switching the input video signals from each of the first signal delay means to form N input video signals whose time axis has been expanded N times. , supplying the formed signal to N second signal delay means each having the above-mentioned relative delay amount so that the formed signal is taken out from each of the second signal delay means at the same timing; This extracted signal is supplied to each of the first signal lines of the same order in each of the groups, and the switch means is driven for each group by the first switch signal, thereby A two-dimensional addressing device characterized in that the input video signal is supplied to each of the first signal lines at the same timing.