JPS58199391A - Liquid crystal matrix driver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving device for a liquid crystal matrix display device.
In particular, the present invention relates to a drive method suitable for active drive using active elements.

The basic principle of the active matrix drive method, which drives individual liquid crystal pixels in a matrix using active GB resistors, is the RC
The application has been filed by Company A.

(Japanese Patent Publication No. 48-28117) On the other hand, many specific application examples have been filed, and the representative example is JP-A No. 55-159493.
Explain.

FIG. 1 shows an overall configuration diagram of the drive circuit. Each display element a is composed of a MOS transistor, a storage capacitor 8, and a liquid crystal pixel 9. Furthermore, the MOS transistors and the MOS transistors are connected through the entire source line 14.

horizontal shift register 4 and vertical shift register 5r; t,
MOS) Turn on transistor and Mos transistor 7
Or generate a signal to set the OFI' state.

These signals are then applied to each MO8) transistor through gate signal lines 12 and 13.

- 10,000, the timing signal generation circuit 3 adds CKH, 8TH, and CKV to the horizontal and vertical shift registers.

Generate STY and M signal to be applied to polarity selection circuit 2 -r'
Ru. , fit1, the polarity selection circuit 2 is a liquid crystal 1It
In this book, the polarity of the video signal is switched every %l field in order to drive the II cable 9 with variable current. In this circuit,
A signal whose polarity has been inverted by the polarity inversion circuit 1 and the original signal are added. Note that 10 is a common-pole terminal, and a constant value of 1 is added.

Next, the operation of these circuits will be explained using the timing diagram shown in FIG.

S'l'V1g signal and CKV signal, MOS) This is a timing signal for sequentially turning on the Langstaff line by line.
) The number of pulses of the CKV signal is the number of gate lines 13 (
m).

On the other hand, the CKH signal and the STH signal are timing signals that sequentially turn on the MOS transistor 6. Therefore, the number of pulses of the CKH signal within one horizontal scanning period is equal to the number (n) of gate lines 12.

For example, Gate 41i! If the 1st line is selected among 13, the 1st line MOS connected to this
) All the Ranjistaffs are turned on, and on the other hand, the MOS transistors 6 are sequentially turned on at the timing of the CKH signal, and the bidet No. 1g is applied to the storage capacitor 8 and the liquid crystal pixel 9 in a time-sharing manner.

The series of operations described above is repeated for each field (1/608).

Therefore, the voltage applied to the liquid crystal -'a9 is shown in FIG. 3. The voltage applied to one liquid crystal 1III element has a waveform whose polarity is inverted every field. At this time, in the non-selected state, the voltage attenuates mainly with a time constant defined by the storage capacitor 8, the capacitor CLc of the liquid crystal 1-, and the resistor LC of the liquid crystal layer.

By the way, to increase the contrast of the display by increasing the effective voltage applied to the liquid crystal pixels using Ken's method,
There are three methods: increasing the capacitance of the storage capacitor 8, decreasing the leakage current of the liquid crystal, or increasing the charging voltage. Among these, increasing the storage capacitor 8 and the pledged voltage requires time in the IC process and is disadvantageous in terms of yield. Furthermore, in order to reduce liquid crystal leakage, it is necessary to reduce the amount of impurities contained in the liquid crystal, which poses a problem during mass production.

The purpose of the present invention is to provide a drive that achieves high contrast by increasing the effective value of the '-pressure applied to the liquid crystal AIII element of a display device that drives a display signal input at a predetermined period, such as a video signal, in an active matrix manner. There is a method to provide.

The present invention is characterized by the fact that one voltage applied to a liquid crystal pixel attenuates with almost the same time constant regardless of voltage conditions.
LCD iiil below the video signal period! The reason is that a voltage is written to the element, substantially increasing the effective voltage and increasing the display contrast.

The present invention will be explained in detail below. FIG. 4 shows an example of the configuration of the present invention. Each display) storage capacitor 23, liquid crystal pixel 22, and MOS) transistor 2
Consists of 1. Among these, one terminal 24ij of the liquid crystal element 22 is set to a common potential. Each MO8) transistor 2
The source of transistor 1 is connected to the drain terminal of MOS transistor 18 by source line 19 . The source of MOB) transistor 18 is connected to the video signal line 25 by 4d, and gradation No. 18 is added.

- 10,000, the vertical shift register 16 performs a scanning No. 15 in which the MOS transistors 21 are sequentially turned on for each line;
~Ll· is generated and passed through the gate line 20 [7, to control each M08 transistor. Also, horizontal 7 foot register 15
generates sampling signals C1 to CI that sequentially turn on the MOS transistors 18, and passes them through the gate line 17 to control each MOS transistor.

Further, the source video signal is converted into a digital signal No. 16 by an analog/digital f/f circuit (hereinafter abbreviated as A/D1g circuit) 30, and inputted to a buffer register 29. d in this buffer register 290 is a digital
The signal is again converted into an analog signal by an analog conversion circuit (hereinafter abbreviated as F113/A circuit) 2B.

The source video signal and the output signal of the D/AIgl path (via No. 1a@) are appropriately selected A by the selection switch circuit 27, and the selection switch 25 is applied to the polarity inversion circuit 26 and the selection switch 25. )Ran resistor 1
The polarity of the video signal applied to the source No. 8 is switched for each field.

Further, a timing circuit 311j generates timing signals for each circuit section.

Here, FIG. 5 shows the operation of the circuit shown in FIG. 4.

This will be explained using FIG. 6 as an example. Of these, in Figure 46, the liquid crystal screen is divided into two blocks, A and B, and the A block is
The liquid crystal pixels are numbered 1 to 0 in the horizontal direction and l-j/2 in the vertical direction, and the B block is similarly numbered 1 to J1 in the horizontal direction and j/2+1 to J in the vertical direction. It is.

10, FIG. 5 shows a buffer register that stores information for one block of pixels shown in FIG. (Then, the buds of the register are set to 1 to 0 in the horizontal direction and 1 to P in the vertical direction, and the display information of one liquid crystal pixel is stored at each address.For example, the A/Dim path 30 shown in FIG. When converting a video signal into a 4-bit digital signal, the video signal refined into 4 lots is stored in each address of the buffer register.

Next, in order to explain in detail the operation of loading data into 8 screens A, it is assumed that display information for 8 screens is stored in the buffer register. In this case, the contents of the output register are the second half of one field (:1/2 field) of the video signal.
is memorized.

First, the selection switch circuit 27 selects the source video signal,
Directly write to pixels l, t (from now on, displayed as C1, 1 - "ru...") on screen A. When the above operation is completed, the selection switch circuit 27 selects 4 of the A/D circuits 28, The video signal converted into an analog quantity is written to e1/l''l+1 of the 8th screen. When this is finished, ml,, ell
, write @.

/XK, A111iii [e, 1. , writes the contents of In1st to .

I/! After this, information of eI+1 is written to m, , t. These series of operations are performed until e, /, □, I and e J, l. As a result, the contents of the buffer register are changed to Am
The display information of the t-plane is stored. This corresponds to the video signal of the first half (1/2 field) of one field.

Next, write the source video signal directly to C1/11 II on the B-side. When this is finished, C2 on the A screen.

The contents of buffer registers m, , , are stored in . After this, m, 1, ej/l and 11. Pledge the displayed information.

Next, ej/'161*! Directly write the source video signal to el*t, m5. , the contents of t-. So, m7. , the display information of eJ/*+t +t is pledged to .

These series of operations are ej/'l + l + ej
Continue until +1. As a result, the buffer register contains
8 screens.

Display information of eI/l, 1+I to ej+1 is stored. This corresponds to the video signal of the latter half of one field (l/2 field).

The operations described above are performed for each field. Figure 7 shows the situation at that time.

For example, when directly writing the first half of one field signal of the source video signal to the Auli surface, the contents of the buffer register are written to the Budu surface. Also, when entering the second half of one field signal of the source video signal on the 8g plane,
Insert the contents of the buffer register into the 11411th plane.

At this time, the selection switch circuit 25 switches the polarity of video No. 16 for each field.

Figure 48 is an enlarged view of a portion of Figure la7.

1. Time is the time when one MOS) transistor 18 is selected. For example, in the first half of the 11th hour, e on screen A
Video signals are written to e1/l and 1+1 of the 8 screens in the latter half.

FIG. 9 shows the timing of the signals shown in item 4-. 8TV in vertical shift register.

In addition to the CK V signal, a scanning signal ~Lj is generated, and N
The 10S transistor 21 is turned on for each line. In this SM example, since the liquid crystal pixel is divided into two,
L, and L7. , (where n==l, 2...j/
2) Since t; has the same timing, the gate lines 20 of each block can be commonly connected.

The M signal is a timing signal whose polarity is inverted for every field of the video signal.

Further, the old numbers 8TH and CKH are added to the horizontal shift register to generate sampling signals 01 to Crt, and the MOS transistor 18 is turned on.

At this time, the video signal is switched using SL1g. Further, the video signal digitally subjected to &A by the A/D circuit is written into the buffer register at the falling timing of the SL multiplied signal.

As a result of the above, the i pressure O1 type applied to the liquid crystal pixel 22 is the 10th
It will look like the figure. At 'a,'d*L, the source video signal is directly applied to the liquid crystal pixel.Also, at t,.

At t, the video signal stored in the buffer register is applied to the liquid crystal pixels. Note that even if the voltage level of the source video signal manually input to the circuit of this embodiment is constant, the voltage level at each time is not strictly constant, but this does not pose a practical problem.

Figures 11 and 12 show other 'jl! This is an example. Here, the screen is divided into four screens, kA, B, C, and D, and the buffer register? It was divided into three blocks: 1, 2, and 3.

The buffer register stores display information for the 3/4@ side. Therefore, o=凰 and p=-J.

Figure 13 shows the timing of entering screens A, B, C, and D. First, if the source video r= is directly written on the A screen, the video signal flit stored in the buffer register is written on the B, C, D screens.

In this case, the writing on each screen is 11. g9 Figure VC shows 1. It is done in time division within the time.

rc, Am+4 video signal t buffer register i
The video signals of the A, C, and D screens are stored in the buffer register in 44,' s time.This process is repeated sequentially.

The video signals stored in each block of the buffer register are shown in FIG. 14. tl
+ "!...It is the same as 11.1... in Figure 413. In other words, when 1/4 field of the video signal is processed, the video signal tube is directly read into the liquid crystal pixel, and the rest is During the 3/4 field time, the video signal stored in the buffer register is received.

The m15 diagram shows the voltage waveform applied to the liquid crystal pixel. In "ah'@e'l, the source video signal is written directly, and in 'kl'@,'4+t11"wJ"h, the video signal stored in the buffer register is written.

In this way, by writing multiple times within one field time of the video signal, the effective value of the voltage applied to the liquid crystal pixel can be increased.

Furthermore, in order to achieve the same effect as this embodiment, it is possible to divide the display screen into N parts and provide a buffer register for storing the display information of the N-1 screen.

Furthermore, in this embodiment, it is assumed that the video signal is input as an analog signal, but when it is input as a digital signal,
A similar effect can be obtained by using two D/A circuits 28 as shown in FIG.

According to the present invention, since the effective voltage applied to the liquid crystal pixels can be increased, the display contrast can be increased.

Furthermore, since the storage capacitor connected in parallel with the liquid crystal pixels can be made smaller, the area required for this can be made smaller, and a smaller display with a limited display screen can be realized.

Furthermore, since the voltage applied to the liquid crystal pixel can be lowered, the resistance l:E of the semiconductor can be lowered, making it easier to integrate into an LSI.

[Brief explanation of the drawing]

Figure 11 is a conventional circuit block diagram, Figure 2 is a timing diagram of Figure 1, and Figure 3 is #L instead of JJO for the liquid crystal pixel in Figure 1.
Voltage waveform diagram Figure 4 shows the block-5 of the circuit of the present invention. Figure 5 shows the addressed FF side control of the buffer register. Figure 6 shows the divided side control of the display screen. Figures 7 and 8 show the display screen. The writing timing diagram of Figure 9 is the timing diagram of Figure 4, and Figure 10 is the timing diagram of Figure 4.
The figure is a voltage waveform diagram for liquid crystal pixels, Figure 11 is a side control of buffer register addressing according to another embodiment, Figure 12 is a display screen division side control, and Figure 13 is a hook for a display screen. Timing diagram J! FIG. 14 is a diagram of the contents of the buffer register, FIG. 15 is a voltage waveform diagram applied to a liquid crystal pixel, and FIG. 16 is a diagram of a circuit configuration according to another embodiment. 15...Horizontal shift register, 16...Vertical shift register, 18.21...MOS transistor, 22
...Liquid crystal mp, 23...Storage capacitor, 2
7... Selection switch circuit, 28... D/A circuit, 2
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figure

Claims (1)

[Claims] 1. At least an active element for switching input pressure and a liquid crystal I [iI
Display elements (t) arranged in a matrix in the X-Y direction and configured to apply display signals to the liquid crystal pixels in a time-division manner Display 16 entered in
1. A liquid crystal matrix driving device, characterized in that the display signal is applied to the liquid crystal pixels at a cycle equal to or less than a period of 1.