JPH02143462A - Thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a TFT with high gate breakdown strength by forming a gate electrode on a substrate, and flatly forming a semiconductor thin film on the gate electrode. CONSTITUTION:A gate electrode 14 is formed on an SiO2 film 11; via a gate insulating film 13, a poly Si thin film 12 is laminated so as to be smaller than the electrode 14; the poly Si thin film 12 is covered with an interlayer insulating film 22; windows 22, 23 are selectively opened, Al wirings 24, 25 are formed, and connected with a source.drain region 16, 17. By this constitution, the gate insulating film 13 can be almost flatly formed, so that, in the gate insulating film 13, electric field concentration is not present between the source.drain region 16, 17 and the gate electrode 14. Since the gate electrode 14 is formed on the lower layer of the semiconductor thin film, each gate electrode can be formed in the same layer, when a TFT is formed in the same chip as a bulk transistor, thereby reducing the processes.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to an FJ'R' in which a semiconductor thin film is formed on the upper layer of a substrate, and a channel region is provided in this semiconductor thin film.
This relates to the A transistor.

[Summary of the invention]

The present invention provides a thin film transistor as described above, by forming a substantially flat semiconductor thin film over a gate electrode formed on a substrate. Broadly speaking, those shown in FIGS. 4 and 5 are conventionally known.

FIG. 4 shows a first conventional example which is also described in Japanese Unexamined Patent Publication No. 61-65476. In this first conventional example, a polycrystalline Si thin film 12 is formed on a SiO□ substrate ll, and this polycrystalline Si thin film 12 is covered with a gate oxide film 13.

A gate electrode 14 is formed on the gate oxide film 13 and is made of polycrystalline Si! A portion of the film 12 below the gate electrode 14 is a channel region 15, and both sides thereof are source/drain regions 16 and 17.

FIG. 5 shows a second conventional example. In this second conventional example, a gate electrode 14 is formed on a SiO□ substrate 11, and this gate electrode 14 is covered with a gate oxide film 13.

The polycrystalline Si thin film 12 is formed so as to straddle the gate electrode 14, and the part of the polycrystalline Si film 12 above the gate electrode 14 is the channel region 15, and both sides thereof are the source region.
These are drain regions 16 and 17.

[Problem to be solved by the invention]

However, in the first conventional example shown in FIG.
It is necessary to first form the polycrystalline 5II film 12 on the plate 11, and then form the gate electrode 14.

For this reason, when forming a thin film transistor on the same chip as a bulk transistor, each gate electrode cannot be formed in the same layer, which increases the number of manufacturing steps.

On the other hand, in the second conventional example shown in FIG.
Since there is a stepped portion in the gate oxide film 13 between the polycrystalline Si thin film 12 and the polycrystalline Si thin film 12, the electric field between the source/drain region 16, 17 and the gate electrode 14 is concentrated on this stepped portion, and the first The gate breakdown voltage is lower than that of the conventional example.

[Means to solve the problem]

The thin film transistor according to the present invention includes a gate electrode 14 formed on a substrate 11 and a semiconductor thin film 12 formed substantially flat above the gate electrode 14.

[Effect]

In the thin film transistor according to the present invention, since the semiconductor thin film 12 is formed substantially flat on the upper layer of the gate electrode 14,
The gate insulating film 13 between the gate electrode 14 and the semiconductor thin film 12 can also be formed substantially flat. Therefore, in the gate insulating film 13, the source/drain regions 16.1
There is no electric field concentration between 7 and the gate electrode 14.

Further, since the gate electrode 14 is formed in the lower layer of the semiconductor heavy IJ 12, each gate electrode can be formed in the same layer when a thin film transistor is formed on the same chip as a bulk transistor.

〔Example〕

Hereinafter, first and second embodiments of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a first embodiment. In this first embodiment, as is clear from FIGS. 1A and 1B, a gate electrode 14 having a larger area than the polycrystalline sine film 12 that will be formed later is formed on the SiO□ substrate 11. A polycrystalline Si thin film 12 is formed on the gate electrode 14 with an oxide film 13 in between.

The polycrystalline Si thin film 12 is covered with an interlayer insulating film 21,
A1 wirings 24 and 25 are connected to source and drain regions 16 and 17 through a plurality of contact windows 22 and 23 formed in this interlayer insulating film 21, respectively.

Further, a contact window 26 for the channel region 15 is also formed in the glabella insulating film 21, and an Aβ wiring 27 for fixing the channel region 15 to a constant potential is also connected thereto. Note that wiring for the gate electrode 14 is provided on the SiO□ substrate 11.

In this first embodiment, unlike the first and second conventional examples described above, the gate electrode 14 and the source/drain regions 16.1
7 are superimposed. However, for example, if the area of the source/drain regions 16 and 17 is 20 μm×50 μm and the thickness of the gate oxide film 13 is 600, the capacitance between them is 1 pF or less.

For example, in a high voltage transistor for driving a fluorescent display tube, if the above-mentioned capacitance is up to about nF, the operation will not be affected. Therefore, the first embodiment can be applied to such high breakdown voltage transistors for driving fluorescent display tubes.

FIG. 2 shows a second embodiment. In this second embodiment, an interlayer SiO□ film 28 having a thickness that is the same as that of the gate electrode 14 is formed on the SiO□ substrate 11.
This embodiment has substantially the same structure as the first embodiment described above, except that the polycrystalline Si thin film 12 is formed substantially flat on the upper gate oxide film 13 and the interlayer 5iOz film 28. There is.

In order to manufacture such a second embodiment, as shown in FIG. 3A, after forming the gate electrode 14, an interlayer SiO□ film 28 is formed.
is deposited by CVD or the like to a thickness equal to or greater than that of the gate electrode 14, and then a photoresist 29 is applied substantially evenly.

Next, under the condition that the photoresist 29 and the interlayer SiO□ film 28 have approximately the same etching rate, the photoresist 29 and the interlayer SiO□ film 28 are etched until the gate electrode 14 is exposed as shown in FIG. 3B. Perform RIE.

In this state, the surface of the polycrystalline Si layer constituting the gate electrode 14 is thermally oxidized to form S as shown in FIG. 3C.
A gate oxide film 13 made of iO□ is formed.

Thereafter, the polycrystalline Si thin film 1
2. Source/drain region 16.17, interlayer insulating film 21
, contact windows 22, 23, Al interconnects 24, 25, etc. are formed.

〔Effect of the invention〕

In the thin film transistor according to the present invention, there is no electric field concentration between the source/drain region and the gate electrode in the gate insulating film, so the gate breakdown voltage is high.

Further, when a thin film transistor is formed on the same chip as a bulk transistor, each gate electrode can be formed in the same layer, so that the number of manufacturing steps can be reduced.

[Brief explanation of the drawing]

Fig. 1A shows a first embodiment of the present invention; Fig. 1B is a side sectional view taken along line A-A in Fig. 1B, Fig. 1B is a plan view of the first embodiment, and Fig. 2 is a cross-sectional view of the second embodiment. FIG. 3 is a side sectional view sequentially showing the manufacturing process of the second embodiment. FIGS. 4 and 5 are side sectional views of first and second conventional examples of the present invention, respectively. In addition, in the symbols used in the drawings, 11--------------5iO□ substrate 12
・・−・−−−−−−−−−−−−・Polycrystalline Si thin 1
This is a simulated gate electrode.

Claims (1)

[Scope of Claims] A thin film transistor comprising a gate electrode formed on a substrate and a semiconductor thin film formed substantially flat above the gate electrode.