JPH01500390A - Improvements in transistors - Google Patents
Improvements in transistorsInfo
- Publication number
- JPH01500390A JPH01500390A JP62502842A JP50284287A JPH01500390A JP H01500390 A JPH01500390 A JP H01500390A JP 62502842 A JP62502842 A JP 62502842A JP 50284287 A JP50284287 A JP 50284287A JP H01500390 A JPH01500390 A JP H01500390A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- gate
- drain regions
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000003870 refractory metal Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 トランジスタの改良 この発明はトランジスタの生産工程に関し、特にサブミクロンＣＭＯＳトランジ スタのソースおよびドレインに適した浅いｐ＋およびｎ＋ドープ処理層の組立て に関する。[Detailed description of the invention] Improvements in transistors This invention relates to the production process of transistors, particularly submicron CMOS transistors. Fabrication of shallow p+ and n+ doped layers suitable for source and drain of star Regarding.
かかるトランジスタの浅い接合は極めて高い抵抗を有し、本発明の狙いはかかる 接合における抵抗を減少させることである。The shallow junctions of such transistors have extremely high resistance, and the aim of the present invention is to The goal is to reduce the resistance at the junction.
本発明により、適当な基板の上に置かれたフィールド酸化物分離層によって囲ま れているゲート酸化物層の上にポリシリコンの層を貼り二ゲート電極を形成する ようにゲート酸化物の上にあるポリシリコン層の選択された領域内でポリシリコ ン層にレジスト層を貼り：ソースおよびドレイン領域を形成するようにイオン注 入を選択し、前記注入はゲート酸化物層を経て前記レジスト層によりマスクされ た領域内を除く制限された範囲までわたり；前記酸化物層から伸びるゲート電極 を残すようにポリシリコン層およびレジスト層を腐食させ：ソースおよびドレイ ン領域を活性化して前記領内のゲート酸化物を除去し；そして最後に前記ゲート 電極およびソースならびにドレイン領域の上に導電層をデポジットする、ことを 含むトランジスタの生産工程が提供される。According to the present invention, a field oxide isolation layer placed on a suitable substrate surrounds the A layer of polysilicon is applied on top of the gate oxide layer to form two gate electrodes. Polysilicon in selected areas of the polysilicon layer overlying the gate oxide to Apply a resist layer to the top layer: Ion implantation is applied to form the source and drain regions. the implant is masked by the resist layer through the gate oxide layer. a gate electrode extending from said oxide layer; Erodes the polysilicon layer and resist layer to leave: source and drain activating the gate region and removing the gate oxide in said region; and finally depositing a conductive layer over the electrode and source and drain regions; A manufacturing process for a transistor including the present invention is provided.
特表昭６４−５ｏｏａ９ｏ （２） ゲート電極を形成する前にポリシリコン層への注入によってソースおよびドレイ ン領域を作るドープ処理局の形成によって、サブミクロンＣＭＯＳトランジスタ のソースおよびドレイン領域に適した浅いｐ＋ならびにｎ＋ドープ処理層を得る ことができる。しかし本発明による工程は、例えばバイポーラ・トランジスタの 生産といったような他の領域にも使用される。Special edition Showa 64-5ooa9o (2) The source and drain electrodes are implanted into the polysilicon layer before forming the gate electrode. Submicron CMOS transistors are Obtain shallow p+ and n+ doped layers suitable for source and drain regions of be able to. However, the process according to the invention is useful for e.g. bipolar transistors. It is also used in other areas such as production.
ソースおよびドレイン領域は、ゲート電極を形成するようにポリシリコン層を腐 食させる前に活性化することができるが、ポリシリコン層が腐食された後でかつ ゲート酸化物層がソースおよびドレイン領域で除去される前に、前記領域を活性 化させることが望ましい。しかしもう１つの別法のように、ソースおよびドレイ ン領域内のドープ材料層の活性化は、ポリシリコンの腐食ならびにゲート酸化物 層の除去後に起こることがある。The source and drain regions are etched into the polysilicon layer to form the gate electrode. It can be activated before etching, but it can be activated after the polysilicon layer has been etched. Activate the source and drain regions before the gate oxide layer is removed in the source and drain regions. It is desirable that the But as another alternative, source and drain Activation of the doped material layer in the gate region is caused by polysilicon corrosion as well as gate oxide This may occur after layer removal.
最終導電層はケイ化物または選択性耐火金属デポジション、例えば選択性タング ステンを含むことがある。The final conductive layer is a silicide or selective refractory metal deposition, e.g. selective tungsten. May contain stainless steel.
本発明は上述の工程で作られたときのトランジスタにも広がる。The invention also extends to transistors produced by the above-described process.
本発明を図面に関して例としてこれから詳しく説明するが、図面は本発明による トランジスタの生産の連続段階を示す。The invention will now be described in detail by way of example with reference to the drawings, which show that the invention is in accordance with the invention. The successive stages of transistor production are shown.
第１図は本発明による工程の初期段階を示し：第２図は基板に浅いソースおよび ドレイン電極を形成する選択性イオン注入の段階を示し： 第３図はポリシリコン層を腐食した後のトランジスタを示し： 第４図はソースおよびドレイン領域の活性化後のトランジスタを示し： 第５図は本発明による工程によって作られた完成品のトランジスタを示す。FIG. 1 shows the initial stage of the process according to the invention; FIG. 2 shows a shallow source and Showing the steps of selective ion implantation to form the drain electrode: Figure 3 shows the transistor after etching the polysilicon layer: Figure 4 shows the transistor after activation of the source and drain regions: FIG. 5 shows a finished transistor made by the process according to the invention.
図面から、ポリシリコン層１は適当な基板４の上に置かれたフィールド酸化物分 離１ｉｉ３によって囲まれているゲート酸化物１！２の上に貼られている。レジ スト１ｌ１５は、第１図に示されるようなゲート′Ｉｉ極を形成するゲート酸化 物層１２の上にあるポリシリコン１１１に貼られている。From the drawing, it can be seen that the polysilicon layer 1 is a field oxide layer placed on a suitable substrate 4. It is pasted on top of the gate oxide 1!2 which is surrounded by an isolation 1ii3. cash register The gate oxide layer 1115 forms the gate 'Ii electrode as shown in FIG. It is attached to polysilicon 111 on top of material layer 12.
次に選択性ｎ形またはｐ形イオン注入が第２図に示される通り行われ、レジスト 層５はマスクとして作用するので酸化物層２の下にある基板の選択された領域の みが注入されてＮＭＯ８またはＰＭＯＳトランジスタのソースおよびドレイン領 域が作られる。注入材６および７はデバイスの活性区域をちょうど貫通する。A selective n-type or p-type ion implantation is then performed as shown in FIG. Layer 5 acts as a mask so that selected areas of the substrate below oxide layer 2 are is implanted into the source and drain regions of NMO8 or PMOS transistors. area is created. Injectants 6 and 7 just pass through the active area of the device.
次にポリシリコンＩ１１は、レジスト層５の下にある領域を除き腐食され、その 後レジスト層は第３図に示される通りポリシリコン・ゲート８を残して除去され る。ソースおよびドレイン領域６ならびに７が次に活性化されて、約０．１μｍ の接合深さまで拡散され、第４図に示される構造物が作られる。The polysilicon I11 is then corroded except for the area under the resist layer 5. The resist layer is then removed leaving behind the polysilicon gate 8 as shown in FIG. Ru. Source and drain regions 6 and 7 are then activated to approximately 0.1 μm The structure shown in FIG. 4 is produced.
最後に、ソースおよびドレイン領域でゲート酸化物層２が除去されてゲート側壁 酸化物フィレット９が作られ、その後ケイ化物層１０がゲート領域８、ソース領 域６、およびドレイン領域７に貼られ、第５図に示される通り層のシート抵抗を 約８Ω／口以下に減少させる。Finally, the gate oxide layer 2 is removed in the source and drain regions to remove the gate sidewalls. An oxide fillet 9 is created and then a silicide layer 10 is applied to the gate region 8, source region 6 and drain region 7 to increase the sheet resistance of the layer as shown in FIG. Reduce the resistance to approximately 8Ω/mouth or less.
本発明による工程は小形（ゲート長さ１μｍ以下）のＣＭＯＳトランジスタに適 しているが、例えばバイポーラ・トランジスタにも適すると思われる。ゲート電 極を形成する前のソースおよびドレインの注入は、極めて浅い拡散の形成を可能 にする。The process according to the present invention is suitable for small-sized (gate length 1 μm or less) CMOS transistors. However, it may also be suitable for bipolar transistors, for example. gate electric Source and drain implants before pole formation allows formation of extremely shallow diffusions Make it.
本発明は上記の例に制限されず、発明の範囲から逸脱せずに変化および変形が可 能である０例えば、ソースおよびドレイン領域６ならびに７はポリシリコン層１ およびレジスト層５を腐食する前に活性化することができる（第３図）が、これ は望ましくない、もう１つの別法として、ソースおよびドレイン領域６ならびに ７はゲート酸化層２がこれらの領域から除去された後で活性化することができる 。The invention is not limited to the examples described above, but may be modified and modified without departing from the scope of the invention. For example, the source and drain regions 6 and 7 are formed on the polysilicon layer 1. and can be activated before corroding the resist layer 5 (Fig. 3), but this Another alternative is that source and drain regions 6 and 7 can be activated after the gate oxide layer 2 is removed from these areas .
ケイ化物１０はポリシリコンまたは任意な他の適当な１１ｆｆｉ層を含むことが ある。別法として、ケイ化物は選択性耐火金属デポジション、例えば選択性タン グステンによって置き替えることができる。Silicide 10 may include polysilicon or any other suitable 11ffi layer. be. Alternatively, silicides can be used for selective refractory metal deposition, e.g. Can be replaced by Gusten.
Ｆｔｒｓ、５゜ 手続補正書（０引 昭和６３年２月１２日Ftrs, 5° Procedural amendment (0 quotation) February 12, 1986
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8611580 | 1986-05-12 | ||
| GB8611580A GB2190790B (en) | 1986-05-12 | 1986-05-12 | Improvements in transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01500390A true JPH01500390A (en) | 1989-02-09 |
| JP2758163B2 JP2758163B2 (en) | 1998-05-28 |
Family
ID=10597752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62502842A Expired - Fee Related JP2758163B2 (en) | 1986-05-12 | 1987-05-11 | Submicron transistor manufacturing method |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4833097A (en) |
| EP (1) | EP0270562B1 (en) |
| JP (1) | JP2758163B2 (en) |
| DE (1) | DE3782146T2 (en) |
| GB (1) | GB2190790B (en) |
| WO (1) | WO1987007084A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2172427A (en) * | 1985-03-13 | 1986-09-17 | Philips Electronic Associated | Semiconductor device manufacture using a deflected ion beam |
| JPH0758701B2 (en) * | 1989-06-08 | 1995-06-21 | 株式会社東芝 | Method for manufacturing semiconductor device |
| KR100189964B1 (en) * | 1994-05-16 | 1999-06-01 | 윤종용 | High voltage transistor and method of manufacturing the same |
| DE4417916A1 (en) * | 1994-05-24 | 1995-11-30 | Telefunken Microelectron | Method of manufacturing a bipolar transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4736984U (en) * | 1971-04-03 | 1972-12-23 | ||
| JPS54879A (en) * | 1977-06-03 | 1979-01-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of mis transistor |
| JPS6154669A (en) * | 1984-08-27 | 1986-03-18 | Hitachi Ltd | Mos type field-effect transistor and manufacture thereof |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3873373A (en) * | 1972-07-06 | 1975-03-25 | Bryan H Hill | Fabrication of a semiconductor device |
| US4026733A (en) * | 1975-10-29 | 1977-05-31 | Intel Corporation | Process for defining polycrystalline silicon patterns |
| JPS54140483A (en) * | 1978-04-21 | 1979-10-31 | Nec Corp | Semiconductor device |
| JPS55107229A (en) * | 1979-02-08 | 1980-08-16 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of manufacturing semiconductor device |
| NL7902878A (en) * | 1979-04-12 | 1980-10-14 | Philips Nv | Semiconductor prodn. method using etched layers - obtaining silicon-oxide layer by thermal oxidation following ion implantation in non-oxidised layers |
| JPS5621367A (en) * | 1979-07-27 | 1981-02-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5648174A (en) * | 1979-09-28 | 1981-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device and its preparation |
| JPS57130417A (en) * | 1981-02-05 | 1982-08-12 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS57204170A (en) * | 1981-06-10 | 1982-12-14 | Fujitsu Ltd | Manufacture of mos type field effect transistor |
| JPS59188974A (en) * | 1983-04-11 | 1984-10-26 | Nec Corp | Manufacture of semiconductor device |
| JPS6177364A (en) * | 1984-09-25 | 1986-04-19 | Oki Electric Ind Co Ltd | Semiconductor ic device |
| US4728617A (en) * | 1986-11-04 | 1988-03-01 | Intel Corporation | Method of fabricating a MOSFET with graded source and drain regions |
-
1986
- 1986-05-12 GB GB8611580A patent/GB2190790B/en not_active Expired
-
1987
- 1987-05-11 WO PCT/GB1987/000314 patent/WO1987007084A1/en active IP Right Grant
- 1987-05-11 JP JP62502842A patent/JP2758163B2/en not_active Expired - Fee Related
- 1987-05-11 US US07/150,410 patent/US4833097A/en not_active Expired - Lifetime
- 1987-05-11 DE DE8787902661T patent/DE3782146T2/en not_active Expired - Lifetime
- 1987-05-11 EP EP87902661A patent/EP0270562B1/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4736984U (en) * | 1971-04-03 | 1972-12-23 | ||
| JPS54879A (en) * | 1977-06-03 | 1979-01-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of mis transistor |
| JPS6154669A (en) * | 1984-08-27 | 1986-03-18 | Hitachi Ltd | Mos type field-effect transistor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0270562A1 (en) | 1988-06-15 |
| JP2758163B2 (en) | 1998-05-28 |
| DE3782146D1 (en) | 1992-11-12 |
| DE3782146T2 (en) | 1993-04-29 |
| US4833097A (en) | 1989-05-23 |
| GB2190790B (en) | 1989-12-13 |
| GB2190790A (en) | 1987-11-25 |
| EP0270562B1 (en) | 1992-10-07 |
| WO1987007084A1 (en) | 1987-11-19 |
| GB8611580D0 (en) | 1986-06-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |