JP3147374B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, and is used, for example, for an SOI device formed on an insulator by direct wafer bonding.

[Conventional technology]

Conventionally, it was formed on insulator by ware direct bonding
SOI (Silicon On I)
In some devices, a wiring layer of doped polysilicon is formed below the SOI layer.
This wiring layer is in contact with the SOI substrate via the SOI substrate contact, and is used for the back side gate, the shield layer, and the SOI substrate electrode.

[Problems to be solved by the invention]

However, in the conventional device described above, the wiring layer is SOI
When used for substrate electrodes, impurities (for example, boron) in doped polysilicon may diffuse from the SOI substrate contact into the SOI substrate due to a process after the formation of the wiring layer (for example, a heat treatment process).

At this time, for example, when the SOI device is a thin film or a short channel, the impurity diffusion from the doped polysilicon reaches the channel region of the SOI region, and further reaches the source region or the drain region. This causes a problem that the device characteristics are remarkably deteriorated.

Therefore, the present invention has been made in view of the above problems, and when a wiring layer containing impurities is set in an element formation region, a semiconductor formed in the element formation region due to impurities in the wiring layer It is an object of the present invention to provide a semiconductor device capable of suppressing adverse effects on element characteristics.

[Means for solving the problem]

Therefore, the present invention relates to an element forming region in which a MOS transistor is formed as a semiconductor element, and a predetermined portion of the element forming region.
A wiring layer that is wired so as to take a substrate contact of the MOS transistor, wherein the wiring layer is made of a material containing impurities,
In addition, the impurity concentration of at least one region in contact with the predetermined portion is set to be equal to or lower than the impurity concentration of the predetermined portion of the element forming region, and the impurity concentration of other regions other than the one region is higher than the impurity concentration of the one region. A semiconductor device characterized by having a concentration is adopted.

[Action]

According to the above configuration, the wiring layer containing the impurity is wired so as to be in contact with the predetermined portion. In the wiring layer, the impurity concentration of at least one region in contact with the predetermined portion is equal to or lower than the impurity concentration of the predetermined portion of the element formation region, and the impurity concentration of other regions other than the one region is the impurity concentration in one region. It has a higher concentration.

〔The invention's effect〕

As described above, in the present invention, since the impurity concentration of the wiring layer at least in contact with the predetermined portion is formed to be lower than the impurity concentration of the predetermined portion of the element formation region, even if the heat treatment is performed after the formation of the wiring layer. Since the impurity concentration is lower than a predetermined portion of the element formation region, the impurity does not diffuse into the element formation region.

Therefore, there is an excellent effect that the impurity-containing wiring layer can be set in the element formation region without adversely affecting the characteristics of the semiconductor element formed in the element formation region.

〔Example〕

 Hereinafter, the present invention will be described based on an embodiment shown in the drawings.

First Embodiment First, a first embodiment will be described.

FIG. 1 is a cross-sectional view showing a cross section of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2 (a) to 2 (h) are cross-sectional views for explaining the semiconductor device in the order of manufacturing steps. is there.

First, as shown in FIG. 2 (a), the main surface of an N-type silicon substrate 1 having a (100) crystal plane is subjected to a thermal oxidation treatment to form a silicon oxide film 2, and then silicon nitride is formed by LPCVD. The film 3 is formed.

Subsequently, portions other than the silicon oxide film 2 and the silicon nitride film 3 in predetermined regions are removed by etching or the like.

Next, as shown in FIG. 8 (b), thermal oxidation is performed in an oxygen atmosphere to obtain a so-called LOCOS (Localized Oxidation of Silicon).
A silicon oxide layer 4 is formed in a region where the silicon nitride film 3 is not formed by a (silicon) oxidation method.

Next, as shown in FIG. 2 (c), the silicon nitride film 3 is removed by hot phosphoric acid or the like, then a predetermined amount of boron is ion-implanted, and heat treatment is applied to the ion-implanted layer (corresponding to an element formation region) 5. Activate and diffuse a P ^- type region.
Here, the silicon oxide layer 4 is used as a mask during ion implantation.

Further, the silicon oxide film 2 and the silicon oxide layer 4 are removed from the silicon substrate 1 by etching or the like.

Next, as shown in FIG. 2 (d), a thermal oxide film 6 having a predetermined thickness is formed, and a part of the thermal oxide film 6 is removed to form a substrate contact 7 and a wiring contact 8. .

Next, as shown in FIG. 2 (e), by the LPCVD method,
The doped polysilicon film 9 doped with boron so as to have the same impurity concentration as the ion implantation layer 5 is formed on the thermal oxide film 6.
Deposit on top.

Then, the portion where the substrate contact 7 is present is covered with a resist layer 10 and then boron ions are implanted to form a high-concentration polysilicon film 17 in the portion of the doped polysilicon film 9 where the resist layer 10 is not present. . Note that the doped polysilicon film 9 and the high-concentration polysilicon film 17 correspond to a wiring layer.

Next, as shown in FIG. 2 (f), after removing the resist layer 10, the doped polysilicon film 9 is patterned into a desired shape.

Next, as shown in FIG. 2 (g), an insulating film 11 is deposited on the doped polysilicon film 9, the high-concentration polysilicon film 17 and the thermal oxide film 6 by the CVD method, and A silicon film 12 is deposited.

Next, as shown in FIG. 2 (h), the polysilicon film 12 is flattened by mirror polishing, etching or the like. Subsequently, a silicon substrate 13 serving as a second substrate having a flattened surface and a polysilicon film 12 having a flattened surface are bonded together in an atmosphere at 400 to 1200 ° C.

Next, as shown in FIG. 1, the wafer as shown in the cross-sectional view of FIG. 2 (h) is turned upside down, and the silicon substrate 1 is thinned by rough polishing while leaving several tens μm. Subsequently, the surface is polished until the thermal oxide film 6 appears by selective polishing,
As a result, a part of the silicon substrate 1 has a separated shape.

Thereafter, through a known MOS transistor forming step, the MOS transistor 15, the Al electrode 16, and the BPSG film 18 are formed on the SOI layer.

Through the steps described above, the semiconductor device according to the first embodiment is formed as shown in the sectional view of FIG.

As shown in FIG. 1, in the semiconductor device according to the first embodiment, of the doped polysilicon film 9 and the high-concentration polysilicon film 17 serving as wiring layers, the doped polysilicon provided under the substrate contact 7 is used. Since the film 9 is formed with an impurity concentration substantially equal to the impurity concentration of the ion-implanted layer 5, the impurities of the doped polysilicon film 9 are removed by the heat treatment process performed in the bonding step or the MOS transistor forming step. Will not spread.

Second Embodiment Next, a second embodiment will be described.

FIG. 3 is a cross-sectional view showing a cross section of a semiconductor device according to a second embodiment of the present invention, and FIGS. 4 (a) to 4 (d) are cross-sectional views for explaining the semiconductor device in the order of manufacturing steps. is there. Note that the second embodiment is similar to the second embodiment in the first embodiment.
This is performed in a later step of the cross-sectional view shown in FIG.

When the step of forming the cross section as shown in FIG. 2 (e) is completed, first, as shown in FIG. 4 (a), after removing the resist layer 10, a titanium nitride film 20 is formed by LPCVD. Is deposited on the doped polysilicon film 9 and the high-concentration polysilicon film 17 with a thickness of

Thereafter, as shown in FIG. 4B, the high precision polysilicon film 17 and the titanium nitride film 16 are patterned into a desired shape by etching or the like.

Next, as shown in FIG. 4C, a tungsten film 21 is selectively formed only on the titanium nitride film 20 by a selective W-CVD method.

Next, as shown in FIG. 4D, an insulating film 11 is deposited on the tungsten film 21 and the thermal oxide film 6 by a CVD method, and a polysilicon film 12 is further deposited on the insulating film 11.

Next, the processing performed after the step of forming as shown in the cross-sectional view of FIG. 2 (h) in the first embodiment is similarly performed, and as shown in FIG. 3, the MOS transistor 1 is formed on the SOI layer.
5, an Al electrode 16 and a BPSG film 18 are formed.

Through the steps described above, the semiconductor device according to the second embodiment is formed as shown in the cross-sectional view of FIG.

Here, as shown in FIG. 3, in the semiconductor device of the second embodiment, a tungsten film 21 and a titanium nitride film 20 are newly formed in addition to the configuration of the semiconductor device of the first embodiment.

This tungsten film 21 is formed so as to reduce the electric resistance of the doped polysilicon film 9 and the high-concentration polysilicon film 17 which are wiring layers.

That is, the doped polysilicon film 9 is
Similarly to the above, since the impurity concentration is lower than that of the high-concentration polysilicon film 17, the electric resistivity of the doped polysilicon film 9 is high. Therefore, by providing the conductive tungsten film 21 around the doped polysilicon film 9 and the high-concentration polysilicon film 17, the electric resistance value of the entire wiring layer is reduced. The reason why the tungsten film 21 is formed also on the high-concentration polysilicon film 17 having a low resistivity is that the contact area between the tungsten film 21 and the high-concentration polysilicon film 17 is determined by the contact area between the tungsten film 21 and the doped polysilicon film 9. This is because an attempt is made to reduce the electric resistance value by making the contact area larger than the contact area.

Further, as shown in the cross-sectional view of FIG. 4B, the formation of the titanium nitride film 20 on the doped polysilicon film 9 and the high-concentration polysilicon film 17, which are wiring layers, is performed in the next processing step. This is to protect the doped polysilicon film 9 and the high-concentration polysilicon film 17 when the tungsten film 21 is formed.

That is, without forming the titanium nitride film 20, the selection W-
When a tungsten film is to be formed by the CVD method, tungsten silicide is formed on the doped polysilicon film 9 and the high-concentration polysilicon film 17, and the contact resistance between each polysilicon and the tungsten film 21 is high. It is because it becomes.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a cross section of a semiconductor device according to a first embodiment of the present invention. FIGS. 2 (a) to 2 (h) are views for explaining the semiconductor device according to the first embodiment in the order of manufacturing steps. FIG. 3 is a cross-sectional view showing a cross section of a semiconductor device according to a second embodiment of the present invention. FIGS. 4 (a) to 4 (d) explain the semiconductor device according to the second embodiment in the order of manufacturing steps. FIG. 5 ... Ion-implanted layer (element formation region), (9, 17) ...
A doped polysilicon film and a high-concentration polysilicon film constituting a wiring layer;

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 2-79470 (JP, A) JP 2-5544 (JP, A) JP 52-109883 (JP, A) JP 62-79 244147 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/76-21/768

Claims (5)

(57) [Claims] 1. A semiconductor device comprising: an element forming region in which a MOS transistor is formed as a semiconductor element; and a wiring layer wired so as to contact a predetermined portion of the element forming region and make a substrate contact of the MOS transistor. The wiring layer is made of a material containing an impurity, and an impurity concentration of at least one region in contact with the predetermined portion is lower than an impurity concentration of the predetermined portion of the element formation region. In addition, the semiconductor device is characterized in that the impurity concentration of the other region other than the one region is higher than the impurity concentration of the one region. 2. The semiconductor device according to claim 1, wherein said predetermined portion of said element forming region is a low impurity concentration region. 3. The semiconductor device according to claim 1, wherein the element forming region is a thin film SOI layer. 4. A metal film for reducing an electric resistance value of the wiring layer is provided on a surface of the wiring layer opposite to a side in contact with the element forming region. 4. The semiconductor device according to any one of 1 to 3. 5. The semiconductor device according to claim 4, wherein said metal film contains tungsten.