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JPH01251620A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH01251620A
JPH01251620A JP7946188A JP7946188A JPH01251620A JP H01251620 A JPH01251620 A JP H01251620A JP 7946188 A JP7946188 A JP 7946188A JP 7946188 A JP7946188 A JP 7946188A JP H01251620 A JPH01251620 A JP H01251620A
Authority
JP
Japan
Prior art keywords
semiconductor
interconnections
layer
etching
electrochemical etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7946188A
Other languages
Japanese (ja)
Other versions
JPH0450738B2 (en
Inventor
Tsutomu Ishihara
力 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7946188A priority Critical patent/JPH01251620A/en
Publication of JPH01251620A publication Critical patent/JPH01251620A/en
Publication of JPH0450738B2 publication Critical patent/JPH0450738B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To enable a semiconductor to be worked into desired configurations reliably, by forming a high-concentration diffused layer on the surface of a substrate on which electric elements are to be formed such that the diffused layer reaches at least proximity of a region to be shaped by electrochemical etching, and applying a bias voltage through the high-concentration diffused layer. CONSTITUTION:A scribed region with an appropriate width is provided around each semiconductor chip on the side of an n-type semiconductor layer on which electric elements are to be formed. N<+> diffused layers 2 with high concentration or N<+> interconnections 3 are formed in these regions by ion implantation or by diffusion, and then a protective layer of SiO2 for example is formed on the surface thereof. The N<+> interconnections 3 have functions of helping to apply equal voltage to all the semiconductor chips 1 as well as of decreasing contact resistance generated when they are electrically connected to the outside. The N<+> interconnections 3 are then connected to a power supply and a structure to be produced by etching an N-type semiconductor layer is set at a positive potential through the N<+> interconnections 3 such that the surface thereof is anodically oxidized to produce SiO2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特に電気化学エツチン
グにより形状加工を行う半導体装置の製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which shape processing is performed by electrochemical etching.

〔従来の技術〕[Conventional technology]

電気化学エツチングにより形状加工されるこの種の半導
体装置として、半導体圧力センサや半導体加速度センサ
などのマイクロメカニカルデバイスがある。これらのデ
バイスは、半導体基板に単に電気的素子を形成するだけ
でなく、半導体基板を薄膜ダイアフラム、カンチレバー
(片持梁)などの微細な構造体に形状加工する点に大き
な特徴がある。電気化学エツチングは、該微細構造体の
高精度加工方法として利用されている。
Examples of this type of semiconductor device whose shape is processed by electrochemical etching include micromechanical devices such as semiconductor pressure sensors and semiconductor acceleration sensors. A major feature of these devices is that they not only simply form electrical elements on a semiconductor substrate, but also process the semiconductor substrate into fine structures such as thin film diaphragms and cantilevers. Electrochemical etching is used as a high-precision processing method for the microstructure.

以下、従来の電気化学エツチング法について説明する。The conventional electrochemical etching method will be explained below.

電気化学エツチング法による半導体装置の製造には、通
常、p型半導体基板の片面にエピタキシャル成長法など
によりn型半導体層を積層したn/ρエピウェーハ、又
は拡散法によりpn接合を形成した基板が使用され、該
基板はn型半導体部分が正の電圧にバイアスされた状態
でエツチング溶液中に浸される。このとき、n型半導体
部分に印加される正の電圧は、エツチング溶液中におい
て、陽極酸化反応によって酸化シリコンの膜が生成する
程度の電圧に設定されており、エツチングがp型半導体
面からn型半導体に達したとき、pn接合の界面近傍に
は酸化膜が形成されるので、エツチングは該pn接合界
面で停止する。
In the manufacture of semiconductor devices using the electrochemical etching method, an n/ρ epiwafer in which an n-type semiconductor layer is laminated on one side of a p-type semiconductor substrate by an epitaxial growth method or the like, or a substrate in which a p-n junction is formed by a diffusion method is used. , the substrate is immersed in an etching solution with the n-type semiconductor portion biased to a positive voltage. At this time, the positive voltage applied to the n-type semiconductor portion is set to such a level that a silicon oxide film is generated by the anodic oxidation reaction in the etching solution, and the etching is carried out from the p-type semiconductor surface to the n-type semiconductor. When the etching reaches the semiconductor, an oxide film is formed near the pn junction interface, so etching stops at the pn junction interface.

以上のように、電気化学エツチングでは何らかの方法で
外部から半導体基板に電圧を供給する必要が生じる。第
2図に従来の電気化学エツチングに用いられてきた半導
体基板の略図を示す。図に示したように、従来は、半導
体ウェーハ11の表面の周辺部を取り巻くように、円形
にn+拡散層12による高濃度拡散領域を設け、該高濃
度拡散領域を介してn型半導体部分13に外部から所望
の電圧及び電流を供給していた。
As described above, in electrochemical etching, it is necessary to supply voltage to the semiconductor substrate from the outside by some method. FIG. 2 shows a schematic diagram of a semiconductor substrate that has been used in conventional electrochemical etching. As shown in the figure, conventionally, a high concentration diffusion region made of an n+ diffusion layer 12 is provided in a circular shape so as to surround the peripheral portion of the surface of a semiconductor wafer 11, and an n-type semiconductor portion 13 is formed through the high concentration diffusion region. The desired voltage and current were supplied externally.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、エツチング溶液中でのシリコン酸化膜の生成
は、半導体にかかる電位によって制御される。しかしな
がら、第2図に示した従来の半導体基板の構造において
は、周辺部以外のシリコン部分の電気抵抗が周辺部に比
べてかなり高いため。
Incidentally, the formation of a silicon oxide film in an etching solution is controlled by the potential applied to the semiconductor. However, in the structure of the conventional semiconductor substrate shown in FIG. 2, the electrical resistance of the silicon portion other than the peripheral portion is considerably higher than that of the peripheral portion.

周辺部から中心部に行くにしたがって、基板の電圧は外
部から供給される電圧とは異なった電圧となる。さらに
、エツチングの進行とともにシリコンの膜厚は減少して
ゆくため、周辺部以外のシリコン部分の抵抗値はさらに
大きな値に増加し、外部電源による設定電圧値と各チッ
プ部分における電圧値の差異はさらに顕著となる。この
結果、中心部分はエツチングがpn接合界面に到達する
以前に酸化膜が形成され始め、本来ならエツチングされ
るべきp型シリコンの部分がエツチングされずに残って
しまい、正確な形状加工が行えないという深刻な問題点
があった。
As you go from the periphery to the center, the voltage on the substrate becomes different from the voltage supplied from the outside. Furthermore, as the silicon film thickness decreases as etching progresses, the resistance value of the silicon parts other than the peripheral part increases to an even larger value, and the difference between the voltage value set by the external power supply and the voltage value at each chip part increases. It becomes even more noticeable. As a result, an oxide film begins to form in the central part before the etching reaches the p-n junction interface, and the p-type silicon part that should have been etched remains unetched, making it impossible to process the exact shape. There was a serious problem.

本発明は上記従来技術の問題点を完全に克服し、所望と
する半導体の形状加工が確実に達成できる半導体装置の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that completely overcomes the problems of the prior art described above and can reliably process a desired semiconductor shape.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明は、半導体基板上に電
気的素子を形成するとともに該半導体基板を電気化学エ
ツチング法により所望の形状に加工する半導体装置の製
造方法において、前記電気的素子が形成される側の基板
面に、前記電気化学エツチングにより形状加工される領
域の少なくとも近傍まで達するような高濃度拡散層を形
成し。
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which an electrical element is formed on a semiconductor substrate and the semiconductor substrate is processed into a desired shape by an electrochemical etching method. A high concentration diffusion layer is formed on the substrate surface on the side to be etched, so as to reach at least the vicinity of the region to be shaped by the electrochemical etching.

該高濃度拡散層を介して電気化学エツチングのためのバ
イアス電圧を供給するものである。
A bias voltage for electrochemical etching is supplied through the high concentration diffusion layer.

〔実施例〕〔Example〕

以下、図面に基づいて、本発明に係る半導体装置の製造
方法の一実施例を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例において使用される半導体基
板の構造の一例を示す概略図である。図に示したように
、電気的素子が形成されるn型半導体層側の各半導体チ
ップ1の周辺に、適当な幅のスクライブ領域を設け、そ
こにイオン注入、もしくは拡散法により高濃度の00拡
散層2すなわちN“配線3を形成した後、表面に5i0
1などの保護層を設ける。このN3配線3は、各半導体
チップ1に同じ条件で電圧が加わるようにする機能と、
外部。
FIG. 1 is a schematic diagram showing an example of the structure of a semiconductor substrate used in an embodiment of the present invention. As shown in the figure, a scribe region of an appropriate width is provided around each semiconductor chip 1 on the n-type semiconductor layer side where electrical elements are formed, and a high concentration of 000 After forming the diffusion layer 2, that is, the N" wiring 3, 5i0 is applied to the surface.
A protective layer such as 1 is provided. This N3 wiring 3 has the function of applying voltage to each semiconductor chip 1 under the same conditions,
external.

どの電気的接続の際に生じる接触抵抗を低減する機能を
持っている。その後、このN0配線3を電源に接続し、
エツチングによって作製しようとするn型半導体層から
なる構造物をその表面において陽極酸化が起こり、Si
O□が生成する程度の正の電位にN9配線3を通じて設
定する一方、エツチングによって切り取られるP型半導
体層部分をSiの異方性エツチングが継続して起こるよ
うな電圧に設定し、エチレンジアミン系、KO)l系、
およびヒドラジン系等のシリコン異方性エツチングが可
能な溶液に浸し、90度付近に加温してエツチングを行
う。
It has the function of reducing contact resistance that occurs during any electrical connection. After that, connect this N0 wiring 3 to the power supply,
Anodic oxidation occurs on the surface of the structure made of an n-type semiconductor layer to be fabricated by etching, and Si
While setting the potential through the N9 wiring 3 to a positive potential that generates O KO) l series,
Then, it is immersed in a solution capable of silicon anisotropic etching, such as hydrazine, and etched by heating it to around 90 degrees.

本実施例によれば、エツチングによって作製しようとす
るn型半導体層からなる構造体のどの部分にも印加電圧
が均一にかかるよう、ウェーハ全面にわたりN3配線3
が形成されているので、エツチングによる形状加工はす
べての部分で均一に行われることになり、高い加工精度
と高歩留りを得ることが可能となる。
According to this embodiment, the N3 wiring 3 is applied over the entire surface of the wafer so that the applied voltage is uniformly applied to any part of the structure made of the n-type semiconductor layer to be fabricated by etching.
is formed, the shape processing by etching is performed uniformly on all parts, making it possible to obtain high processing accuracy and high yield.

第1図に示した上記実施例の半導体基板においてはスク
ライブ領域以外の周辺にもN+導電体層が設けられてい
るが、外部電源に対して接続できる領域さえ設けられれ
ば周辺の導電体層はなくても差し支えない。その場合、
従来技術で外周部のN″″層形成に費やしていた領域に
、チップを配置することが可能になり、ウェーハあたり
の歩留りはさらに改良される。
In the semiconductor substrate of the above embodiment shown in FIG. 1, an N+ conductor layer is also provided in the periphery other than the scribe area, but as long as a region that can be connected to an external power source is provided, the peripheral conductor layer can be You can do without it. In that case,
Chips can now be placed in the area that was previously spent forming N'''' layers on the periphery, further improving the yield per wafer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、電気化学エツチン
グによって作製しようとする一導電型半導体層からなる
構造体のどの部分にも印加電圧が均一にかかるよう、半
導体基板全面にわたりN4配線が形成されるので、電気
化学エツチングによる形状加工はすべての部分で均一に
行われることになり、高い加工精度と高歩留りを得るこ
とができる。
As explained above, according to the present invention, the N4 wiring is formed over the entire surface of the semiconductor substrate so that an applied voltage can be uniformly applied to any part of the structure made of one conductivity type semiconductor layer to be fabricated by electrochemical etching. Therefore, shape processing by electrochemical etching is uniformly performed on all parts, and high processing accuracy and high yield can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例において電気化学エツチング
に使用される半導体基板の一例を示す正面図、第2図は
従来の電気化学エツチングに使用されていた半導体基板
の正面図である。
FIG. 1 is a front view showing an example of a semiconductor substrate used for electrochemical etching in an embodiment of the present invention, and FIG. 2 is a front view of a semiconductor substrate used for conventional electrochemical etching.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板上に電気的素子を形成するとともに該半
導体基板を電気化学エッチング法により所望の形状に加
工する半導体装置の製造方法において、前記電気的素子
が形成される側の基板面に、前記電気化学エッチングに
より形状加工される領域の少なくとも近傍まで達するよ
うな高濃度拡散層を形成し、該高濃度拡散層を介して電
気化学エッチングのためのバイアス電圧を供給すること
を特徴とする半導体装置の製造方法。
1. In a method for manufacturing a semiconductor device in which an electrical element is formed on a semiconductor substrate and the semiconductor substrate is processed into a desired shape by electrochemical etching, the above-mentioned A semiconductor device characterized by forming a highly concentrated diffusion layer that reaches at least the vicinity of a region to be shaped by electrochemical etching, and supplying a bias voltage for electrochemical etching through the highly concentrated diffusion layer. manufacturing method.
JP7946188A 1988-03-30 1988-03-30 Manufacture of semiconductor device Granted JPH01251620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7946188A JPH01251620A (en) 1988-03-30 1988-03-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7946188A JPH01251620A (en) 1988-03-30 1988-03-30 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPH01251620A true JPH01251620A (en) 1989-10-06
JPH0450738B2 JPH0450738B2 (en) 1992-08-17

Family

ID=13690520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7946188A Granted JPH01251620A (en) 1988-03-30 1988-03-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01251620A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370770A (en) * 1976-12-07 1978-06-23 Nec Corp Production of schottky barrier gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370770A (en) * 1976-12-07 1978-06-23 Nec Corp Production of schottky barrier gate type field effect transistor

Also Published As

Publication number Publication date
JPH0450738B2 (en) 1992-08-17

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